debugging simulation

general/macros353.v

@@ -82,7 +82,7 @@ parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
     assign	QR= ram[AR];
 endmodule
 
-// Fixing Xilinx SLR16_x
+// Modifying Xilinx SLR16_x to better simulate real hardware
 module SRL16_MOD #(
     parameter INIT = 16'h0000,
     parameter INVERT = 0 // *_1 - invert
@@ -100,9 +100,10 @@ module SRL16_MOD #(
     wire        clk_;
     wire  [3:0] a = {A3, A2, A1, A0};
 
+    assign Q = (|data) ? ((&data) ? 1'b1 : data[a]) :  1'b0 ;
 
-    assign Q = (data == 16'h0) ? 1'b0 :
-               ((data == 16'hffff) ? 1'b1 : data[a]);
+//    assign Q = (data == 16'h0) ? 1'b0 :
+//               ((data == 16'hffff) ? 1'b1 : data[a]);
     assign clk_ = INVERT? (~CLK) : CLK;
 
     initial

memctrl353/sdseq353.v

@@ -186,7 +186,6 @@ module sdseq (clk0,	// global clock 75-100MHz (hope to get to 120MHz with Sparta
      next <= prenext_refr || prenext_wr || (!drun_wr && pre_next_old); // add m0 and refr here too
      decLeft <= (prenext_m1s || prenext_m1d || prenext_m0); // add m0 and refr here too
      if (first) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
-///AF2015 - revert:    	 if (first || rst) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
      else if (decLeft)   left[4:0] <= left[4:0] -1;
    end
 

sensor/sensorpads353.v

@@ -31,22 +31,22 @@
 module	sensorpads (/// interface to DCM
                      sclk,       // system clock, @negedge
                      cmd,        // [6:0] command for phase adjustment @ negedge (sclk) MSB - reset pclk2x DCM
-							wcmd,       // write command@ negedge (slck)
+					 wcmd,       // write command@ negedge (slck)
                      dcm_done,   // DCM command done
                      dcm_status, // [7:0] output dcm status (bit 1 - dcm clkin stopped)
                      dcm_locked, //   DCM locked
-							clk_sel,    // 0 - use clk, 1 - sensor dclk (bpf pad) for DCM input (if dclkmode - use clk if 0)
-							hact_length,// [13:0] WOI width-1 (to overwrite sensor HACT duration)
+					 clk_sel,    // 0 - use clk, 1 - sensor dclk (bpf pad) for DCM input (if dclkmode - use clk if 0)
+					 hact_length,// [13:0] WOI width-1 (to overwrite sensor HACT duration)
                      hact_regen, // 0 - use hact from sensor, 1 - regenerate using hact_lengh
                      clk,        //pixel clock, posedge
                      pclk2x,     // output - twice pixel clock
                      vact,       // VACT pad, inout
-							hact,       // HACT pad, inout
-							bpf,        // BPF  pad, inout
-							pxd,        // [11:0] pads {PXD [9:0],CNVCLK, CNVSYNC} inout
-							mrst,       // MRST pad, inoput (input in JTAG external FPGA programming mode)
-							arst,       // ARST pad, output (output in JTAG external FPGA programming mode)
-							aro,        // ARO pad, output
+					 hact,       // HACT pad, inout
+					 bpf,        // BPF  pad, inout
+					 pxd,        // [11:0] pads {PXD [9:0],CNVCLK, CNVSYNC} inout
+					 mrst,       // MRST pad, inoput (input in JTAG external FPGA programming mode)
+					 arst,       // ARST pad, output (output in JTAG external FPGA programming mode)
+					 aro,        // ARO pad, output
                      dclkmode,   // input 0 - DCLK is clock to sensor, 1 - combined sync from sensor (like 10347)
                      pxd14,      // input 1 - use {vact,hact} as 2 LSB in 14-bit data
                      debug, // 2-bit debug mode input