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Commit aafa6d1d authored by Andrey Filippov's avatar Andrey Filippov
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debugging simulation

parent d6e9be6b
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Showing with 1149 additions and 667 deletions
general/macros353.v
View file @ aafa6d1d
......@@ -82,7 +82,7 @@ parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
assign QR= ram[AR];
endmodule
// Fixing Xilinx SLR16_x
// Modifying Xilinx SLR16_x to better simulate real hardware
module SRL16_MOD #(
parameter INIT = 16'h0000,
parameter INVERT = 0 // *_1 - invert
......@@ -100,9 +100,10 @@ module SRL16_MOD #(
wire clk_;
wire [3:0] a = {A3, A2, A1, A0};
assign Q = (|data) ? ((&data) ? 1'b1 : data[a]) : 1'b0 ;
assign Q = (data == 16'h0) ? 1'b0 :
((data == 16'hffff) ? 1'b1 : data[a]);
// assign Q = (data == 16'h0) ? 1'b0 :
// ((data == 16'hffff) ? 1'b1 : data[a]);
assign clk_ = INVERT? (~CLK) : CLK;
initial
......
memctrl353/sdseq353.v
View file @ aafa6d1d
......@@ -186,7 +186,6 @@ module sdseq (clk0, // global clock 75-100MHz (hope to get to 120MHz with Sparta
next <= prenext_refr || prenext_wr || (!drun_wr && pre_next_old); // add m0 and refr here too
decLeft <= (prenext_m1s || prenext_m1d || prenext_m0); // add m0 and refr here too
if (first) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
///AF2015 - revert: if (first || rst) left[4:0] <= (mode)? 5'h14:((param[4:0]==5'b0)?5'h1f:param[4:0]);
else if (decLeft) left[4:0] <= left[4:0] -1;
end
......
sensor/sensorpads353.v
View file @ aafa6d1d
......@@ -31,22 +31,22 @@
module sensorpads (/// interface to DCM
sclk, // system clock, @negedge
cmd, // [6:0] command for phase adjustment @ negedge (sclk) MSB - reset pclk2x DCM
wcmd, // write command@ negedge (slck)
wcmd, // write command@ negedge (slck)
dcm_done, // DCM command done
dcm_status, // [7:0] output dcm status (bit 1 - dcm clkin stopped)
dcm_locked, // DCM locked
clk_sel, // 0 - use clk, 1 - sensor dclk (bpf pad) for DCM input (if dclkmode - use clk if 0)
hact_length,// [13:0] WOI width-1 (to overwrite sensor HACT duration)
clk_sel, // 0 - use clk, 1 - sensor dclk (bpf pad) for DCM input (if dclkmode - use clk if 0)
hact_length,// [13:0] WOI width-1 (to overwrite sensor HACT duration)
hact_regen, // 0 - use hact from sensor, 1 - regenerate using hact_lengh
clk, //pixel clock, posedge
pclk2x, // output - twice pixel clock
vact, // VACT pad, inout
hact, // HACT pad, inout
bpf, // BPF pad, inout
pxd, // [11:0] pads {PXD [9:0],CNVCLK, CNVSYNC} inout
mrst, // MRST pad, inoput (input in JTAG external FPGA programming mode)
arst, // ARST pad, output (output in JTAG external FPGA programming mode)
aro, // ARO pad, output
hact, // HACT pad, inout
bpf, // BPF pad, inout
pxd, // [11:0] pads {PXD [9:0],CNVCLK, CNVSYNC} inout
mrst, // MRST pad, inoput (input in JTAG external FPGA programming mode)
arst, // ARST pad, output (output in JTAG external FPGA programming mode)
aro, // ARO pad, output
dclkmode, // input 0 - DCLK is clock to sensor, 1 - combined sync from sensor (like 10347)
pxd14, // input 1 - use {vact,hact} as 2 LSB in 14-bit data
debug, // 2-bit debug mode input
......
x353_1.sav
View file @ aafa6d1d
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Mon Jul 27 06:55:08 2015
[*] Mon Jul 27 18:34:40 2015
[*]
[dumpfile] "/home/andrey/git/x353/simulation/x353_1-20150727004619246.lxt"
[dumpfile_mtime] "Mon Jul 27 06:47:53 2015"
[dumpfile_size] 49089165
[dumpfile] "/home/andrey/git/x353/simulation/x353_1-20150727121507816.lxt"
[dumpfile_mtime] "Mon Jul 27 18:19:16 2015"
[dumpfile_size] 132295306
[savefile] "/home/andrey/git/x353/x353_1.sav"
[timestart] 0
[size] 1823 1173
[size] 1823 1180
[pos] 1917 0
*-25.064463 110293750 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-25.641851 6500000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] testbench353.
[treeopen] testbench353.i_x353.
[treeopen] testbench353.i_x353.i_mcontr.
[treeopen] testbench353.i_x353.i_sensorpads.i_sensor_phase.
[treeopen] testbench353.i_x353.i_sysinterface.i_we.
[sst_width] 335
......@@ -21,9 +20,405 @@
[sst_vpaned_height] 430
@820
testbench353.TEST_TITLE[639:0]
@800200
-sensor_in
@22
testbench353.PXD[11:0]
@28
testbench353.VACT[0]
testbench353.VACT1CYCLE[0]
testbench353.i_x353.HACT[0]
testbench353.MRST[0]
testbench353.ARST[0]
testbench353.ARO[0]
testbench353.SCL0[0]
testbench353.SDA0[0]
@1000200
-sensor_in
@800200
-debug_sensorpads
@28
testbench353.i_x353.i_sensorpads.iaro[0]
testbench353.i_x353.cb_sensor_trigger[0]
testbench353.i_x353.iaro[0]
testbench353.i_x353.sensor_trigger[0]
testbench353.i_x353.en_vacts_free[0]
testbench353.i_x353.vact_overdue[0]
@1000200
-debug_sensorpads
@200
-
@800200
-twelve_ios
@c00023
testbench353.EXT[11:0]
@28
(0)testbench353.EXT[11:0]
(1)testbench353.EXT[11:0]
(2)testbench353.EXT[11:0]
(3)testbench353.EXT[11:0]
(4)testbench353.EXT[11:0]
(5)testbench353.EXT[11:0]
(6)testbench353.EXT[11:0]
(7)testbench353.EXT[11:0]
(8)testbench353.EXT[11:0]
(9)testbench353.EXT[11:0]
(10)testbench353.EXT[11:0]
(11)testbench353.EXT[11:0]
@1401201
-group_end
@28
testbench353.external_sync_line[0]
@800200
-iopins_9
@28
testbench353.i_x353.i_iopins9.GTS[0]
testbench353.i_x353.i_iopins9.IO[0]
testbench353.i_x353.i_iopins9.I[0]
testbench353.i_x353.i_iopins9.O[0]
testbench353.i_x353.i_iopins9.T[0]
testbench353.i_x353.i_iopins9.ts[0]
@1000200
-iopins_9
@c00200
-iopins_8
@28
testbench353.i_x353.i_iopins8.GTS[0]
testbench353.i_x353.i_iopins8.IO[0]
testbench353.i_x353.i_iopins8.I[0]
testbench353.i_x353.i_iopins8.O[0]
testbench353.i_x353.i_iopins8.T[0]
testbench353.i_x353.i_iopins8.ts[0]
@1401200
-iopins_8
@c00022
testbench353.i_x353.io_t[11:0]
@28
(0)testbench353.i_x353.io_t[11:0]
(1)testbench353.i_x353.io_t[11:0]
(2)testbench353.i_x353.io_t[11:0]
(3)testbench353.i_x353.io_t[11:0]
(4)testbench353.i_x353.io_t[11:0]
(5)testbench353.i_x353.io_t[11:0]
(6)testbench353.i_x353.io_t[11:0]
(7)testbench353.i_x353.io_t[11:0]
(8)testbench353.i_x353.io_t[11:0]
(9)testbench353.i_x353.io_t[11:0]
(10)testbench353.i_x353.io_t[11:0]
(11)testbench353.i_x353.io_t[11:0]
@1401200
-group_end
@800022
testbench353.i_x353.EXT[11:0]
@28
(0)testbench353.i_x353.EXT[11:0]
(1)testbench353.i_x353.EXT[11:0]
(2)testbench353.i_x353.EXT[11:0]
(3)testbench353.i_x353.EXT[11:0]
(4)testbench353.i_x353.EXT[11:0]
(5)testbench353.i_x353.EXT[11:0]
(6)testbench353.i_x353.EXT[11:0]
(7)testbench353.i_x353.EXT[11:0]
(8)testbench353.i_x353.EXT[11:0]
(9)testbench353.i_x353.EXT[11:0]
(10)testbench353.i_x353.EXT[11:0]
(11)testbench353.i_x353.EXT[11:0]
@1001200
-group_end
@22
testbench353.i_x353.io_do[11:0]
@c00022
testbench353.i_x353.io_pins[11:0]
@28
(0)testbench353.i_x353.io_pins[11:0]
(1)testbench353.i_x353.io_pins[11:0]
(2)testbench353.i_x353.io_pins[11:0]
(3)testbench353.i_x353.io_pins[11:0]
(4)testbench353.i_x353.io_pins[11:0]
(5)testbench353.i_x353.io_pins[11:0]
(6)testbench353.i_x353.io_pins[11:0]
(7)testbench353.i_x353.io_pins[11:0]
(8)testbench353.i_x353.io_pins[11:0]
(9)testbench353.i_x353.io_pins[11:0]
(10)testbench353.i_x353.io_pins[11:0]
(11)testbench353.i_x353.io_pins[11:0]
@1401200
-group_end
@28
testbench353.i_x353.da_io_pins[0]
@22
testbench353.i_x353.i_twelve_ios.ch_en[3:0]
@28
testbench353.i_x353.i_twelve_ios.cr_wen[0]
@22
testbench353.i_x353.i_twelve_ios.da[11:0]
testbench353.i_x353.i_twelve_ios.da_en[11:0]
testbench353.i_x353.i_twelve_ios.da_en_m[11:0]
testbench353.i_x353.i_twelve_ios.db[11:0]
testbench353.i_x353.i_twelve_ios.db_en[11:0]
testbench353.i_x353.i_twelve_ios.db_en_m[11:0]
testbench353.i_x353.i_twelve_ios.dc[11:0]
testbench353.i_x353.i_twelve_ios.dc_en[11:0]
testbench353.i_x353.i_twelve_ios.dc_en_m[11:0]
testbench353.i_x353.i_twelve_ios.di[15:0]
testbench353.i_x353.i_twelve_ios.did[31:0]
testbench353.i_x353.i_twelve_ios.ds[11:0]
testbench353.i_x353.i_twelve_ios.ds_en[11:0]
testbench353.i_x353.i_twelve_ios.ds_en_m[11:0]
testbench353.i_x353.i_twelve_ios.io_do[11:0]
testbench353.i_x353.i_twelve_ios.io_t[11:0]
@28
testbench353.i_x353.i_twelve_ios.pre_wen[0]
testbench353.i_x353.i_twelve_ios.pre_wen_d[0]
testbench353.i_x353.i_twelve_ios.sclk[0]
@1000200
-twelve_ios
@800200
-debug_camsync
@28
testbench353.i_x353.i_camsync.trigger_condition[0]
@800022
testbench353.i_x353.i_camsync.gpio_in[11:0]
@28
(0)testbench353.i_x353.i_camsync.gpio_in[11:0]
(1)testbench353.i_x353.i_camsync.gpio_in[11:0]
(2)testbench353.i_x353.i_camsync.gpio_in[11:0]
(3)testbench353.i_x353.i_camsync.gpio_in[11:0]
(4)testbench353.i_x353.i_camsync.gpio_in[11:0]
(5)testbench353.i_x353.i_camsync.gpio_in[11:0]
(6)testbench353.i_x353.i_camsync.gpio_in[11:0]
(7)testbench353.i_x353.i_camsync.gpio_in[11:0]
(8)testbench353.i_x353.i_camsync.gpio_in[11:0]
(9)testbench353.i_x353.i_camsync.gpio_in[11:0]
(10)testbench353.i_x353.i_camsync.gpio_in[11:0]
(11)testbench353.i_x353.i_camsync.gpio_in[11:0]
@1001200
-group_end
@c00022
testbench353.i_x353.i_camsync.input_pattern[11:0]
@28
(0)testbench353.i_x353.i_camsync.input_pattern[11:0]
(1)testbench353.i_x353.i_camsync.input_pattern[11:0]
(2)testbench353.i_x353.i_camsync.input_pattern[11:0]
(3)testbench353.i_x353.i_camsync.input_pattern[11:0]
(4)testbench353.i_x353.i_camsync.input_pattern[11:0]
(5)testbench353.i_x353.i_camsync.input_pattern[11:0]
(6)testbench353.i_x353.i_camsync.input_pattern[11:0]
(7)testbench353.i_x353.i_camsync.input_pattern[11:0]
(8)testbench353.i_x353.i_camsync.input_pattern[11:0]
(9)testbench353.i_x353.i_camsync.input_pattern[11:0]
(10)testbench353.i_x353.i_camsync.input_pattern[11:0]
(11)testbench353.i_x353.i_camsync.input_pattern[11:0]
@1401200
-group_end
@c00022
testbench353.i_x353.i_camsync.input_use[11:0]
@28
(0)testbench353.i_x353.i_camsync.input_use[11:0]
(1)testbench353.i_x353.i_camsync.input_use[11:0]
(2)testbench353.i_x353.i_camsync.input_use[11:0]
(3)testbench353.i_x353.i_camsync.input_use[11:0]
(4)testbench353.i_x353.i_camsync.input_use[11:0]
(5)testbench353.i_x353.i_camsync.input_use[11:0]
(6)testbench353.i_x353.i_camsync.input_use[11:0]
(7)testbench353.i_x353.i_camsync.input_use[11:0]
(8)testbench353.i_x353.i_camsync.input_use[11:0]
(9)testbench353.i_x353.i_camsync.input_use[11:0]
(10)testbench353.i_x353.i_camsync.input_use[11:0]
(11)testbench353.i_x353.i_camsync.input_use[11:0]
@1401200
-group_end
@28
testbench353.i_x353.i_camsync.out_data[0]
@22
testbench353.EXT[11:0]
@1000200
-debug_camsync
@c00200
-camsync
@22
testbench353.i_x353.i_camsync.bit_length[7:0]
testbench353.i_x353.i_camsync.bit_length_plus1[7:0]
testbench353.i_x353.i_camsync.bit_length_short[7:0]
testbench353.i_x353.i_camsync.bit_rcv_counter[6:0]
testbench353.i_x353.i_camsync.bit_rcv_duration[7:0]
@28
testbench353.i_x353.i_camsync.bit_rcv_duration_zero[0]
@22
testbench353.i_x353.i_camsync.bit_snd_counter[5:0]
testbench353.i_x353.i_camsync.bit_snd_duration[7:0]
@28
testbench353.i_x353.i_camsync.bit_snd_duration_zero[0]
@22
testbench353.i_x353.i_camsync.di[15:0]
testbench353.i_x353.i_camsync.did[31:0]
testbench353.i_x353.i_camsync.dly_cntr[31:0]
@28
testbench353.i_x353.i_camsync.dly_cntr_run[0]
testbench353.i_x353.i_camsync.dly_cntr_run_d[0]
@22
testbench353.i_x353.i_camsync.gpio_active[11:0]
testbench353.i_x353.i_camsync.gpio_in[11:0]
testbench353.i_x353.i_camsync.gpio_out[11:0]
testbench353.i_x353.i_camsync.gpio_out_en[11:0]
@28
testbench353.i_x353.i_camsync.high_zero[0]
@22
testbench353.i_x353.i_camsync.input_dly[31:0]
testbench353.i_x353.i_camsync.input_pattern[11:0]
testbench353.i_x353.i_camsync.input_use[11:0]
@28
testbench353.i_x353.i_camsync.input_use_intern[0]
testbench353.i_x353.i_camsync.out_data[0]
testbench353.i_x353.i_camsync.outsync[0]
testbench353.i_x353.i_camsync.overdue[0]
testbench353.i_x353.i_camsync.pclk[0]
testbench353.i_x353.i_camsync.pre_input_use_intern[0]
@22
testbench353.i_x353.i_camsync.pre_period[31:0]
@28
testbench353.i_x353.i_camsync.pre_rcv_error[0]
testbench353.i_x353.i_camsync.pre_set_bit[0]
testbench353.i_x353.i_camsync.pre_set_period[0]
testbench353.i_x353.i_camsync.pre_start0[0]
testbench353.i_x353.i_camsync.pre_start_out_pulse[0]
testbench353.i_x353.i_camsync.pre_wen[0]
testbench353.i_x353.i_camsync.pre_wend[0]
testbench353.i_x353.i_camsync.rcv_done[0]
testbench353.i_x353.i_camsync.rcv_done_rq[0]
testbench353.i_x353.i_camsync.rcv_done_rq_d[0]
testbench353.i_x353.i_camsync.rcv_error[0]
testbench353.i_x353.i_camsync.rcv_run[0]
testbench353.i_x353.i_camsync.rcv_run_d[0]
testbench353.i_x353.i_camsync.rcv_run_or_deaf[0]
testbench353.i_x353.i_camsync.rep_en[0]
@22
testbench353.i_x353.i_camsync.repeat_period[31:0]
@28
testbench353.i_x353.i_camsync.restart[0]
@22
testbench353.i_x353.i_camsync.restart_cntr[31:0]
@28
testbench353.i_x353.i_camsync.restart_cntr_run[1:0]
testbench353.i_x353.i_camsync.sclk[0]
testbench353.i_x353.i_camsync.set_bit[0]
testbench353.i_x353.i_camsync.set_period[0]
@22
testbench353.i_x353.i_camsync.sr_rcv_first[31:0]
testbench353.i_x353.i_camsync.sr_rcv_second[31:0]
testbench353.i_x353.i_camsync.sr_snd_first[31:0]
testbench353.i_x353.i_camsync.sr_snd_second[31:0]
@28
testbench353.i_x353.i_camsync.start0[0]
testbench353.i_x353.i_camsync.start[0]
testbench353.i_x353.i_camsync.start_d[0]
testbench353.i_x353.i_camsync.start_dly[0]
testbench353.i_x353.i_camsync.start_en[0]
testbench353.i_x353.i_camsync.start_out_pulse[0]
testbench353.i_x353.i_camsync.start_pclk16[0]
testbench353.i_x353.i_camsync.start_pclk[2:0]
testbench353.i_x353.i_camsync.start_to_pclk[0]
testbench353.i_x353.i_camsync.testmode[0]
testbench353.i_x353.i_camsync.trigger1[0]
testbench353.i_x353.i_camsync.trigger1_dly16[0]
testbench353.i_x353.i_camsync.trigger[0]
testbench353.i_x353.i_camsync.trigger_condition[0]
testbench353.i_x353.i_camsync.trigger_condition_d[0]
testbench353.i_x353.i_camsync.trigger_condition_filtered[0]
@22
testbench353.i_x353.i_camsync.trigger_filter_cntr[6:0]
@28
testbench353.i_x353.i_camsync.triggered_mode[0]
testbench353.i_x353.i_camsync.triggered_mode_pclk[0]
testbench353.i_x353.i_camsync.trigrst[0]
testbench353.i_x353.i_camsync.ts_external[0]
testbench353.i_x353.i_camsync.ts_external_pclk[0]
testbench353.i_x353.i_camsync.ts_pre_stb[2:0]
@22
testbench353.i_x353.i_camsync.ts_rcv_sec[31:0]
testbench353.i_x353.i_camsync.ts_rcv_usec[19:0]
@28
testbench353.i_x353.i_camsync.ts_snap[0]
testbench353.i_x353.i_camsync.ts_snd_en[0]
testbench353.i_x353.i_camsync.ts_snd_en_pclk[0]
@22
testbench353.i_x353.i_camsync.ts_snd_sec[31:0]
testbench353.i_x353.i_camsync.ts_snd_usec[19:0]
@28
testbench353.i_x353.i_camsync.ts_stb[0]
testbench353.i_x353.i_camsync.ts_stb_pclk[0]
testbench353.i_x353.i_camsync.wa[1:0]
testbench353.i_x353.i_camsync.wad[1:0]
@22
testbench353.i_x353.i_camsync.wen[3:0]
@1401200
-camsync
@c00200
-sensorpads
@28
testbench353.i_x353.i_sensorpads.aro[0]
testbench353.i_x353.i_sensorpads.arst[0]
testbench353.i_x353.i_sensorpads.bpf[0]
testbench353.i_x353.i_sensorpads.clk[0]
testbench353.i_x353.i_sensorpads.clk_sel[0]
@22
testbench353.i_x353.i_sensorpads.cmd[6:0]
@28
testbench353.i_x353.i_sensorpads.cnvctl[1:0]
testbench353.i_x353.i_sensorpads.cnven[0]
testbench353.i_x353.i_sensorpads.dclk[0]
testbench353.i_x353.i_sensorpads.dclkmode[0]
testbench353.i_x353.i_sensorpads.dcm_done[0]
testbench353.i_x353.i_sensorpads.dcm_drst[2:0]
testbench353.i_x353.i_sensorpads.dcm_locked[0]
testbench353.i_x353.i_sensorpads.dcm_rst[0]
testbench353.i_x353.i_sensorpads.dcm_rst_cmd[0]
@22
testbench353.i_x353.i_sensorpads.dcm_status[7:0]
@28
testbench353.i_x353.i_sensorpads.debug[1:0]
testbench353.i_x353.i_sensorpads.en_vacts[0]
testbench353.i_x353.i_sensorpads.fifo_clkin[0]
testbench353.i_x353.i_sensorpads.force_senspgm[0]
testbench353.i_x353.i_sensorpads.hact[0]
@22
testbench353.i_x353.i_sensorpads.hact_length[13:0]
@28
testbench353.i_x353.i_sensorpads.hact_regen[0]
testbench353.i_x353.i_sensorpads.iaro[0]
testbench353.i_x353.i_sensorpads.iarst[0]
testbench353.i_x353.i_sensorpads.idclk[0]
testbench353.i_x353.i_sensorpads.ihact[0]
testbench353.i_x353.i_sensorpads.imrst[0]
@22
testbench353.i_x353.i_sensorpads.ipxd[15:0]
@28
testbench353.i_x353.i_sensorpads.mrst[0]
testbench353.i_x353.i_sensorpads.pclk2x[0]
testbench353.i_x353.i_sensorpads.pclk2xi[0]
testbench353.i_x353.i_sensorpads.pxd14[0]
@22
testbench353.i_x353.i_sensorpads.pxd[11:0]
testbench353.i_x353.i_sensorpads.pxdi[11:0]
@28
testbench353.i_x353.i_sensorpads.sclk[0]
testbench353.i_x353.i_sensorpads.sens_clk[0]
testbench353.i_x353.i_sensorpads.senspgm[0]
testbench353.i_x353.i_sensorpads.senspgmin[0]
testbench353.i_x353.i_sensorpads.vact[0]
testbench353.i_x353.i_sensorpads.vacts[0]
testbench353.i_x353.i_sensorpads.wcmd[0]
testbench353.i_x353.i_sensorpads.xfpgadone[0]
testbench353.i_x353.i_sensorpads.xfpgaprog[0]
testbench353.i_x353.i_sensorpads.xfpgatck[0]
testbench353.i_x353.i_sensorpads.xfpgatdi[0]
testbench353.i_x353.i_sensorpads.xfpgatdo[0]
testbench353.i_x353.i_sensorpads.xfpgatms[0]
testbench353.i_x353.i_sensorpads.xpgmen[0]
testbench353.i_x353.i_sensorpads.xpgmen_d[1:0]
@1401200
-sensorpads
@800200
-sdram
@22
testbench353.i_x353.SDA[14:0]
......@@ -385,6 +780,66 @@ testbench353.i_x353.i_mcontr.i_channelRequest0.wrempty[0]
@1401200
-chnrq0
@c00200
-chnrq1
@28
testbench353.i_x353.i_mcontr.i_channelRequest1.ackn[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.cntrsInit[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.cntrsValid[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.current_wnr[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.done[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.eclk[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.ecnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest1.enXfer[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.en_done[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.iclk[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.icnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest1.init[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.next_ecnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest1.next_icnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest1.next_rcnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest1.rcnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest1.rdy[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.rdy_async[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.ready_off[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.rqInit[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.rq[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.rst[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.start[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.wnr[0]
testbench353.i_x353.i_mcontr.i_channelRequest1.wrempty[0]
@1401200
-chnrq1
@c00200
-chnrq2
@28
testbench353.i_x353.i_mcontr.i_channelRequest2.ackn[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.cntrsInit[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.cntrsValid[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.current_wnr[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.done[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.eclk[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.ecnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest2.enXfer[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.en_done[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.iclk[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.icnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest2.init[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.next_ecnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest2.next_icnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest2.next_rcnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest2.rcnt[2:0]
testbench353.i_x353.i_mcontr.i_channelRequest2.rdy[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.rdy_async[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.ready_off[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.rqInit[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.rq[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.rst[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.start[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.wnr[0]
testbench353.i_x353.i_mcontr.i_channelRequest2.wrempty[0]
@1401200
-chnrq2
@c00200
-chnrq3
@28
testbench353.i_x353.i_mcontr.i_channelRequest3.ackn[0]
......@@ -561,7 +1016,7 @@ testbench353.i_x353.i_mcontr.i_descrproc.updSuspXfer[0]
-descrproc
@200
-
@800200
@c00200
-debug_memcntr
@28
testbench353.i_x353.i_mcontr.i_sdseq.clk0[0]
......@@ -594,15 +1049,15 @@ testbench353.i_x353.i_mcontr.i_sdseq.prenext_m0r[0]
testbench353.i_x353.i_mcontr.i_sdseq.start_m0r[0]
testbench353.i_x353.i_mcontr.i_sdseq.prenext_m0w1[0]
testbench353.i_x353.i_mcontr.i_sdseq.start_m0w[0]
@23
@22
testbench353.i_x353.i_mcontr.i_sdseq.param[5:0]
@28
testbench353.i_x353.i_mcontr.i_sdseq.continue_m0[0]
@1000200
@1401200
-debug_memcntr
@200
-
@800200
@c00200
-sdseq
@28
testbench353.i_x353.i_mcontr.i_sdseq.chsel[1:0]
......@@ -698,7 +1153,7 @@ testbench353.i_x353.i_mcontr.i_sdseq.start_m1[0]
testbench353.i_x353.i_mcontr.i_sdseq.startf_m1[0]
testbench353.i_x353.i_mcontr.i_sdseq.wnr[0]
testbench353.i_x353.i_mcontr.i_sdseq.xfer[0]
@1000200
@1401200
-sdseq
[pattern_trace] 1
[pattern_trace] 0
x353_1.tf
View file @ aafa6d1d
......@@ -361,7 +361,8 @@ wire SYS_SDCLKI = 1'bx; // not tested
wire BRIN = 1'bx; // not tested
/// connect external sync
assign EXT[8]=EXT[9];
assign #10 EXT[8] = EXT[9];
///AF2015: with old simulator it did work w/o delay, with current EXT[9] was forced to be 1'bz (same as [8]) !!!!
wire external_sync_line=~EXT[9]; //SuppressThisWarning Veditor UNUSED
x353 i_x353 (
......@@ -553,7 +554,7 @@ defparam i_sensor12bits.trigdly = TRIG_LINES; // delay between trigger input a
`ifdef TEST_IMU
`include "imu_sim_include.vh"
`endif
#200000;
#600000;
TEST_TITLE = "FIRST_INIT_DONE";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
$finish;
......@@ -1244,6 +1245,8 @@ task program_compressor;
read256_ch3;
repeat (1) cpu_wr(8,'h2); // decrease phase
read256_ch3;
TEST_TITLE = "done_read_tests";
$display("===================== TEST_%s ========================= @%t",TEST_TITLE,$time);
`endif
///TODO: There is a mixture of several test below, clean them up
......@@ -1297,647 +1300,9 @@ task program_compressor;
end
// Some tasks unused from the include, also VDT does not recognize that $readmem assignes values
`include "x353_sim_tasks_include.vh"
// CPU tasks
parameter CPU_C_A = 3;
parameter CPU_A_WL = 10;
parameter CPU_A_RL = 10; //10;
parameter CPU_RL_RH = 10; //10;
parameter CPU_WL_D = 4;
parameter CPU_D_WH = 16;
parameter CPU_WH_A = 2;
parameter CPU_WH_D = 4;
parameter CPU_RH_A = 2;
task dma_en;
input chn; // DMA channel (0/1)
input d; // 0 - disable, 1 - enable;
begin
if (chn) BUS_EN[BUSOP_DMA_1] = d;
else BUS_EN[BUSOP_DMA_0] = d;
end
endtask
task dma_rd;
input [ 7:0] ia;
input [ 7:0] burst;
integer i;
begin
wait (DREQ); // in this model CPU will not abanon DMA even if DREQ is reset before granted
wait (~BUS[BUSOP_DMA_0]);
BUS_RQ[BUSOP_DMA_0] = 1;
wait (BUS[BUSOP_DMA_0]);
BUS_RQ[BUSOP_DMA_0] = 0;
wait (CPU_CLK); wait (~CPU_CLK); wait (CPU_CLK);
for (i = 0; i < burst; i = i+1) begin
wait (~CPU_CLK); wait (CPU_CLK);
// once per burst
#(CPU_C_A) A[7:0] = ia[7:0];
DACK = 1'b1;
CE = 1'b0;
#(CPU_A_RL) OE = 1'b0;
#(CPU_RL_RH) DMA_DI = D[31:0];
OE = 1'b1;
end
#(CPU_RH_A) A[7:0] = 8'bx;
CE = 1'b1;
DACK = 1'b0;
BUS[BUSOP_DMA_0] =0;
// delay to let data from the CPU be written to the SDRAM
for (i = 0; i < burst; i = i+1) begin
wait (~CPU_CLK); wait (CPU_CLK);
wait (~CPU_CLK); wait (CPU_CLK);
end
end
endtask
task dma_rd_1;
input [ 7:0] ia;
input [ 7:0] burst;
integer i;
begin
wait (DREQ1); // in this model CPU will not abanon DMA even if DREQ is reset before granted
wait (~BUS[BUSOP_DMA_1]);
BUS_RQ[BUSOP_DMA_1] = 1;
wait (BUS[BUSOP_DMA_1]);
BUS_RQ[BUSOP_DMA_1] = 0;
wait (CPU_CLK); wait (~CPU_CLK); wait (CPU_CLK);
for (i = 0; i < burst; i = i+1) begin
wait (~CPU_CLK); wait (CPU_CLK);
// once per burst
#(CPU_C_A) A[7:0] = ia[7:0];
DACK1 = 1;
CE = 0;
#(CPU_A_RL) OE = 0;
#(CPU_RL_RH) DMA_DI_1 = D[31:0];
OE = 1;
end
#(CPU_RH_A) A[7:0] = 8'bx;
CE = 1;
DACK1 = 0;
BUS[BUSOP_DMA_1] =0;
// delay to let data from the CPU be written to the SDRAM
for (i = 0; i < burst; i = i+1) begin
wait (~CPU_CLK); wait (CPU_CLK);
wait (~CPU_CLK); wait (CPU_CLK);
end
end
endtask
task cpu_wr;
input [ 7:0] ia;
input [31:0] id;
begin
wait (~BUS[BUSOP_IO_WR]);
BUS_RQ[BUSOP_IO_WR] = 1;
wait (BUS[BUSOP_IO_WR]);
BUS_RQ[BUSOP_IO_WR] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE = 0;
#(CPU_A_WL) WE = 0;
CPU_DO[31:0] = id[31:0];
#(CPU_WL_D) CPU_OE = 1;
#(CPU_D_WH) WE = 1;
#(CPU_WH_A) A[7:0] = 8'bx;
CE = 1;
#(CPU_WH_D-CPU_WH_A) CPU_OE = 0;
BUS[BUSOP_IO_WR] = 0;
end
endtask
task cpu_rd;
input [ 7:0] ia;
begin
wait (~BUS[BUSOP_IO_RD]);
BUS_RQ[BUSOP_IO_RD] = 1;
wait (BUS[BUSOP_IO_RD]);
BUS_RQ[BUSOP_IO_RD] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE = 0;
#(CPU_A_RL) OE = 0;
#(CPU_RL_RH) CPU_DI[31:0] = D[31:0];
CPU_DI[31:0] = D[31:0];
OE = 1;
#(CPU_RH_A) A[7:0] = 8'bx;
CE = 1;
BUS[BUSOP_IO_RD] = 0;
end
endtask
task cpu_rd_ce1;
input [ 7:0] ia;
begin
wait (~BUS[BUSOP_IO_RD1]);
BUS_RQ[BUSOP_IO_RD1] = 1;
wait (BUS[BUSOP_IO_RD1]);
BUS_RQ[BUSOP_IO_RD1] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE1 = 0;
#(CPU_A_RL) OE = 0;
#(CPU_RL_RH) CPU_DI[31:0] = D[31:0];
OE = 1;
#(CPU_RH_A) A[7:0] = 8'bx;
CE1 = 1;
BUS[BUSOP_IO_RD1] = 0;
end
endtask
task cpu_wr_isr;
input [ 7:0] ia;
input [31:0] id;
begin
wait (~BUS[BUSOP_ISR_WR]);
BUS_RQ[BUSOP_ISR_WR] = 1;
wait (BUS[BUSOP_ISR_WR]);
BUS_RQ[BUSOP_ISR_WR] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE = 0;
#(CPU_A_WL) WE = 0;
CPU_DO[31:0] = id[31:0];
#(CPU_WL_D) CPU_OE = 1;
#(CPU_D_WH) WE = 1;
#(CPU_WH_A) A[7:0] = 8'bx;
CE = 1;
#(CPU_WH_D-CPU_WH_A) CPU_OE = 0;
BUS[BUSOP_ISR_WR] = 0;
end
endtask
task cpu_rd_isr;
input [ 7:0] ia;
begin
wait (~BUS[BUSOP_ISR_RD]);
BUS_RQ[BUSOP_ISR_RD] = 1;
wait (BUS[BUSOP_ISR_RD]);
BUS_RQ[BUSOP_ISR_RD] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE = 0;
#(CPU_A_RL) OE = 0;
#(CPU_RL_RH) CPU_DI[31:0] = D[31:0];
CPU_DI[31:0] = D[31:0];
OE = 1;
#(CPU_RH_A) A[7:0] = 8'bx;
CE = 1;
BUS[BUSOP_ISR_RD] = 0;
end
endtask
task cpu_rd_ce1_isr; //SuppressThisWarning Veditor UNUSED TASK
input [ 7:0] ia;
begin
wait (~BUS[BUSOP_ISR_RD1]);
BUS_RQ[BUSOP_ISR_RD1] = 1;
wait (BUS[BUSOP_ISR_RD1]);
BUS_RQ[BUSOP_ISR_RD1] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE1 = 0;
#(CPU_A_RL) OE = 0;
#(CPU_RL_RH) CPU_DI[31:0] = D[31:0];
OE = 1;
#(CPU_RH_A) A[7:0] = 8'bx;
CE1 = 1;
BUS[BUSOP_ISR_RD1] = 0;
end
endtask
parameter SDRAM_WAITINIT= 1000; // actually - 100usec - will it check?
parameter SDRAM_MANCMD= 8'h23;
parameter SDRAM_ENABLE= 8'h27; //!NOTE: Changed format - now each bit is replaced by a dibit - 0x - don't change, 10 - reset, 11 - set
parameter CHN_BASEA= 8'h20;
parameter CHN3_BASEA= 8'h2c;
parameter STATUS_ADDR= 8'h10;
parameter CH3_DATA_WND= 8'h30;
parameter CH3_RDY_BITNUM=7;
parameter CH3_WEMPTY_BITNUM=8; // was 0??
task read_status;
begin
cpu_rd(STATUS_ADDR);
end
endtask
task init_sdram;
begin
#(SDRAM_WAITINIT);
cpu_wr(SDRAM_MANCMD,32'h17fff); // precharge, a[10]=1 - all banks
#(100);
cpu_wr(SDRAM_MANCMD,32'h02000); // load extended mode register - enable DLL
#(100);
cpu_wr(SDRAM_MANCMD,32'h00163); // load mode register (CL=2.5, burst length=8 - no full page)and reset DLL
#(100);
cpu_wr(SDRAM_MANCMD,32'h17fff); // precharge, a[10]=1 - all banks
#(100);
cpu_wr(SDRAM_MANCMD,32'h8000); // refresh
#(100);
cpu_wr(SDRAM_MANCMD,32'h8000); // refresh
#(100);
cpu_wr(SDRAM_MANCMD,32'h00063); // load mode register (CL=2.5, burst length=8 - no full page)and reset DLL - not need for Micron
#(100);
// enable SDRAM controller and refresh (all channels disabled)
SDRAM_MODE = 'h00; cpu_wr(SDRAM_ENABLE,{20'b0,SDRAM_MODE}); // to init to 0 (for simulation only)
#(100);
// SDRAM_MODE=6'h03; cpu_wr(SDRAM_ENABLE,SDRAM_MODE); // All channels disabled, only refresh and sdram itself
SDRAM_MODE= 'haaf; cpu_wr(SDRAM_ENABLE,{20'b0,SDRAM_MODE}); // All channels disabled, only refresh and sdram itself
end
endtask
task init_chan;
input [1:0] ichnum; // channel number 0..3
input [1:0] imode; // mode - 3 - 1+ "rollover"
input iwnr; // write
input idep;
input [26:0] isa; // start address - lower 8 bits will be ignored
input [9:0] inTileX; // mode0: 5 MSBs - number of full (256*16) pages in line, 4 LSBs - additional partial page
input [11:0] inTileY; // in mode1 only 7MSBs are used
reg [24:0] sa;
reg [15:0] w0;
reg [15:0] w1;
reg [15:0] w2;
begin
sa[24:0] = {isa[24:8],8'b0};
$display ("init_chan: num=%x, mode=%x, rollover=%x, WnR=%x, depend=%x, startAddr=%x, nTileX=%x, ntileY=%x",ichnum,imode[0], imode[1],iwnr,idep,sa,inTileX,inTileY);
// w0[15:0]= {imode,iwnr,idep,1'b0,isa[19:8]};
w0[15:0]= {imode[0],(iwnr | &imode[1:0]) ,idep,isa[20:8]};
w1[15:0]= {2'b0,inTileX[9:0],isa[24:21]};
w2[15:0]= {4'b0,inTileY[11:0]};
$display (" writing %x to %x",w1,CHN_BASEA+4*ichnum+1);
cpu_wr(CHN_BASEA+4*ichnum+1,{16'b0,w1});
$display (" writing %x to %x",w2,CHN_BASEA+4*ichnum+2);
cpu_wr(CHN_BASEA+4*ichnum+2,{16'b0,w2});
$display (" writing %x to %x",w0,CHN_BASEA+4*ichnum+0);
cpu_wr(CHN_BASEA+4*ichnum+0,{16'b0,w0});
// enable channel:
// SDRAM_MODE=SDRAM_MODE | (6'h4 << ichnum);
SDRAM_MODE= (12'h030 << (ichnum <<1));
case (ichnum )
4'h0: SDRAM_MODE= 12'h030;
4'h1: SDRAM_MODE= 12'h0c0;
4'h2: SDRAM_MODE= 12'h300;
4'h3: SDRAM_MODE= 12'hc00;
endcase
cpu_wr(SDRAM_ENABLE,{20'b0,SDRAM_MODE});
end
endtask
// init_chan (2,1,0,1,'h200000,'h07,'h10); // ch2,mode1,wnr0,depend1,sa000000,nTileX10, nTileY10
task init_chan_seq;
input [7:0] seq_addr; // sequencer address to write to
input [1:0] ichnum; // channel number 0..3
input [1:0] imode; // mode - 3 - 1+ "rollover"
input iwnr; // write
input idep;
input [26:0] isa; // start address - lower 8 bits will be ignored
input [9:0] inTileX; // mode0: 5 MSBs - number of full (256*16) pages in line, 4 LSBs - additional partial page
input [13:0] inTileY; // in mode1 only 7MSBs are used
reg [24:0] sa;
reg [15:0] w0;
reg [15:0] w1;
reg [15:0] w2;
reg [ 7:0] a0;
reg [ 7:0] a1;
reg [ 7:0] a2;
begin
sa[24:0] = {isa[24:8],8'b0};
$display ("init_chan_seq: num=%x, mode=%x, rollover=%x, WnR=%x, depend=%x, startAddr=%x, nTileX=%x, ntileY=%x",ichnum,imode[0], imode[1],iwnr,idep,sa,inTileX,inTileY);
// w0[15:0]= {imode,iwnr,idep,1'b0,isa[19:8]};
w0[15:0]= {imode[0],(iwnr | &imode[1:0]) ,idep,isa[20:8]};
w1[15:0]= {2'b0,inTileX[9:0],isa[24:21]};
w2[15:0]= {2'b0,inTileY[13:0]};
a0[7:0]=CHN_BASEA+4*ichnum+0;
a1[7:0]=CHN_BASEA+4*ichnum+1;
a2[7:0]=CHN_BASEA+4*ichnum+2;
$display (" writing %x to %x",{a1[7:0],8'h0,w1[15:0]},seq_addr);
cpu_wr(seq_addr, {a1[7:0],8'h0,w1[15:0]});
$display (" writing %x to %x",{a2[7:0],8'h0,w2[15:0]},seq_addr);
cpu_wr(seq_addr, {a2[7:0],8'h0,w2[15:0]});
$display (" writing %x to %x",{a0[7:0],8'h0,w0[15:0]},seq_addr);
cpu_wr(seq_addr, {a0[7:0],8'h0,w0[15:0]});
// enable channel:
// SDRAM_MODE=SDRAM_MODE | (6'h4 << ichnum);
// SDRAM_MODE= (12'h030 << (ichnum <<1));
case (ichnum )
4'h0: SDRAM_MODE= 12'h030;
4'h1: SDRAM_MODE= 12'h0c0;
4'h2: SDRAM_MODE= 12'h300;
4'h3: SDRAM_MODE= 12'hc00;
endcase
// cpu_wr(SDRAM_ENABLE,SDRAM_MODE);
$display (" writing %x to %x",{SDRAM_ENABLE[7:0],12'h0,SDRAM_MODE[11:0]},seq_addr);
cpu_wr(seq_addr, {SDRAM_ENABLE[7:0],12'h0,SDRAM_MODE[11:0]});
end
endtask
task close_ch3;
begin
read_status;
while (!CPU_DI[CH3_WEMPTY_BITNUM]) read_status;
end
endtask
task read_ch3_descript;
begin
cpu_rd(CHN3_BASEA+0);
cpu_rd(CHN3_BASEA+1);
cpu_rd(CHN3_BASEA+2);
end
endtask
task write256_ch3; // write 16 16-bit words (as 8 x 32) , each next is greater by 1, starting with first;
input [15:0] first;
reg [15:0] i;
begin
$display ("write_256 (%d)",first);
read_status;
while (!CPU_DI[CH3_RDY_BITNUM]) read_status;
// for (i = 0; i < 128; i = i+1) cpu_wr(CH3_DATA_WND+i,first+2*i+(first+2*i+1)*65536);
for (i = 0; i < 128; i = i+1) cpu_wr(CH3_DATA_WND,first+2*i+(first+2*i+1)*65536);
cpu_wr(CHN3_BASEA+3,32'b0);
end
endtask
/*
task writeGrad_ch3; // write 256 8-bit words (as 64 x 32) , same all lines, with value=first+x
input [7:0] first;
integer i;
reg [7:0] j;
begin
$display ("writeGrad_ch3 (%d)",first);
read_status;
while (!CPU_DI[CH3_RDY_BITNUM]) read_status;
for (i =0; i< 128; i = i+8) begin
for (j = 0; j < 32; j = j+4)
// cpu_wr(CH3_DATA_WND+i+(j>>2),{(first+(j & 4'hf)+2'h3),(first+(j & 4'hf)+2'h2),(first+(j & 4'hf)+2'h1),(first+(j & 4'hf)+2'h0)});
cpu_wr(CH3_DATA_WND,{(first+(j & 4'hf)+2'h2),(first+(j & 4'hf)+2'h1),(first+(j & 4'hf)+2'h0)});
end
cpu_wr(CHN3_BASEA+3,32'b0);
end
endtask
task writeGrad_ch3_A; // write 256 8-bit words (as 64 x 32) , same all lines, with value=first+x
input [7:0] first;
integer i;
reg [7:0] j;
begin
$display ("writeGrad_ch3_A (%d)",first);
read_status;
while (!CPU_DI[CH3_RDY_BITNUM]) read_status;
for (i =0; i< 128; i = i+8) begin
for (j = 0; j < 32; j = j+4)
// cpu_wr(CH3_DATA_WND+i+(j>>2),{(first+(((j & 4'hf)+2'h3)<<4)),(first+(((j & 4'hf)+2'h2)<<4)),(first+(((j & 4'hf)+2'h1)<<4)),(first+(((j & 4'hf)+2'h00)<<4))});
cpu_wr(CH3_DATA_WND,{(first+(((j & 4'hf)+2'h2)<<4)),(first+(((j & 4'hf)+2'h1)<<4)),(first+(((j & 4'hf)+2'h0)<<4))});
end
cpu_wr(CHN3_BASEA+3,32'b0);
end
endtask
*/
// 1-cycle latency!
task read256_ch3; // read 16 16-bit words (as 8 x 32)
reg [15:0] i;
begin
read_status;
while (!CPU_DI[CH3_RDY_BITNUM]) read_status;
// cpu_rd(CH3_DATA_WND);
cpu_rd_ce1(CH3_DATA_WND);
for (i = 0; i < 127; i = i+1) begin
// cpu_rd(CH3_DATA_WND+i+1);
cpu_rd_ce1(CH3_DATA_WND);
$display ("ch3 (%x) = %x",i,CPU_DI);
end
// cpu_rd(CH3_DATA_WND+127);
cpu_rd_ce1(CH3_DATA_WND);
$display ("ch3 (%x) = %x",127,CPU_DI);
cpu_wr(CHN3_BASEA+3,32'b0);
end
endtask
//parameter CH3_RDY_BITNUM=4;
//parameter CH3_WEMPTY_BITNUM=5; // was 0??
/*
task read128_ch3;
integer i;
begin
$display ("read_128");
for (i = 0; i < 8; i = i+1) read_ch3;
end
endtask
*/
task program_huffman;
// huffman tables data
reg [23:0] huff_data[0:511]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i;
begin
$readmemh("huffman.dat",huff_data);
cpu_wr ('he,'h200); // start address of huffman tables
for (i=0;i<512;i=i+1) begin
cpu_wr('hf,{8'b0,huff_data[i]});
end
end
endtask
task program_quantization;
// quantization tables data
// reg [11:0] quant_data[0:255];
reg [15:0] quant_data[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i;
begin
// $readmemh("quantization.dat",quant_data);
$readmemh("quantization_100.dat",quant_data);
cpu_wr ('he,'h0); // start address of quantization tables
for (i=0;i<256;i=i+2) begin
cpu_wr('hf,{quant_data[i+1],quant_data[i]});
end
end
endtask
task program_coring;
// coring tables data
reg [15:0] coring_data[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i;
begin
// $readmemh("quantization.dat",quant_data);
$readmemh("coring.dat",coring_data);
cpu_wr ('he,'hc00); // start address of coring tables
for (i=0;i<1024;i=i+2) begin
cpu_wr('hf,{coring_data[i+1],coring_data[i]});
end
end
endtask
task program_focus_filt;
// focus quality filter data
reg [15:0] filt_data[0:127]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i;
begin
$readmemh("focus_filt.dat",filt_data);
cpu_wr ('he,'h800); // start address of focus filter tables
for (i=0;i<128;i=i+1) begin
cpu_wr('hf,{16'b0,filt_data[i]});
end
end
endtask
/*
task set_focus_filt;
// lower 3 bits of left/right/top/bottom will be ignored. Window includes borders
input [11:0] left;
input [11:0] right;
input [11:0] top;
input [11:0] bottom;
input [11:0] full_width; // 4 LSBs ignored
input [ 3:0] filter_sel;
input filter_strength;
begin
cpu_wr ('he,'hbc0); // start address of focus parameters (page 15)
cpu_wr ('hf,left[11:0]);
cpu_wr ('hf,right[11:0]);
cpu_wr ('hf,top[11:0]);
cpu_wr ('hf,bottom[11:0]);
cpu_wr ('hf,full_width[11:0]);
cpu_wr ('hf,filter_sel[3:0]);
cpu_wr ('hf,filter_strength);
end
endtask
cpu_wr('h68,'h0c0063ff); // focus mode 3
*/
task set_focus_filt;
// lower 3 bits of left/right/top/bottom will be ignored. Window includes borders
input [11:0] left;
input [11:0] right;
input [11:0] top;
input [11:0] bottom;
input [11:0] full_width; // 4 LSBs ignored
input [ 3:0] filter_sel;
input filter_strength;
begin
// cpu_wr ('he,'hbc0); // start address of focus parameters (page 15)
cpu_wr('h68,'h0e000bc0); // ASAP, start address of focus parameters (page 15)
// cpu_wr ('hf,left[11:0]);
cpu_wr('h68,{8'h0f,12'h0,left[11:0]});
// cpu_wr ('hf,right[11:0]);
cpu_wr('h68,{8'h0f,12'h0,right[11:0]});
// cpu_wr ('hf,top[11:0]);
cpu_wr('h68,{8'h0f,12'h0,top[11:0]});
// cpu_wr ('hf,bottom[11:0]);
cpu_wr('h68,{8'h0f,12'h0,bottom[11:0]});
// cpu_wr ('hf,full_width[11:0]);
cpu_wr('h68,{8'h0f,12'h0,full_width[11:0]});
// cpu_wr ('hf,filter_sel[3:0]);
cpu_wr('h68,{8'h0f,20'h0,filter_sel[3:0]});
// cpu_wr ('hf,filter_strength);
cpu_wr('h68,{8'h0f,23'h0,filter_strength});
end
endtask
task set_zero_bin;
// lower 3 bits of left/right/top/bottom will be ignored. Window includes borders
input [7:0] zero_bin;
input [7:0] quant_bias;
begin
// cpu_wr('h68,'h0e000be0); // ASAP, start address of focus parameters (page 15)
// cpu_wr('h68,{8'h0f,8'h0,quant_bias[7:0],zero_bin[7:0]});
cpu_wr('h68,{8'h0b,8'h0,quant_bias[7:0],zero_bin[7:0]});
end
endtask
task program_curves;
reg [9:0] curves_data[0:1027]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer n,i,base,diff,diff1;
///AF: reg [10:0] curv_diff;
begin
$readmemh("linear1028rgb.dat",curves_data);
// $readmemh("zero1028rgb.dat",curves_data);
cpu_wr ('he,'h400); // start address of quantization tables
for (n=0;n<4;n=n+1) begin
for (i=0;i<256;i=i+1) begin
base =curves_data[257*n+i];
diff =curves_data[257*n+i+1]-curves_data[257*n+i];
diff1=curves_data[257*n+i+1]-curves_data[257*n+i]+8;
// $display ("%x %x %x %x %x %x",n,i,curves_data[257*n+i], base, diff, diff1);
#1;
if ((diff>63) || (diff < -64)) cpu_wr('hf,{14'b0,1'b1,diff1[10:4],base[9:0]});
else cpu_wr('hf,{14'b0,1'b0,diff [ 6:0],base[9:0]});
end
end
end
endtask
/// NOTE: Can not use sequencer to program tables - may collide with software table writes !!!
task pre_program_curves; // all but last word, last word schedule through sequencer to provided address //SuppressThisWarning Veditor UNUSED TASK
input [7:0] seq_addr;
reg [9:0] curves_data[0:1027]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer n,i,base,diff,diff1;
///AF: reg [10:0] curv_diff;
reg [23:0] data;
begin
$readmemh("linear1028rgb.dat",curves_data);
// $readmemh("zero1028rgb.dat",curves_data);
cpu_wr ('he,'h400); // start address of quantization tables
for (n=0;n<4;n=n+1) begin
for (i=0;i<256;i=i+1) begin
base =curves_data[257*n+i];
diff =curves_data[257*n+i+1]-curves_data[257*n+i];
diff1=curves_data[257*n+i+1]-curves_data[257*n+i]+8;
// $display ("%x %x %x %x %x %x",n,i,curves_data[257*n+i], base, diff, diff1);
#1;
if ((diff>63) || (diff < -64)) data={6'b0,1'b1,diff1[10:4],base[9:0]};
else data={6'b0,1'b0,diff [ 6:0],base[9:0]};
if ((n<3) || (i<255)) cpu_wr('hf, {8'b0,data});
else begin
cpu_wr(seq_addr,'h0e0007ff);
cpu_wr(seq_addr,{8'h0f,data[23:0]});
end
end
end
// cpu_wr('h61,'h04000005);
end
endtask
task program_compressor;
input [ 7:0] address;
input [ 1:0] focus_mode;
input [ 1:0] bayer_shift;
input [ 2:0] tile_shift;
input [ 3:0] mode;
input dcsub;
input [ 2:0] qpage;
input [ 1:0] cmd;
begin
cpu_wr(address[7:0],
{8'h0c,
1'b1,focus_mode[1:0],
1'b1,bayer_shift[1:0],
1'b1,tile_shift[2:0],
1'b1,mode[3:0],
1'b1,dcsub,
1'b1,qpage[2:0],
1'b1,cmd[1:0]});
end
endtask
`ifdef TEST_IMU
`include "imu_sim_tasks_include.vh"
`endif
......
x353_sim_tasks_include.vh 0 → 100644
View file @ aafa6d1d
/*******************************************************************************
* Include file: x353_sim_tasks_include.vh
* Date:2015-07-26
* Author: Andrey Filippov
* Description: Moved here all simulation tasks except the IMU logger
*
* Copyright (c) 2015 Elphel, Inc .
* x353_sim_tasks_include.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x353_sim_tasks_include.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// CPU tasks
parameter CPU_C_A = 3;
parameter CPU_A_WL = 10;
parameter CPU_A_RL = 10; //10;
parameter CPU_RL_RH = 10; //10;
parameter CPU_WL_D = 4;
parameter CPU_D_WH = 16;
parameter CPU_WH_A = 2;
parameter CPU_WH_D = 4;
parameter CPU_RH_A = 2;
task dma_en;
input chn; // DMA channel (0/1)
input d; // 0 - disable, 1 - enable;
begin
if (chn) BUS_EN[BUSOP_DMA_1] = d;
else BUS_EN[BUSOP_DMA_0] = d;
end
endtask
task dma_rd;
input [ 7:0] ia;
input [ 7:0] burst;
integer i;
begin
wait (DREQ); // in this model CPU will not abanon DMA even if DREQ is reset before granted
wait (~BUS[BUSOP_DMA_0]);
BUS_RQ[BUSOP_DMA_0] = 1;
wait (BUS[BUSOP_DMA_0]);
BUS_RQ[BUSOP_DMA_0] = 0;
wait (CPU_CLK); wait (~CPU_CLK); wait (CPU_CLK);
for (i = 0; i < burst; i = i+1) begin
wait (~CPU_CLK); wait (CPU_CLK);
// once per burst
#(CPU_C_A) A[7:0] = ia[7:0];
DACK = 1'b1;
CE = 1'b0;
#(CPU_A_RL) OE = 1'b0;
#(CPU_RL_RH) DMA_DI = D[31:0];
OE = 1'b1;
end
#(CPU_RH_A) A[7:0] = 8'bx;
CE = 1'b1;
DACK = 1'b0;
BUS[BUSOP_DMA_0] =0;
// delay to let data from the CPU be written to the SDRAM
for (i = 0; i < burst; i = i+1) begin
wait (~CPU_CLK); wait (CPU_CLK);
wait (~CPU_CLK); wait (CPU_CLK);
end
end
endtask
task dma_rd_1;
input [ 7:0] ia;
input [ 7:0] burst;
integer i;
begin
wait (DREQ1); // in this model CPU will not abanon DMA even if DREQ is reset before granted
wait (~BUS[BUSOP_DMA_1]);
BUS_RQ[BUSOP_DMA_1] = 1;
wait (BUS[BUSOP_DMA_1]);
BUS_RQ[BUSOP_DMA_1] = 0;
wait (CPU_CLK); wait (~CPU_CLK); wait (CPU_CLK);
for (i = 0; i < burst; i = i+1) begin
wait (~CPU_CLK); wait (CPU_CLK);
// once per burst
#(CPU_C_A) A[7:0] = ia[7:0];
DACK1 = 1;
CE = 0;
#(CPU_A_RL) OE = 0;
#(CPU_RL_RH) DMA_DI_1 = D[31:0];
OE = 1;
end
#(CPU_RH_A) A[7:0] = 8'bx;
CE = 1;
DACK1 = 0;
BUS[BUSOP_DMA_1] =0;
// delay to let data from the CPU be written to the SDRAM
for (i = 0; i < burst; i = i+1) begin
wait (~CPU_CLK); wait (CPU_CLK);
wait (~CPU_CLK); wait (CPU_CLK);
end
end
endtask
task cpu_wr;
input [ 7:0] ia;
input [31:0] id;
begin
wait (~BUS[BUSOP_IO_WR]);
BUS_RQ[BUSOP_IO_WR] = 1;
wait (BUS[BUSOP_IO_WR]);
BUS_RQ[BUSOP_IO_WR] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE = 0;
#(CPU_A_WL) WE = 0;
CPU_DO[31:0] = id[31:0];
#(CPU_WL_D) CPU_OE = 1;
#(CPU_D_WH) WE = 1;
#(CPU_WH_A) A[7:0] = 8'bx;
CE = 1;
#(CPU_WH_D-CPU_WH_A) CPU_OE = 0;
BUS[BUSOP_IO_WR] = 0;
end
endtask
task cpu_rd;
input [ 7:0] ia;
begin
wait (~BUS[BUSOP_IO_RD]);
BUS_RQ[BUSOP_IO_RD] = 1;
wait (BUS[BUSOP_IO_RD]);
BUS_RQ[BUSOP_IO_RD] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE = 0;
#(CPU_A_RL) OE = 0;
#(CPU_RL_RH) CPU_DI[31:0] = D[31:0];
CPU_DI[31:0] = D[31:0];
OE = 1;
#(CPU_RH_A) A[7:0] = 8'bx;
CE = 1;
BUS[BUSOP_IO_RD] = 0;
end
endtask
task cpu_rd_ce1;
input [ 7:0] ia;
begin
wait (~BUS[BUSOP_IO_RD1]);
BUS_RQ[BUSOP_IO_RD1] = 1;
wait (BUS[BUSOP_IO_RD1]);
BUS_RQ[BUSOP_IO_RD1] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE1 = 0;
#(CPU_A_RL) OE = 0;
#(CPU_RL_RH) CPU_DI[31:0] = D[31:0];
OE = 1;
#(CPU_RH_A) A[7:0] = 8'bx;
CE1 = 1;
BUS[BUSOP_IO_RD1] = 0;
end
endtask
task cpu_wr_isr;
input [ 7:0] ia;
input [31:0] id;
begin
wait (~BUS[BUSOP_ISR_WR]);
BUS_RQ[BUSOP_ISR_WR] = 1;
wait (BUS[BUSOP_ISR_WR]);
BUS_RQ[BUSOP_ISR_WR] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE = 0;
#(CPU_A_WL) WE = 0;
CPU_DO[31:0] = id[31:0];
#(CPU_WL_D) CPU_OE = 1;
#(CPU_D_WH) WE = 1;
#(CPU_WH_A) A[7:0] = 8'bx;
CE = 1;
#(CPU_WH_D-CPU_WH_A) CPU_OE = 0;
BUS[BUSOP_ISR_WR] = 0;
end
endtask
task cpu_rd_isr;
input [ 7:0] ia;
begin
wait (~BUS[BUSOP_ISR_RD]);
BUS_RQ[BUSOP_ISR_RD] = 1;
wait (BUS[BUSOP_ISR_RD]);
BUS_RQ[BUSOP_ISR_RD] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE = 0;
#(CPU_A_RL) OE = 0;
#(CPU_RL_RH) CPU_DI[31:0] = D[31:0];
CPU_DI[31:0] = D[31:0];
OE = 1;
#(CPU_RH_A) A[7:0] = 8'bx;
CE = 1;
BUS[BUSOP_ISR_RD] = 0;
end
endtask
task cpu_rd_ce1_isr; //SuppressThisWarning Veditor UNUSED TASK
input [ 7:0] ia;
begin
wait (~BUS[BUSOP_ISR_RD1]);
BUS_RQ[BUSOP_ISR_RD1] = 1;
wait (BUS[BUSOP_ISR_RD1]);
BUS_RQ[BUSOP_ISR_RD1] = 0;
#(CPU_C_A) A[7:0] = ia[7:0];
CE1 = 0;
#(CPU_A_RL) OE = 0;
#(CPU_RL_RH) CPU_DI[31:0] = D[31:0];
OE = 1;
#(CPU_RH_A) A[7:0] = 8'bx;
CE1 = 1;
BUS[BUSOP_ISR_RD1] = 0;
end
endtask
parameter SDRAM_WAITINIT= 1000; // actually - 100usec - will it check?
parameter SDRAM_MANCMD= 8'h23;
parameter SDRAM_ENABLE= 8'h27; //!NOTE: Changed format - now each bit is replaced by a dibit - 0x - don't change, 10 - reset, 11 - set
parameter CHN_BASEA= 8'h20;
parameter CHN3_BASEA= 8'h2c;
parameter STATUS_ADDR= 8'h10;
parameter CH3_DATA_WND= 8'h30;
parameter CH3_RDY_BITNUM=7;
parameter CH3_WEMPTY_BITNUM=8; // was 0??
task read_status;
begin
cpu_rd(STATUS_ADDR);
end
endtask
task init_sdram;
begin
#(SDRAM_WAITINIT);
cpu_wr(SDRAM_MANCMD,32'h17fff); // precharge, a[10]=1 - all banks
#(100);
cpu_wr(SDRAM_MANCMD,32'h02000); // load extended mode register - enable DLL
#(100);
cpu_wr(SDRAM_MANCMD,32'h00163); // load mode register (CL=2.5, burst length=8 - no full page)and reset DLL
#(100);
cpu_wr(SDRAM_MANCMD,32'h17fff); // precharge, a[10]=1 - all banks
#(100);
cpu_wr(SDRAM_MANCMD,32'h8000); // refresh
#(100);
cpu_wr(SDRAM_MANCMD,32'h8000); // refresh
#(100);
cpu_wr(SDRAM_MANCMD,32'h00063); // load mode register (CL=2.5, burst length=8 - no full page)and reset DLL - not need for Micron
#(100);
// enable SDRAM controller and refresh (all channels disabled)
SDRAM_MODE = 'h00; cpu_wr(SDRAM_ENABLE,{20'b0,SDRAM_MODE}); // to init to 0 (for simulation only)
#(100);
// SDRAM_MODE=6'h03; cpu_wr(SDRAM_ENABLE,SDRAM_MODE); // All channels disabled, only refresh and sdram itself
SDRAM_MODE= 'haaf; cpu_wr(SDRAM_ENABLE,{20'b0,SDRAM_MODE}); // All channels disabled, only refresh and sdram itself
end
endtask
task init_chan;
input [1:0] ichnum; // channel number 0..3
input [1:0] imode; // mode - 3 - 1+ "rollover"
input iwnr; // write
input idep;
input [26:0] isa; // start address - lower 8 bits will be ignored
input [9:0] inTileX; // mode0: 5 MSBs - number of full (256*16) pages in line, 4 LSBs - additional partial page
input [11:0] inTileY; // in mode1 only 7MSBs are used
reg [24:0] sa;
reg [15:0] w0;
reg [15:0] w1;
reg [15:0] w2;
begin
sa[24:0] = {isa[24:8],8'b0};
$display ("init_chan: num=%x, mode=%x, rollover=%x, WnR=%x, depend=%x, startAddr=%x, nTileX=%x, ntileY=%x",ichnum,imode[0], imode[1],iwnr,idep,sa,inTileX,inTileY);
// w0[15:0]= {imode,iwnr,idep,1'b0,isa[19:8]};
w0[15:0]= {imode[0],(iwnr | &imode[1:0]) ,idep,isa[20:8]};
w1[15:0]= {2'b0,inTileX[9:0],isa[24:21]};
w2[15:0]= {4'b0,inTileY[11:0]};
$display (" writing %x to %x",w1,CHN_BASEA+4*ichnum+1);
cpu_wr(CHN_BASEA+4*ichnum+1,{16'b0,w1});
$display (" writing %x to %x",w2,CHN_BASEA+4*ichnum+2);
cpu_wr(CHN_BASEA+4*ichnum+2,{16'b0,w2});
$display (" writing %x to %x",w0,CHN_BASEA+4*ichnum+0);
cpu_wr(CHN_BASEA+4*ichnum+0,{16'b0,w0});
// enable channel:
// SDRAM_MODE=SDRAM_MODE | (6'h4 << ichnum);
SDRAM_MODE= (12'h030 << (ichnum <<1));
case (ichnum )
4'h0: SDRAM_MODE= 12'h030;
4'h1: SDRAM_MODE= 12'h0c0;
4'h2: SDRAM_MODE= 12'h300;
4'h3: SDRAM_MODE= 12'hc00;
endcase
cpu_wr(SDRAM_ENABLE,{20'b0,SDRAM_MODE});
end
endtask
// init_chan (2,1,0,1,'h200000,'h07,'h10); // ch2,mode1,wnr0,depend1,sa000000,nTileX10, nTileY10
task init_chan_seq;
input [7:0] seq_addr; // sequencer address to write to
input [1:0] ichnum; // channel number 0..3
input [1:0] imode; // mode - 3 - 1+ "rollover"
input iwnr; // write
input idep;
input [26:0] isa; // start address - lower 8 bits will be ignored
input [9:0] inTileX; // mode0: 5 MSBs - number of full (256*16) pages in line, 4 LSBs - additional partial page
input [13:0] inTileY; // in mode1 only 7MSBs are used
reg [24:0] sa;
reg [15:0] w0;
reg [15:0] w1;
reg [15:0] w2;
reg [ 7:0] a0;
reg [ 7:0] a1;
reg [ 7:0] a2;
begin
sa[24:0] = {isa[24:8],8'b0};
$display ("init_chan_seq: num=%x, mode=%x, rollover=%x, WnR=%x, depend=%x, startAddr=%x, nTileX=%x, ntileY=%x",ichnum,imode[0], imode[1],iwnr,idep,sa,inTileX,inTileY);
// w0[15:0]= {imode,iwnr,idep,1'b0,isa[19:8]};
w0[15:0]= {imode[0],(iwnr | &imode[1:0]) ,idep,isa[20:8]};
w1[15:0]= {2'b0,inTileX[9:0],isa[24:21]};
w2[15:0]= {2'b0,inTileY[13:0]};
a0[7:0]=CHN_BASEA+4*ichnum+0;
a1[7:0]=CHN_BASEA+4*ichnum+1;
a2[7:0]=CHN_BASEA+4*ichnum+2;
$display (" writing %x to %x",{a1[7:0],8'h0,w1[15:0]},seq_addr);
cpu_wr(seq_addr, {a1[7:0],8'h0,w1[15:0]});
$display (" writing %x to %x",{a2[7:0],8'h0,w2[15:0]},seq_addr);
cpu_wr(seq_addr, {a2[7:0],8'h0,w2[15:0]});
$display (" writing %x to %x",{a0[7:0],8'h0,w0[15:0]},seq_addr);
cpu_wr(seq_addr, {a0[7:0],8'h0,w0[15:0]});
// enable channel:
// SDRAM_MODE=SDRAM_MODE | (6'h4 << ichnum);
// SDRAM_MODE= (12'h030 << (ichnum <<1));
case (ichnum )
4'h0: SDRAM_MODE= 12'h030;
4'h1: SDRAM_MODE= 12'h0c0;
4'h2: SDRAM_MODE= 12'h300;
4'h3: SDRAM_MODE= 12'hc00;
endcase
// cpu_wr(SDRAM_ENABLE,SDRAM_MODE);
$display (" writing %x to %x",{SDRAM_ENABLE[7:0],12'h0,SDRAM_MODE[11:0]},seq_addr);
cpu_wr(seq_addr, {SDRAM_ENABLE[7:0],12'h0,SDRAM_MODE[11:0]});
end
endtask
task close_ch3;
begin
read_status;
while (!CPU_DI[CH3_WEMPTY_BITNUM]) read_status;
end
endtask
task read_ch3_descript;
begin
cpu_rd(CHN3_BASEA+0);
cpu_rd(CHN3_BASEA+1);
cpu_rd(CHN3_BASEA+2);
end
endtask
task write256_ch3; // write 16 16-bit words (as 8 x 32) , each next is greater by 1, starting with first;
input [15:0] first;
reg [15:0] i;
begin
$display ("write_256 (%d)",first);
read_status;
while (!CPU_DI[CH3_RDY_BITNUM]) read_status;
// for (i = 0; i < 128; i = i+1) cpu_wr(CH3_DATA_WND+i,first+2*i+(first+2*i+1)*65536);
for (i = 0; i < 128; i = i+1) cpu_wr(CH3_DATA_WND,first+2*i+(first+2*i+1)*65536);
cpu_wr(CHN3_BASEA+3,32'b0);
end
endtask
/*
task writeGrad_ch3; // write 256 8-bit words (as 64 x 32) , same all lines, with value=first+x
input [7:0] first;
integer i;
reg [7:0] j;
begin
$display ("writeGrad_ch3 (%d)",first);
read_status;
while (!CPU_DI[CH3_RDY_BITNUM]) read_status;
for (i =0; i< 128; i = i+8) begin
for (j = 0; j < 32; j = j+4)
// cpu_wr(CH3_DATA_WND+i+(j>>2),{(first+(j & 4'hf)+2'h3),(first+(j & 4'hf)+2'h2),(first+(j & 4'hf)+2'h1),(first+(j & 4'hf)+2'h0)});
cpu_wr(CH3_DATA_WND,{(first+(j & 4'hf)+2'h2),(first+(j & 4'hf)+2'h1),(first+(j & 4'hf)+2'h0)});
end
cpu_wr(CHN3_BASEA+3,32'b0);
end
endtask
task writeGrad_ch3_A; // write 256 8-bit words (as 64 x 32) , same all lines, with value=first+x
input [7:0] first;
integer i;
reg [7:0] j;
begin
$display ("writeGrad_ch3_A (%d)",first);
read_status;
while (!CPU_DI[CH3_RDY_BITNUM]) read_status;
for (i =0; i< 128; i = i+8) begin
for (j = 0; j < 32; j = j+4)
// cpu_wr(CH3_DATA_WND+i+(j>>2),{(first+(((j & 4'hf)+2'h3)<<4)),(first+(((j & 4'hf)+2'h2)<<4)),(first+(((j & 4'hf)+2'h1)<<4)),(first+(((j & 4'hf)+2'h00)<<4))});
cpu_wr(CH3_DATA_WND,{(first+(((j & 4'hf)+2'h2)<<4)),(first+(((j & 4'hf)+2'h1)<<4)),(first+(((j & 4'hf)+2'h0)<<4))});
end
cpu_wr(CHN3_BASEA+3,32'b0);
end
endtask
*/
// 1-cycle latency!
task read256_ch3; // read 16 16-bit words (as 8 x 32)
reg [15:0] i;
begin
read_status;
while (!CPU_DI[CH3_RDY_BITNUM]) read_status;
// cpu_rd(CH3_DATA_WND);
cpu_rd_ce1(CH3_DATA_WND);
for (i = 0; i < 127; i = i+1) begin
// cpu_rd(CH3_DATA_WND+i+1);
cpu_rd_ce1(CH3_DATA_WND);
$display ("ch3 (%x) = %x",i,CPU_DI);
end
// cpu_rd(CH3_DATA_WND+127);
cpu_rd_ce1(CH3_DATA_WND);
$display ("ch3 (%x) = %x",127,CPU_DI);
cpu_wr(CHN3_BASEA+3,32'b0);
end
endtask
//parameter CH3_RDY_BITNUM=4;
//parameter CH3_WEMPTY_BITNUM=5; // was 0??
/*
task read128_ch3;
integer i;
begin
$display ("read_128");
for (i = 0; i < 8; i = i+1) read_ch3;
end
endtask
*/
task program_huffman;
// huffman tables data
reg [23:0] huff_data[0:511]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i;
begin
$readmemh("huffman.dat",huff_data);
cpu_wr ('he,'h200); // start address of huffman tables
for (i=0;i<512;i=i+1) begin
cpu_wr('hf,{8'b0,huff_data[i]});
end
end
endtask
task program_quantization;
// quantization tables data
// reg [11:0] quant_data[0:255];
reg [15:0] quant_data[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i;
begin
// $readmemh("quantization.dat",quant_data);
$readmemh("quantization_100.dat",quant_data);
cpu_wr ('he,'h0); // start address of quantization tables
for (i=0;i<256;i=i+2) begin
cpu_wr('hf,{quant_data[i+1],quant_data[i]});
end
end
endtask
task program_coring;
// coring tables data
reg [15:0] coring_data[0:1023]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i;
begin
// $readmemh("quantization.dat",quant_data);
$readmemh("coring.dat",coring_data);
cpu_wr ('he,'hc00); // start address of coring tables
for (i=0;i<1024;i=i+2) begin
cpu_wr('hf,{coring_data[i+1],coring_data[i]});
end
end
endtask
task program_focus_filt;
// focus quality filter data
reg [15:0] filt_data[0:127]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i;
begin
$readmemh("focus_filt.dat",filt_data);
cpu_wr ('he,'h800); // start address of focus filter tables
for (i=0;i<128;i=i+1) begin
cpu_wr('hf,{16'b0,filt_data[i]});
end
end
endtask
/*
task set_focus_filt;
// lower 3 bits of left/right/top/bottom will be ignored. Window includes borders
input [11:0] left;
input [11:0] right;
input [11:0] top;
input [11:0] bottom;
input [11:0] full_width; // 4 LSBs ignored
input [ 3:0] filter_sel;
input filter_strength;
begin
cpu_wr ('he,'hbc0); // start address of focus parameters (page 15)
cpu_wr ('hf,left[11:0]);
cpu_wr ('hf,right[11:0]);
cpu_wr ('hf,top[11:0]);
cpu_wr ('hf,bottom[11:0]);
cpu_wr ('hf,full_width[11:0]);
cpu_wr ('hf,filter_sel[3:0]);
cpu_wr ('hf,filter_strength);
end
endtask
cpu_wr('h68,'h0c0063ff); // focus mode 3
*/
task set_focus_filt;
// lower 3 bits of left/right/top/bottom will be ignored. Window includes borders
input [11:0] left;
input [11:0] right;
input [11:0] top;
input [11:0] bottom;
input [11:0] full_width; // 4 LSBs ignored
input [ 3:0] filter_sel;
input filter_strength;
begin
// cpu_wr ('he,'hbc0); // start address of focus parameters (page 15)
cpu_wr('h68,'h0e000bc0); // ASAP, start address of focus parameters (page 15)
// cpu_wr ('hf,left[11:0]);
cpu_wr('h68,{8'h0f,12'h0,left[11:0]});
// cpu_wr ('hf,right[11:0]);
cpu_wr('h68,{8'h0f,12'h0,right[11:0]});
// cpu_wr ('hf,top[11:0]);
cpu_wr('h68,{8'h0f,12'h0,top[11:0]});
// cpu_wr ('hf,bottom[11:0]);
cpu_wr('h68,{8'h0f,12'h0,bottom[11:0]});
// cpu_wr ('hf,full_width[11:0]);
cpu_wr('h68,{8'h0f,12'h0,full_width[11:0]});
// cpu_wr ('hf,filter_sel[3:0]);
cpu_wr('h68,{8'h0f,20'h0,filter_sel[3:0]});
// cpu_wr ('hf,filter_strength);
cpu_wr('h68,{8'h0f,23'h0,filter_strength});
end
endtask
task set_zero_bin;
// lower 3 bits of left/right/top/bottom will be ignored. Window includes borders
input [7:0] zero_bin;
input [7:0] quant_bias;
begin
// cpu_wr('h68,'h0e000be0); // ASAP, start address of focus parameters (page 15)
// cpu_wr('h68,{8'h0f,8'h0,quant_bias[7:0],zero_bin[7:0]});
cpu_wr('h68,{8'h0b,8'h0,quant_bias[7:0],zero_bin[7:0]});
end
endtask
task program_curves;
reg [9:0] curves_data[0:1027]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer n,i,base,diff,diff1;
///AF: reg [10:0] curv_diff;
begin
$readmemh("linear1028rgb.dat",curves_data);
// $readmemh("zero1028rgb.dat",curves_data);
cpu_wr ('he,'h400); // start address of quantization tables
for (n=0;n<4;n=n+1) begin
for (i=0;i<256;i=i+1) begin
base =curves_data[257*n+i];
diff =curves_data[257*n+i+1]-curves_data[257*n+i];
diff1=curves_data[257*n+i+1]-curves_data[257*n+i]+8;
// $display ("%x %x %x %x %x %x",n,i,curves_data[257*n+i], base, diff, diff1);
#1;
if ((diff>63) || (diff < -64)) cpu_wr('hf,{14'b0,1'b1,diff1[10:4],base[9:0]});
else cpu_wr('hf,{14'b0,1'b0,diff [ 6:0],base[9:0]});
end
end
end
endtask
/// NOTE: Can not use sequencer to program tables - may collide with software table writes !!!
task pre_program_curves; // all but last word, last word schedule through sequencer to provided address //SuppressThisWarning Veditor UNUSED TASK
input [7:0] seq_addr;
reg [9:0] curves_data[0:1027]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer n,i,base,diff,diff1;
///AF: reg [10:0] curv_diff;
reg [23:0] data;
begin
$readmemh("linear1028rgb.dat",curves_data);
// $readmemh("zero1028rgb.dat",curves_data);
cpu_wr ('he,'h400); // start address of quantization tables
for (n=0;n<4;n=n+1) begin
for (i=0;i<256;i=i+1) begin
base =curves_data[257*n+i];
diff =curves_data[257*n+i+1]-curves_data[257*n+i];
diff1=curves_data[257*n+i+1]-curves_data[257*n+i]+8;
// $display ("%x %x %x %x %x %x",n,i,curves_data[257*n+i], base, diff, diff1);
#1;
if ((diff>63) || (diff < -64)) data={6'b0,1'b1,diff1[10:4],base[9:0]};
else data={6'b0,1'b0,diff [ 6:0],base[9:0]};
if ((n<3) || (i<255)) cpu_wr('hf, {8'b0,data});
else begin
cpu_wr(seq_addr,'h0e0007ff);
cpu_wr(seq_addr,{8'h0f,data[23:0]});
end
end
end
// cpu_wr('h61,'h04000005);
end
endtask
task program_compressor;
input [ 7:0] address;
input [ 1:0] focus_mode;
input [ 1:0] bayer_shift;
input [ 2:0] tile_shift;
input [ 3:0] mode;
input dcsub;
input [ 2:0] qpage;
input [ 1:0] cmd;
begin
cpu_wr(address[7:0],
{8'h0c,
1'b1,focus_mode[1:0],
1'b1,bayer_shift[1:0],
1'b1,tile_shift[2:0],
1'b1,mode[3:0],
1'b1,dcsub,
1'b1,qpage[2:0],
1'b1,cmd[1:0]});
end
endtask
\ No newline at end of file
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