Commit d6e9be6b authored by Andrey Filippov's avatar Andrey Filippov

fixing VDT warnings, splitting testbench file, adding modified primitive SLR version for simulation

parent 5d6f430e
......@@ -9,20 +9,50 @@
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......@@ -18,7 +18,7 @@ Here is what makes it difficult:
2. Last verion of the ISE (it is ISE 14.7) can not use the older code "as is"
3. We were able to modify the Verilog code to be parsed by the current XST, but it does not
recognize some statements in the *.xcf constraints file (I had to rename original *.ucf to *.xcf).
4. Attempt to try old parser (Suggested by XST itself as the new parser is not the default for
4. Attempt to try old parser (suggested by XST itself as the new parser is not the default for
the Spartan 3e):
```
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default
......
......@@ -198,7 +198,7 @@ input hdr; // second green absolute, not difference
reg four_blocks_r;
reg scale_diff_r;
reg hdr_r;
reg [1:0] tile_margin_r;
reg [1:0] tile_margin_r; // SuppressThisWarning Veditor UNUSED
// reg [2:0] tile_shift_r;
reg [1:0] bayer_phase_r;
reg [3:0] bayer_phase_onehot;
......@@ -259,7 +259,7 @@ input hdr; // second green absolute, not difference
last_from_sdram <= en & preline_was_0 && (prepix[4:0]==0);
inc_sdrama <= en & (pre_first_pixel || (inc_sdrama && !last_from_sdram ));
if (pre_first_pixel) sdram_a9[8:0] <= sdrama_top_left[8:0];
else if (inc_sdrama) sdram_a9[8:0] <= sdram_a9[8:0] + (pre_start_of_line ? sdrama_line_inc[2:0] : 1);
else if (inc_sdrama) sdram_a9[8:0] <= sdram_a9[8:0] + (pre_start_of_line ? sdrama_line_inc[2:0] : 3'b1);
if (!en || memWasInit) sdram_a9_page[1:0] <= 2'h0;
else if (last_from_sdram && inc_sdrama) sdram_a9_page[1:0] <= sdram_a9_page[1:0]+1;
......@@ -445,7 +445,7 @@ input hdr; // second green absolute, not difference
if (first_pixel) begin
first0 <= willbe_first;
last0 <= (bcntr[17:0]==17'b0);
last0 <= (bcntr[17:0] == 18'b0);
end
if (ccv_out_start) begin
first <= first0;
......
......@@ -219,21 +219,21 @@ module compressor(// cwr, // CPU write - global clock
// 3 - enable compressor, enable repetitive mode
//
// control registetr bits
wire cr_w; // data written to cr (1 cycle) - now just to reset legacy IRQ
wire raw_dv; // input pixel data valid (pxd[7:0]may be sent to DMA buffer through multiplexor)
wire color_dv; // unused // color data valid (color_d[7:0] may be sent to DMA buffer through multiplexor)
wire [ 9:0] color_d; // data out stream from color space converter (6X64 blocks for each MCU - 4Y, Cb,Cr)
wire [ 2:0] color_tn; // tile number in an MCU from color space converter (valid @ color_dv)
wire [ 8:0] color_avr; // [8:0] DC (average value) 9 bit signed for Y: 9'h000..9'h0ff, for C - 9h100..9'h000..9'h0ff
wire color_first; // sending first MCU (valid @ ds)
wire color_last; // sending last MCU (valid @ ds)
wire cr_w; // data written to cr (1 cycle) - now just to reset legacy IRQ
wire raw_dv; // input pixel data valid (pxd[7:0]may be sent to DMA buffer through multiplexor) // SuppressThisWarning Veditor UNUSED
wire color_dv; // unused // color data valid (color_d[7:0] may be sent to DMA buffer through multiplexor)// SuppressThisWarning Veditor UNUSED
wire [ 9:0] color_d; // data out stream from color space converter (6X64 blocks for each MCU - 4Y, Cb,Cr)
wire [ 2:0] color_tn; // tile number in an MCU from color space converter (valid @ color_dv)
wire [ 8:0] color_avr; // [8:0] DC (average value) 9 bit signed for Y: 9'h000..9'h0ff, for C - 9h100..9'h000..9'h0ff
wire color_first; // sending first MCU (valid @ ds)
wire color_last; // sending last MCU (valid @ ds)
// wire dct_en;
wire dct_start;
wire dct_dv;
wire dct_start;
wire dct_dv; // SuppressThisWarning Veditor UNUSED
wire [12:0] dct_out;
wire dct_last_in; // output high during input of the last of 64 pixels in a 8x8 block
wire dct_pre_first_out; // 1 cycle ahead of the first output in a 64 block
wire dct_last_in; // output high during input of the last of 64 pixels in a 8x8 block
wire dct_pre_first_out; // 1 cycle ahead of the first output in a 64 block
wire [17:0] ntiles; //number of 16x16 MCU tiles in a frame to process
reg quant_start;
......@@ -245,7 +245,7 @@ module compressor(// cwr, // CPU write - global clock
wire focus_ds;
// wire enc_first;
wire enc_last;
wire enc_last; // SuppressThisWarning Veditor UNUSED
wire [15:0] enc_do;
wire enc_dv;
......@@ -664,8 +664,8 @@ FD i_is_compressing (.Q(is_compressing),.C(clk), .D(cmprs_en && (go_single || (i
// single-cycle @ negedge sclk
`ifdef debug_compressor
wire debug_bcntrIsZero;
wire [17:0] debug_bcntr;
wire debug_bcntrIsZero;
wire [17:0] debug_bcntr; //SuppressThisWarning Veditor UNUSED
`endif
color_proc i_color_proc(.clk(clk), // pixel clock 37.5MHz
.en(cmprs_en), // Enable (0 will reset states)
......@@ -1080,7 +1080,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk)
reg [23:0] cr;
///AF: reg [23:0] cr;
reg [17:0] ntiles;
reg [15:0] ntiles0;
reg [17:0] ntiles1;
......@@ -1095,7 +1095,8 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk)
assign rcs[1:0]={cwe && rs, cwe && ~rs};
reg rcs0_d, rcs0_dd, rcs1_d;
reg rcs0_d, rcs0_dd;
///AF: reg rcs1_d;
reg [2:0] rcs1d;
reg [1:0] is_compressing_sclk; // sync to negedge sclk
......@@ -1168,7 +1169,7 @@ module compr_ifc (clk, // compressor input clock (1/2 of sclk)
// always @ (posedge clk) cr[23:0] <=cri[23:0]; // make it sync
always @ (negedge sclk) if (rcs[1]) ntiles0[15:0] <= di[15:0];
// always @ (negedge sclk) if (rcs1_d) ntiles1[17:0] <= {di[15:0],ntiles0[15:0]};
always @ (negedge sclk) if (rcs1d[0]) ntiles1[17:0] <= {di[15:0],ntiles0[15:0]};
always @ (negedge sclk) if (rcs1d[0]) ntiles1[17:0] <= {di[ 1:0],ntiles0[15:0]};
always @ (negedge sclk) if (rcs1d[2]) ntiles1_prev[17:0] <= ntiles1[17:0];
// rcs1d[2:0]<={rcs1d[1:0],rcs[1]};
......
......@@ -129,7 +129,10 @@ module csconvert_jp4diff (en,
reg dly_1;
reg [14:0] dly_16;
reg dly_17;
wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17:dly_16):(bayer_phase[0]?dly_1:pre_first_in);
// wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17:dly_16):(bayer_phase[0]?dly_1:pre_first_in);
///AF2015 - What was supposed to be here for "dly_16" (15 bits, expected 1) - any non-zero or [14]?
// wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17: (|dly_16)):(bayer_phase[0]?dly_1:pre_first_in);
wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17: dly_16[14]):(bayer_phase[0]?dly_1:pre_first_in);
reg [7:0] iadr;
reg iadr_run;
reg [1:0] mux_plus_sel;
......
......@@ -234,7 +234,8 @@ assign mult_b[17:0] = use_coef ? {d1[10:0],{7{d1[0]}}}: mult_s[17:0];
use_k_dly[5:0]<={use_k_dly[4:0],use_coef};
acc_ldval <= !(|start2[7:6]);
if (acc_clear || (acc_corr && acc_blk[23])) acc_blk[23:0] <= {1'b0,{23{acc_ldval}}};
else if (acc_add) acc_blk[23:0] <= acc_blk[23:0]+mult_p[35:8];
///AF: else if (acc_add) acc_blk[23:0] <= acc_blk[23:0]+mult_p[35:8];
else if (acc_add) acc_blk[23:0] <= acc_blk[23:0]+mult_p[31:8];
if (acc_to_out) fdo[11:0] <= (|acc_blk[23:20])?12'hfff:acc_blk[19:8]; // positive, 0..0xfff
if (acc_to_out) sum_blk[22:0] <= acc_blk[22:0]; // accumulator for the sum ((a[i]*d[i])^2), copied at block end
......@@ -290,18 +291,12 @@ assign mult_b[17:0] = use_coef ? {d1[10:0],{7{d1[0]}}}: mult_s[17:0];
.RSTP(1'b0) // Synchronous reset input for the P port
);
RAM16X1D i_tn0 (.D(tni[0]),.DPO(tn[0]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAM16X1D i_tn1 (.D(tni[1]),.DPO(tn[1]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAM16X1D i_tn2 (.D(tni[2]),.DPO(tn[2]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAM16X1D i_first (.D(firsti),.DPO(first),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAM16X1D i_last (.D(lasti), .DPO(last), .A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb));
RAM16X1D i_tn0 (.D(tni[0]),.DPO(tn[0]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_tn1 (.D(tni[1]),.DPO(tn[1]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_tn2 (.D(tni[2]),.DPO(tn[2]),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_first (.D(firsti),.DPO(first),.A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAM16X1D i_last (.D(lasti), .DPO(last), .A0(ic[0]),.A1(ic[1]),.A2(1'b0),.A3(1'b0),.DPRA0(oc[0]),.DPRA1(oc[1]),.DPRA2(1'b0),.DPRA3(1'b0),.WCLK(clk),.WE(stb),.SPO());
RAMB16_S18_S18 i_focus_dct_tab (
.DOA(tdo[15:0]), // Port A 16-bit Data Output
......
......@@ -68,9 +68,9 @@ module huffman (pclk, // half frequency, sync to incoming data
output gotLastBlock;
reg test_lbw;
wire [19:0] tables_out;
wire [15:0] hcode; // table output huffman code (1..16 bits)
wire [15:0] hcode; // table output huffman code (1..16 bits)
wire [ 3:0] hlen; // table - code length only 4 LSBs are used
wire [11:0] unused;
wire [11:0] unused; // SuppressThisWarning Veditor UNUSED
reg [ 7:0] haddr_r; // index in huffman table
wire [ 7:0] haddr_next;
wire [ 8:0] haddr; // index in huffman table (after latches)
......@@ -335,18 +335,18 @@ module huff_fifo (pclk,
output dav;
output[15:0] q;
reg [9:0] wa;
reg [9:0] sync_wa; // delayed wa, re-calculated at output clock
reg [9:0] wa;
reg [9:0] sync_wa; // delayed wa, re-calculated at output clock
reg [9:0] ra_r;
wire [9:0] ra;
wire [15:0] q;
reg load_q;
wire [15:0] q;
reg load_q; // SuppressThisWarning Veditor VDT_BUG
wire [15:0] fifo_o;
reg ds1; // ds delayed by one pclk to give time to block ram to write data. Not needed likely.
reg synci;
reg [1:0] synco;
reg sync_we; // single clk period pulse for each ds@pclk
reg en2x; // en sync to clk;
reg sync_we; // single clk period pulse for each ds@pclk
reg en2x; // en sync to clk;
reg re_r;
wire re;
......@@ -404,7 +404,6 @@ module huff_fifo (pclk,
LD i_ra1 (.Q(ra[1]),.G(clk),.D(ra_r[1]));
LD i_ra0 (.Q(ra[0]),.G(clk),.D(ra_r[0]));
always @ (posedge clk) begin
// load_q <= dav?want_read:re_r;
load_q <= dav?want_read_early:re_r;
end
LD_1 i_q15 (.Q( q[15]),.G(clk),.D(load_q?fifo_o[15]:q[15]));
......
......@@ -223,6 +223,7 @@ This value divided by 2raised to 8 is equivalent to ignoring the 8 lsb bits of t
reg[9:0] xa0_in, xa1_in, xa2_in, xa3_in, xa4_in, xa5_in, xa6_in, xa7_in;
reg[9:0] xa0_reg, xa1_reg, xa2_reg, xa3_reg, xa4_reg, xa5_reg, xa6_reg, xa7_reg;
reg[9:0] addsub1a_comp,addsub2a_comp,addsub3a_comp,addsub4a_comp;
reg[10:0] add_sub1a,add_sub2a,add_sub3a,add_sub4a;
reg save_sign1a, save_sign2a, save_sign3a, save_sign4a;
reg[17:0] p1a,p2a,p3a,p4a;
......@@ -384,15 +385,22 @@ always @ (negedge clk)
// 9th clk for registering shifted input and 10th clk for add_sub
// to synchronize the i value to the add_sub value, i value is incremented
// only after 10 clks
// Adding these wires to get rid of the MSB that is always 0
wire [10:0] addsub1a_comp_w = add_sub1a[10]? (-add_sub1a) : add_sub1a;
wire [10:0] addsub2a_comp_w = add_sub2a[10]? (-add_sub2a) : add_sub2a;
wire [10:0] addsub3a_comp_w = add_sub3a[10]? (-add_sub3a) : add_sub3a;
wire [10:0] addsub4a_comp_w = add_sub4a[10]? (-add_sub4a) : add_sub4a;
always @ (negedge clk) begin
save_sign1a <= add_sub1a[10];
save_sign2a <= add_sub2a[10];
save_sign3a <= add_sub3a[10];
save_sign4a <= add_sub4a[10];
addsub1a_comp <= add_sub1a[10]? (-add_sub1a) : add_sub1a;
addsub2a_comp <= add_sub2a[10]? (-add_sub2a) : add_sub2a;
addsub3a_comp <= add_sub3a[10]? (-add_sub3a) : add_sub3a;
addsub4a_comp <= add_sub4a[10]? (-add_sub4a) : add_sub4a;
addsub1a_comp <= addsub1a_comp_w[9:0]; //add_sub1a[10]? (-add_sub1a) : add_sub1a;
addsub2a_comp <= addsub2a_comp_w[9:0]; //add_sub2a[10]? (-add_sub2a) : add_sub2a;
addsub3a_comp <= addsub3a_comp_w[9:0]; //add_sub3a[10]? (-add_sub3a) : add_sub3a;
addsub4a_comp <= addsub4a_comp_w[9:0]; //add_sub4a[10]? (-add_sub4a) : add_sub4a;
end
assign p1a_all = addsub1a_comp * memory1a[15:0];
......@@ -504,7 +512,7 @@ wire sxregs;
wire sxregs_d8;
reg enable_toggle;
reg en_started;
wire disdv;
SRL16 i_endv (.Q(endv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(start)); // dly=14+1
SRL16 i_disdv (.Q(disdv), .A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b1), .CLK(clk), .D(rd_cntr[5:0]==6'h3f)); // dly=14+1
......@@ -621,6 +629,11 @@ always @ (posedge clk)
add_sub4b <= ({xb4_reg[15],xb4_reg[15:0]} - {xb3_reg[15],xb3_reg[15:0]});
end
// Adding these wires to get rid of the MSB that is always 0
wire [16:0] addsub1b_comp_w = add_sub1b[16]? (-add_sub1b) : add_sub1b;
wire [16:0] addsub2b_comp_w = add_sub2b[16]? (-add_sub2b) : add_sub2b;
wire [16:0] addsub3b_comp_w = add_sub3b[16]? (-add_sub3b) : add_sub3b;
wire [16:0] addsub4b_comp_w = add_sub4b[16]? (-add_sub4b) : add_sub4b;
always @ (posedge clk) begin
// save_sign1b <= add_sub1b[10];
......@@ -635,21 +648,26 @@ always @ (posedge clk) begin
save_sign2b <= add_sub2b[16];
save_sign3b <= add_sub3b[16];
save_sign4b <= add_sub4b[16];
addsub1b_comp <= add_sub1b[16]? (-add_sub1b) : add_sub1b;
addsub2b_comp <= add_sub2b[16]? (-add_sub2b) : add_sub2b;
addsub3b_comp <= add_sub3b[16]? (-add_sub3b) : add_sub3b;
addsub4b_comp <= add_sub4b[16]? (-add_sub4b) : add_sub4b;
addsub1b_comp <= addsub1b_comp_w[15:0]; // add_sub1b[16]? (-add_sub1b) : add_sub1b;
addsub2b_comp <= addsub2b_comp_w[15:0]; // add_sub2b[16]? (-add_sub2b) : add_sub2b;
addsub3b_comp <= addsub3b_comp_w[15:0]; // add_sub3b[16]? (-add_sub3b) : add_sub3b;
addsub4b_comp <= addsub4b_comp_w[15:0]; // add_sub4b[16]? (-add_sub4b) : add_sub4b;
end
// assign p1b_all = addsub1b_comp * memory1a[15:0];
// assign p2b_all = addsub2b_comp * memory2a[15:0];
// assign p3b_all = addsub3b_comp * memory3a[15:0];
// assign p4b_all = addsub4b_comp * memory4a[15:0];
assign p1b_all = addsub1b_comp[15:0] * memory1a[15:0];
assign p2b_all = addsub2b_comp[15:0] * memory2a[15:0];
assign p3b_all = addsub3b_comp[15:0] * memory3a[15:0];
assign p4b_all = addsub4b_comp[15:0] * memory4a[15:0];
///AF2015:
// assign p1b_all = addsub1b_comp[15:0] * memory1a[15:0];
// assign p2b_all = addsub2b_comp[15:0] * memory2a[15:0];
// assign p3b_all = addsub3b_comp[15:0] * memory3a[15:0];
// assign p4b_all = addsub4b_comp[15:0] * memory4a[15:0];
assign p1b_all = addsub1b_comp * memory1a;
assign p2b_all = addsub2b_comp * memory2a;
assign p3b_all = addsub3b_comp * memory3a;
assign p4b_all = addsub4b_comp * memory4a;
always @ (posedge clk)
begin
......
......@@ -119,7 +119,7 @@ module camsync (sclk, // @negedge
reg [31:0] restart_cntr; // restart period counter
reg [1:0] restart_cntr_run; // restart counter running
wire restart; // restart out sync
reg [8:0] out_pulse_cntr;
///AF: reg [8:0] out_pulse_cntr;
reg trigger_condition; // GPIO input trigger condition met
reg trigger_condition_d; // GPIO input trigger condition met, delayed (for edge detection)
reg trigger_condition_filtered; // trigger condition filtered
......@@ -140,7 +140,7 @@ module camsync (sclk, // @negedge
wire pre_start_out_pulse;
reg start_out_pulse; /// start generation of output pulse. In internal trigger mode uses delay counter, in external - no delay
reg pre_start;
///AF: reg pre_start;
reg [31:0] pre_period;
reg [ 7:0] bit_length='hff; /// Output pulse duration or bit duration in timestamp mode
/// input will be filtered with (bit_length>>2) duration
......@@ -228,7 +228,7 @@ module camsync (sclk, // @negedge
// if (wen[3]) repeat_period[31:0] <= did[31:0];
if (wen[3]) pre_period[31:0] <= did[31:0];
if (wen[3]) high_zero = did[31:8]==24'b0;
if (wen[3]) high_zero <= did[31:8]==24'b0;
// start <= wen[3] && (did[31:0]!=32'h0);
......
......@@ -45,7 +45,7 @@ module dcm333(
output xclk;
output SDCLK, SDNCLK;
input [1:0] phsel;
input sdcl_fb;
input sdcl_fb; // SuppressThisWarning Veditor UNUSED - was designed to use external pin sync (maybe still use it?)
input dcm_rst, dcm_incdec, dcm_en, dcm_clk;
output dcm_done;
......
......@@ -160,7 +160,7 @@ FD_1 i_initialized ( .Q(initialized), .C(sclk), .D(por[1] && ( initialized || (r
we_fifo_wp <= wen_d[1] || wpage0_inc;
if (wen_d[1]) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0];
if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 7'h0:(fifo_wr_pointers_outw_r[5:0]+1);
if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri
// command seq fifo (RAMB16_S9_S18)
......
......@@ -131,7 +131,7 @@ module dma_fifo_sync ( clk, // system clock, 120MHz? (currentle negedge used)
burst_start_sync[1:0] <= {burst_start_sync[0],~first_four_r[2] & first_four_r[1]};
first_four_r[2:0]={first_four_r[1:0],first_four};
first_four_r[2:0] <= {first_four_r[1:0],first_four};
empties[3:0] <= {4{!rst && (infifo[9:0]==10'h0) && !dreq && !dack_r[1]}} & {empties[2:0],1'b1};
......
......@@ -201,8 +201,8 @@ module i2c_writeonly (sclk, // @negedge
bytes_cmd <= wen_d[0] && is_ctl && di_1[11];
dly_cmd <= wen_d[0] && is_ctl && di_1[ 8];
// setting control parameters
if (bytes_cmd) i2c_bytes[1:0]=di_2[10:9];
if (dly_cmd) i2c_dly[7:0] =di_2[ 7:0];
if (bytes_cmd) i2c_bytes[1:0] <= di_2[10:9];
if (dly_cmd) i2c_dly[7:0] <= di_2[ 7:0];
if (reset_cmd || (run_cmd && !di_2[12])) i2c_enrun <= 1'b0;
else if (run_cmd && di_2[12]) i2c_enrun <= 1'b1;
// write pointer memory
......@@ -220,7 +220,7 @@ module i2c_writeonly (sclk, // @negedge
we_fifo_wp <= wen_d[1] || wpage0_inc;
if (wen_d[1]) fifo_wr_pointers_outw_r[5:0] <= fifo_wr_pointers_outw[5:0];
if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 7'h0:(fifo_wr_pointers_outw_r[5:0]+1);
if (we_fifo_wp) fifo_wr_pointers[wpage_w[2:0]] <= wpage0_inc_d? 6'h0:(fifo_wr_pointers_outw_r[5:0]+1);
fifo_wr_pointers_outr_r[5:0] <= fifo_wr_pointers_outr[5:0]; // just register distri
// command i2c fifo (RAMB16_S9_S18)
......
......@@ -55,7 +55,7 @@ module interrupts_vector(sclk, // @negedge
wire [15:0] irq_insa;
reg [15:0] irq_insb;
reg [15:0] irq_insc; //single cycle sync interrupt request.
wire [15:0] irq_rst;
///AF: wire [15:0] irq_rst;
reg rst_rqs, en_rqs, dis_rqs, pre_set_irqv, set_irqv;
reg [ 3:0] irqv_a; // irq vectors table write address
reg [ 7:0] irqv_d; // irq vectors table write data
......@@ -190,7 +190,7 @@ module interrupts_vector(sclk, // @negedge
FD_1 i_irq_um_15 (.C(sclk), .D(~(rst_rq[15]) & (irq_insc[15] | irq_um[15])), .Q(irq_um[15]));
myRAM16X8D_1 i_vecttab (.D(irqv_d[7:0]), .WE(set_irqv), .clk(sclk), .AW(irqv_a[3:0]), .AR(irqn_r[3:0]), .QR(irqv[7:0]));
myRAM16X8D_1 i_vecttab (.D(irqv_d[7:0]), .WE(set_irqv), .clk(sclk), .AW(irqv_a[3:0]), .AR(irqn_r[3:0]), .QR(irqv[7:0]), .QW());
always @ (negedge sclk) begin
if (pre_wen) did[15:0] <= di[15:0];
......@@ -208,8 +208,8 @@ module interrupts_vector(sclk, // @negedge
set_irqv <= pre_set_irqv;
if (pre_set_irqv) irqv_a[3:0] <= did[11:8];
if (pre_set_irqv) irqv_d[7:0] <= did[ 7:0];
rst_rq[15:0] <= ({15{rst_rqs}} & did[15:0]) | rst_rq_inta[15:0];
dis_rq[15:0] <= ({15{dis_rqs}} & did[15:0]);
rst_rq[15:0] <= ({16{rst_rqs}} & did[15:0]) | rst_rq_inta[15:0];
dis_rq[15:0] <= ({16{dis_rqs}} & did[15:0]);
// en_rq [15:0] <= ({15{ en_rqs}} & did[15:0]);
inta_s[5:0] <= {inta_s[4:0], inta};
......
......@@ -539,10 +539,15 @@ module dqs2 (c0,/*c90,*/c270,
input c0,/*c90,*/c270,t;
inout UDQS, LDQS;
output udqsr90,ldqsr90,udqsr270,ldqsr270;
wire t0,t1,t2,tr;
wire t0,t1,tr;
///AF: wire t2;
FD_1 #(.INIT(1'b1)) i_t0 (.C(c0),.D(t),.Q(t0));
FD #(.INIT(1'b1)) i_t1 (.C(c0),.D(t0),.Q(t1));
FD #(.INIT(1'b1)) i_t2 (.C(c270),.D(t0),.Q(t2));
///AF: FD #(.INIT(1'b1)) i_t2 (.C(c270),.D(t0),.Q(t2));
assign tr= t1;
dqs2_0 i_dqsu(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({udqsr270,udqsr90}),.dq(UDQS));
dqs2_0 i_dqsl(.c0(c0),/*.c90(c90),*/.c270(c270),.t(tr),.q({ldqsr270,ldqsr90}),.dq(LDQS));
endmodule
module dqs2_0(c0,/*c90,*/c270,t,q,dq);
......@@ -563,7 +568,7 @@ module dqs2_0(c0,/*c90,*/c270,t,q,dq);
// as in IFDDRCPE.v
FDCPE_1 #(.INIT(1'b1)) i_q0 (.C(c270), .CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[0]));
FDCPE_1 #(.INIT(1'b0)) i_q0 (.C(c270), .CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[0]));
FDCPE i_q1 (.C(c270),.CE(1'b1),.CLR(1'b0),.D(qp),.PRE(1'b0),.Q(q[1]));
// synthesis attribute IOB of i_q0 is "TRUE"
// synthesis attribute IOB of i_q1 is "TRUE"
......@@ -577,7 +582,7 @@ endmodule
module sddrdm(c0,/*c90,*/c270,d,dq);
input c0,/*c90,*/c270;
input [1:0] d;
inout dq;
inout dq; //SuppressThisWarning Veditor UNUSED
sddrdm0 i_dq (.c0(c0),/*.c90(c90),*/.c270(c270),.d(d),.dq(dq));
// s--ynthesis attribute KEEP_HIERARCHY of i_dq is "TRUE"
endmodule
......
......@@ -260,7 +260,7 @@ module timestamp353( mclk, // system clock (negedge)
else if (hacti && !hact_d) vact_pend <= 1'b0;
if (hacti && !hact_d) odd_line <= !vact_pend && !odd_line;
// if (hacti && !hact_d) line[3:0] <= vact_pend?4'h1:{line[2:0],1'b0};
if (hacti && !hact_d) line[2:0] <= vact_pend?4'h1:{line[1:0],1'b0};
if (hacti && !hact_d) line[2:0] <= vact_pend ? 3'h1 : {line[1:0],1'b0};
if (hacti && !hact_d) ts_line <= tsmode[1]? (vact_pend || line[0] ) : (!vact_pend && (line[1] || line[2]));
......@@ -282,9 +282,9 @@ module timestamp353( mclk, // system clock (negedge)
// else ts_data[25:0]<= 16'h0;
ts_active_r <= ts_active;
ts_line_r <= ts_line;
if (ts_active_r) ts_data[25:0]<= {ts_data[24:0],1'b0};
else if (ts_line_r) ts_data[25:0]<= odd_line?sec[31:6]:{sec[5:0],usec[19:0]};
else ts_data[25:0]<= 16'h0;
if (ts_active_r) ts_data[25:0] <= {ts_data[24:0],1'b0};
else if (ts_line_r) ts_data[25:0] <= odd_line?sec[31:6]:{sec[5:0],usec[19:0]};
else ts_data[25:0] <= 26'h0;
end
endmodule
......
......@@ -135,7 +135,7 @@ FDCE_1 i_enable_mot_clk (.C(clk),.CE(we_ctl && di_d[1]),.CLR(1'b0),
// reset at simulation
assign sequence_next[1:0]=sequence[1:0]+1;
assign sequence_next[3:2]=(sequence[1:0]==3'b11)?((sequence[3:2]==3'b11)?2'b01:(sequence[3:2]+1)):sequence[3:2];
assign sequence_next[3:2]=(sequence[1:0]==2'b11)?((sequence[3:2]==2'b11)?2'b01:(sequence[3:2]+1)):sequence[3:2];
FD i_sequence_0(.C(xclk),.D(sequence_next[0]), .Q(sequence[0]));
FD i_sequence_1(.C(xclk),.D(sequence_next[1]), .Q(sequence[1]));
FD i_sequence_2(.C(xclk),.D(sequence_next[2]), .Q(sequence[2]));
......@@ -342,6 +342,9 @@ endmodule
/// Combine old (freom register file) /new encoded periods, inc/dec pulses to prepare a 6-bit (partial) index for a RAM table.
/// Together with the position error (another 6 bits) the full 12-bit undex provides 1 4-bit PWM code from the RAM table
/// Updates direction immediately, period - if inc_dec or when new period > saved period (so it will be updated even if the motor is stopped)
/// AF2015: Replace eith a function?
module calc_speed (clk, // posedge, 80 MHz
en_in, // enable (just for simulation), for real - let it on even when motors are off
process, // increment (with limit) period
......@@ -355,11 +358,11 @@ module calc_speed (clk, // posedge, 80 MHz
enc_period_this // [4:0] encoded period for the register file/ table index
);
parameter IGNORE_EN=1;
input clk; // posedge, 80MHz
input clk; // posedge, 80MHz // SuppressThisWarning Veditor UNUSED
input en_in; // enable, 0 resets period counter - simulation only
input process; // increment (with limit) period
input process; // increment (with limit) period // SuppressThisWarning Veditor UNUSED
input inc_dec; // encoder pulse detected
input inc; // encoder position increment
input inc; // encoder position increment // SuppressThisWarning Veditor UNUSED
input dec; // encoder position decrement
input [4:0] enc_period_curr; // encoded current period (still running if !inc_dec)
input dir_last; // last stored direction (from register file)
......@@ -560,14 +563,14 @@ module motor_pwm( clk, // posedge, 80MHz
output [2:0] new_pwm; // [2:0]
output [1:0] mot; // [1:0] - data to be copied to the motor outputs
reg [9:0] pwm_cycle_count;
reg [9:0] pwm_cycle_count; /// AF2015: Seems to be a bug - 2 MSBs are never used (only 8 LSB)
reg pwm_cycle_next;
reg [3:0] pwm_delay_count;
reg [3:0] pwm_delay_count; /// AF2015: Seems to be a bug - 1 MSB is never used (only 3 LSB)
reg pwm_delay_end;
reg [2:0] pwm_phase;
wire [2:0] spreaded_phase;
wire pwn_on;
wire pwn_off;
wire pwn_on; // SuppressThisWarning Veditor UNUSED
wire pwn_off; // SuppressThisWarning Veditor UNUSED
wire [2:0] new_pwm;
wire stop_cmd;
wire [3:0] pwm_diff;
......@@ -575,7 +578,7 @@ module motor_pwm( clk, // posedge, 80MHz
assign spreaded_phase[2:0]= pwm_phase[2:0]+spread[2:0];
assign pwn_on= pwm_cycle_next && (spreaded_phase == 0) && (pwm_code != 0);
assign pwn_off=pwm_cycle_next && (spreaded_phase == pwm_code);
assign pwn_off=pwm_cycle_next && (spreaded_phase == pwm_code[2:0]);
assign stop_cmd= !en || (pwm_code==8) ;
assign pwm_diff[3:0]={1'b0,pwm_code[2:0]}-{1'b0,spreaded_phase[2:0]};
......@@ -584,10 +587,14 @@ module motor_pwm( clk, // posedge, 80MHz
assign new_pwm[2]=!en || (pwm_cycle_next? (new_pwm[1:0]!=cur_pwm[1:0]):(cur_pwm[2]&& !pwm_delay_end));
assign mot[1:0]=(stop_cmd || new_pwm[2])? 2'b0:(new_pwm[1]?{new_pwm[0],!new_pwm[0]}:2'b11);
always @ (posedge clk) if (pre_first) begin // change these registers once per cycle of all motors
pwm_cycle_count<= (!en || (pwm_cycle_count==0))?pwm_cycle:(pwm_cycle_count-1);
/// AF2015: pwm_cycle_count<= (!en || (pwm_cycle_count==0)) ? pwm_cycle:(pwm_cycle_count-1);
pwm_cycle_count<= (!en || (pwm_cycle_count==0)) ? {2'b0,pwm_cycle}:(pwm_cycle_count-1);
pwm_cycle_next<= en && (pwm_cycle_count==0);
// pwm_delay_count<= (!en || (pwm_delay_count==0))?0:(pwm_cycle_next?pwm_delay: (pwm_delay_count-1));
pwm_delay_count<= (!en || pwm_cycle_next)?pwm_delay:((pwm_delay_count==0)?0: (pwm_delay_count-1));
/// AF2015: pwm_delay_count<= (!en || pwm_cycle_next)?pwm_delay:((pwm_delay_count==0)?0: (pwm_delay_count-1));
pwm_delay_count<= (!en || pwm_cycle_next)?{1'b0,pwm_delay}:((pwm_delay_count==0)? 4'b0: (pwm_delay_count-1));
pwm_delay_end<= en && (pwm_delay_count==1);
pwm_phase<= (!en)? 0: (pwm_phase + pwm_cycle_next); // divide by 8
end
......
......@@ -311,7 +311,7 @@ imu_timestamps i_imu_timestamps (
.ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored
.ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
.dout(timestamps_rdata[15:0]));// output data
wire [0:0] debug_state_unused;
wire [0:0] debug_state_unused; // SuppressThisWarning Veditor UNUSED
rs232_rcv i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles
.ser_di(ser_di), // rs232 (ttl) serial data in
......@@ -415,7 +415,7 @@ module logger_arbiter(xclk, // 80 MHz, posedge
reg [3:1] chn1hot; // channels 1-hot - granted and ready, priority applied
reg rq_not_zero; // at least one channel is ready for processing (same time as chn1hot[3:0])
reg [1:0] channel;
reg start;
///AF: reg start;
reg busy;
wire wstart;
reg ts_en;
......@@ -462,7 +462,7 @@ module logger_arbiter(xclk, // 80 MHz, posedge
channels_ready[2] & ~|channels_ready[1:0],
channels_ready[1] & ~channels_ready[0]};
start <= wstart;
///AF: start <= wstart;
if ((seq_cntr[4:0]=='h1e) || rst) busy <= 1'b0;
else if (rq_not_zero) busy <= 1'b1;
......@@ -765,10 +765,12 @@ module imu_spi ( sclk, // system clock, negedge
stall_dur[7:0] <= stall_dur_mclk[7:0];
bit_duration_zero <= (bit_duration[7:0]==8'h0);
clk_div[1:0]=en?(clk_div[1:0]+1):2'b0;
clk_en[3:0] <= {clk_en[2:0],clk_div[1:0]==2'h3};
clk_div[1:0] <= en?(clk_div[1:0]+1):2'b0;
clk_en[3:0] <= {clk_en[2:0],clk_div[1:0]==2'h3};
if (bit_duration_zero || (bit_duration_cntr[7:0]==8'h0)) bit_duration_cntr[7:0]<=bit_duration[7:0];
else bit_duration_cntr[7:0] <= bit_duration_cntr[7:0]-1;
clk_en[3:0] <= {clk_en[2:0],bit_duration_cntr[7:0]==8'h3}; // change 9'h3 to enforce frequency limit
end
......@@ -795,7 +797,7 @@ module imu_spi ( sclk, // system clock, negedge
else if (end_spi) seq_counter[9:0] <= 10'h001;
else if (clk_en[3] && (seq_state[1:0]!=2'h0) && !stall) seq_counter[9:0] <= seq_counter[9:0] - 1;
set_mosi_prepare <= clk_en[2] && first_prepare;
set_mosi_spi <= clk_en[2] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h1f) && (seq_counter[9:5]!=6'h0) && !stall; // last word use zero
set_mosi_spi <= clk_en[2] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h1f) && (seq_counter[9:5] != 5'h0) && !stall; // last word use zero
// no stall before the first word
if (!en) skip_stall <= 1'b0;
......@@ -1109,7 +1111,7 @@ module rs232_rcv (xclk, // half frequency (80 MHz nominal)
reg wait_just_pause;
wire wstart;
wire [4:0] debug;
reg [4:0] debug0; // {was_ts_stb, was_start, was_error, was_ser_di_1, was_ser_di_0} - once after reset
reg [4:0] debug0; // {was_ts_stb, was_start, was_error, was_ser_di_1, was_ser_di_0} - once after reset // SuppressThisWarning Veditor UNUSED
assign reset_wait_pause= (restart[1] && !restart[0]) || (wait_pause && !wait_start && !ser_di);
assign error=!ser_filt_di && last_half_bit && bit_half_end && receiving_byte;
assign sample_bit=shift_en && bit_half_end && !bit_cntr[0];
......@@ -1161,7 +1163,7 @@ module rs232_rcv (xclk, // half frequency (80 MHz nominal)
if (ser_rst) debug0[4:0] <=5'b0;
else debug0[4:0] <= debug | {ts_stb,start,error,ser_di_d,~ser_di_d};
else debug0[4:0] <= debug | {ts_stb,start,error,ser_di_d[0],~ser_di_d[0]};
end
endmodule
......@@ -1571,7 +1573,7 @@ module imu_timestamps (
rq_sclk2[1] & ~rq_sclk2[0],
rq_sclk2[0]};
pri_sclk_d[3:0] <= pri_sclk[3:0];
proc[9:0] <= {proc[9:0], wstart};
proc[9:0] <= {proc[8:0], wstart};
if (proc[0]) wa[3:2] <= {|pri_sclk_d[3:2], pri_sclk_d[3] | pri_sclk_d[1]};
if (proc[0]) sec_latched[31:0] <= sec[31:0];