Commit 49896216 authored by Andrey Filippov's avatar Andrey Filippov

modifying for co-simulation with 393

parent bbfa8af4
This diff is collapsed.
...@@ -229,6 +229,7 @@ module sensorpix( pclk, // clock (==pclk) ...@@ -229,6 +229,7 @@ module sensorpix( pclk, // clock (==pclk)
assign interp_data[9:0] = table_base_r[9:0]+table_mult_r[17:8]+table_mult_r[7]; //round assign interp_data[9:0] = table_base_r[9:0]+table_mult_r[17:8]+table_mult_r[7]; //round
assign cdata[7:0] = interp_data[9:2]; //truncate assign cdata[7:0] = interp_data[9:2]; //truncate
reg [7:0] pd_lenscorr_out_d2; // AF2015
always @ (posedge pclk) begin always @ (posedge pclk) begin
table_base[9:0] <= table_base_w[9:0]; table_base[9:0] <= table_base_w[9:0];
table_diff[10:0] <= table_diff_w[7]? table_diff[10:0] <= table_diff_w[7]?
...@@ -236,6 +237,7 @@ module sensorpix( pclk, // clock (==pclk) ...@@ -236,6 +237,7 @@ module sensorpix( pclk, // clock (==pclk)
{{4{table_diff_w[6]}},table_diff_w[6:0]}; {{4{table_diff_w[6]}},table_diff_w[6:0]};
/// dsat_r[7:0] <= dsat[7:0]; /// dsat_r[7:0] <= dsat[7:0];
pd_lenscorr_out_d[7:0] <= pd_lenscorr_out[7:0]; pd_lenscorr_out_d[7:0] <= pd_lenscorr_out[7:0];
pd_lenscorr_out_d2 <= pd_lenscorr_out_d; // AF2015 - one more cycle delay
table_mult_r[17:7] <= table_mult[17:7]; table_mult_r[17:7] <= table_mult[17:7];
table_base_r[ 9:0] <= table_base[ 9:0]; table_base_r[ 9:0] <= table_base[ 9:0];
end end
...@@ -244,7 +246,8 @@ module sensorpix( pclk, // clock (==pclk) ...@@ -244,7 +246,8 @@ module sensorpix( pclk, // clock (==pclk)
MULT18X18 i_table_mult ( MULT18X18 i_table_mult (
.P(table_mult), // 36-bit multiplier output .P(table_mult), // 36-bit multiplier output
.A({{7{table_diff[10]}},table_diff[10:0]}), // 18-bit multiplier input .A({{7{table_diff[10]}},table_diff[10:0]}), // 18-bit multiplier input
.B({10'b0,pd_lenscorr_out_d[7:0]}) // 18-bit multiplier input // .B({10'b0,pd_lenscorr_out_d[7:0]}) // 18-bit multiplier input
.B({10'b0,pd_lenscorr_out_d2[7:0]}) // 18-bit multiplier input // AF2015 - one more cycle delay
); );
...@@ -360,7 +363,8 @@ module sensorpix( pclk, // clock (==pclk) ...@@ -360,7 +363,8 @@ module sensorpix( pclk, // clock (==pclk)
/// NOTE: adding 5 cycles here /// NOTE: adding 5 cycles here
SRL16 i_hact_dly3 (.Q(hact_dly3), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(pclk), .D(hact_m)); // dly=2+1+5 SRL16 i_hact_dly3 (.Q(hact_dly3), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(pclk), .D(hact_m)); // dly=2+1+5
SRL16 i_en_out (.Q(en_out), .A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(en)); // dly=5+1+5 SRL16 i_en_out (.Q(en_out), .A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(en)); // dly=5+1+5
SRL16 i_hact_outp (.Q(hact_outp), .A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(hact_m)); // dly=5+1+5 //AF2015 SRL16 i_hact_outp (.Q(hact_outp), .A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(hact_m)); // dly=5+1+5
SRL16 i_hact_outp (.Q(hact_outp), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(hact_m)); // dly=5+1+5
assign incbwa= (dwe && (wa[7:0]==8'hff)) || (|wa[7:0] && !hact_out); assign incbwa= (dwe && (wa[7:0]==8'hff)) || (|wa[7:0] && !hact_out);
always @ (posedge pclk) begin always @ (posedge pclk) begin
wpage <= incbwa; wpage <= incbwa;
......
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...@@ -35,7 +35,8 @@ module testbench353(); ...@@ -35,7 +35,8 @@ module testbench353();
parameter SYNC_BIT_LENGTH=8-1; /// 7 pixel clock pulses parameter SYNC_BIT_LENGTH=8-1; /// 7 pixel clock pulses
parameter FPGA_XTRA_CYCLES= 1500; // 1072+; parameter FPGA_XTRA_CYCLES= 1500; // 1072+;
parameter HISTOGRAM_LEFT= 0; //2; // left parameter HISTOGRAM_LEFT= 0; //2; // left
parameter HISTOGRAM_TOP = 2; // top // parameter HISTOGRAM_TOP = 2; // top
parameter HISTOGRAM_TOP = 8; // top - otherwise no time to erase
parameter HISTOGRAM_WIDTH= 6; // width parameter HISTOGRAM_WIDTH= 6; // width
parameter HISTOGRAM_HEIGHT=6; // height parameter HISTOGRAM_HEIGHT=6; // height
parameter CLK0_PER = 6.25; //160MHz parameter CLK0_PER = 6.25; //160MHz
...@@ -1122,7 +1123,8 @@ $display ("saturation=2"); ...@@ -1122,7 +1123,8 @@ $display ("saturation=2");
// cpu_wr('h62,'h0c002400); // JP46 - mode 2 // cpu_wr('h62,'h0c002400); // JP46 - mode 2
cpu_wr('h62,'h0c000006); // mode - single cpu_wr('h62,'h0c000006); // mode - single
cpu_wr('h62, 'h4e000000 | 'h4 );// bayer=0 cpu_wr('h62, 'h4e000000 | 'h4 );// bayer=0
cpu_wr('h64, 'h4e000000 | 'h5 );// bayer=1 //AF2015 cpu_wr('h64, 'h4e000000 | 'h5 );// bayer=1
cpu_wr('h65, 'h4e000000 | 'h5 );// bayer=1 AF2015 - make it later to compare with 393
/* /*
AX(0x000000): writing 0x000000 to 0x31 AX(0x000000): writing 0x000000 to 0x31
...@@ -1141,11 +1143,13 @@ $display ("saturation=2"); ...@@ -1141,11 +1143,13 @@ $display ("saturation=2");
// Lens flat field correction // Lens flat field correction
cpu_wr('h62,'h31000000); // [AX] => 0x0 // cpu_wr('h62,'h31000000); // [AX] => 0x0
cpu_wr('h62,'h31080000); // [AY] => 0 // cpu_wr('h62,'h31080000); // [AY] => 0
cpu_wr('h62,'h31108000); // [C] => 0x8000 cpu_wr('h62,'h31108000); // [C] => 0x8000
cpu_wr('h62,'h31200000); // [BX] => 0 cpu_wr('h62,'h31380000); // [BX] => 0x180000; // 0
cpu_wr('h62,'h31400000); // [BY] => 0 cpu_wr('h62,'h31580000); // [BY] => 0x180000; // 0
// cpu_wr('h62,'h31200000); // [BX] => 0x180000; // 0
// cpu_wr('h62,'h31400000); // [BY] => 0x180000; // 0
cpu_wr('h62,'h31608000); // [scales0] => 32768 cpu_wr('h62,'h31608000); // [scales0] => 32768
cpu_wr('h62,'h31628000); // [scales1] => 32768 cpu_wr('h62,'h31628000); // [scales1] => 32768
...@@ -1155,11 +1159,14 @@ $display ("saturation=2"); ...@@ -1155,11 +1159,14 @@ $display ("saturation=2");
cpu_wr('h62,'h31690000); // [fatzero_out] => 0 cpu_wr('h62,'h31690000); // [fatzero_out] => 0
cpu_wr('h62,'h316a0001); // [post_scale] => 3 - X cpu_wr('h62,'h316a0001); // [post_scale] => 3 - X
cpu_wr('h63,'h31020000); // [AX] => 0x20000 // cpu_wr('h63,'h31020000); // [AX] => 0x20000
cpu_wr('h63,'h310a0000); // [AY] => 0x20000 // cpu_wr('h63,'h310a0000); // [AY] => 0x20000
cpu_wr('h62,'h31020000); // [AX] => 0x20000
cpu_wr('h62,'h310a0000); // [AY] => 0x20000
cpu_wr('h64,'h31200000); // [BX] => 0x180000 // TODO: move to 'h62 (together with 393)
cpu_wr('h64,'h31400000); // [BY] => 0x180000 // cpu_wr('h64,'h31200000); // [BX] => 0x180000
// cpu_wr('h64,'h31400000); // [BY] => 0x180000
`ifdef CONTINUOUS_COMPRESSION `ifdef CONTINUOUS_COMPRESSION
TEST_TITLE = "START_CONTINUOUS_COMPRESSION"; TEST_TITLE = "START_CONTINUOUS_COMPRESSION";
......
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