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Commit 49896216 authored by Andrey Filippov's avatar Andrey Filippov
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modifying for co-simulation with 393

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sensor/histogram353.v
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/*
** -----------------------------------------------------------------------------**
** histogram.v
**
** Calculation of image histograms
**
** Copyright (C) 2005-2010 Elphel, Inc.
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
module histogram (pclk, // pixel clock (posedge, only some input signals
pclk2x, // pclk multiplied by 2
sclk, // global (commands @negedge)
wen, // @negedge sclk, 1 ahead of write enable/read enable
rnext, // read histogram, increment address
wa, // [2:0] register address:
// old - 00 - {top, left}
// old - 01 - {height-1, width-1}
// old - 02 - hist. data start address (will also read pointed word to output word
// 00 - left
// 01 - top
// 02 - width-1
// 03 - height-1
// 04 - hist. data start address (will also read pointed word to output word
/*
** -----------------------------------------------------------------------------**
** histogram.v
**
** Calculation of image histograms
**
** Copyright (C) 2005-2010 Elphel, Inc.
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
module histogram (pclk, // pixel clock (posedge, only some input signals
pclk2x, // pclk multiplied by 2
sclk, // global (commands @negedge)
wen, // @negedge sclk, 1 ahead of write enable/read enable
rnext, // read histogram, increment address
wa, // [2:0] register address:
// old - 00 - {top, left}
// old - 01 - {height-1, width-1}
// old - 02 - hist. data start address (will also read pointed word to output word
// 00 - left
// 01 - top
// 02 - width-1
// 03 - height-1
// 04 - hist. data start address (will also read pointed word to output word
hist_do, // [31:0] histogram data (actually now just [17:0])
// 256*R, 256*Gr, 256*Gb, 256*B
wd, // [31:0] PIO data to write
frame_run, // frame active - @posedge pclk
line_run_a, // hact_out @posedge pclk
di_a, // [15:0] @posedge pclk
di_vld_a, // di[15:0] valid @posedge pclk
bayer_phase // [1:0]
);
input pclk;
input pclk2x;
input sclk;
input wen;
input rnext;
input [ 2:0] wa;
output [31:0] hist_do;
// input [15:0] wd;
input [15:0] wd;
input frame_run;
input line_run_a;
input [15:0] di_a;
input di_vld_a;
input [ 1:0] bayer_phase;
wire [17:0] hist_do0;
// extra layer of registers
reg line_run;
reg [15:0] di;
reg pre_di_vld, di_vld;
always @(posedge pclk) begin
line_run <= line_run_a;
di[15:0] <= di_a[15:0];
// di_vld <= di_vld_a;
end
always @ (posedge pclk2x) begin
pre_di_vld <= di_vld_a;
di_vld <= pre_di_vld; // so di_vld can be duplicated
end
// In Model 353 switching to 2x multipled pixel clock without it did not work when sclk < 2 * pclk
// pixels always go in pairs (low/high byte of di)
reg [15:0] di2x;
reg [ 3:0] dvld2x; // dvld2x[0] is valid second half di_vld, dvld2x[1] - 1 pclk2x cycle later, dvld2x[2] - 2 cycles
reg [ 1:0] bayer;
reg [ 1:0] bayer_phase_latched;
reg [ 9:0] hist_waddr; // histogram memory address (write side) - {color,pixel_value}
reg [ 9:0] hist_waddr_hold1; // hist_waddr - first hold register (latency read-increment-write)
reg [ 9:0] hist_waddr_hold2; // hist_waddr - second hold register (latency read-increment-write)
reg same_waddr; // same pixel value (use previous result instead of memory as it is not written yet)
reg pre_same_addr;
reg [ 2:0] frame_run_s;
reg [ 2:0] line_run_s;
reg line_start,line_end;
reg frame_start;
// reg frame_end;
reg [ 5:0] hist_seq; // delay line for the histogram calculation sequencer (each other bit can be active)
reg [ 9:0] hist_init_cntr;
reg end_hist_init;
reg [17:0] hist_pre; // previous value of the histogram - before increment
reg [17:0] hist_post; // new value of the histogram - after increment
wire hist_bank; // use FD so it will be reset at power up for simulation
reg odd_line;
reg [13:1] pix_cntr;
reg [13:1] line_cntr;
reg line_started, // left margin over
line_ended; // right margin
reg frame_started;// top margin over
reg frame_ended; // bottom margin
// reg frame_ended_d;
reg init_hist; // write zeros to all hist elements.
reg init_hist_d;
reg window_on; // window active
// increased dimesions to 8K
reg [13:1] pos_left; // all dimensions will be even (to simplify processing pixel data packed in pairs)
reg [13:1] pos_top;
reg [13:1] size_width;
reg [13:1] size_height;
reg [1:0] we_pos;
reg [1:0] we_size;
reg we_addr;
reg we_addr_d;
// reg rd_hist;
wire rd_hist;
reg [ 9:0] hist_raddr; // histogram memory address (read side) - {color,pixel_value}
reg hist_wea;
reg hist_ena;
reg bayer_en; // enable latching bayer
reg last_line;
wire [17:0] hist_doa; // RAM output
wire [17:0] hist_dia= hist_post[17:0]; // RAM input
reg [15:0] wdd; // wd[15:0] delayed by 1 clock
reg [13:1] minus_pos_left; // TIG
reg pos_left_is_zero; // TIG
reg line_start_posl_zero; // start with pos_left_is_zero
reg line_start_posl_nzero; // start with !pos_left_is_zero
assign rd_hist = rnext || we_addr_d;
assign hist_do[31:0]={14'h0,hist_do0[17:0]};
/*
//debug
reg [9:0] test_cntr;
always @ (posedge pclk2x) if (frame_run_s[1] && !frame_run_s[2]) begin
test_cntr[9:0] <= test_cntr[9:0]+1;
end
assign hist_do[31:0]={1'h0,frame_run_s[1],hist_bank,test_cntr[9:0],frame_run,hist_do0[17:0]}; /// Temporary testing !!!
// assign hist_do[31:0]={1'h0,hist_bank,hist_raddr[9:0],2'h0,hist_do0[17:0]}; /// Temporary testing !!!
*/
// FDE i_hist_bank (.C(pclk2x), .CE(frame_end), .D(~hist_bank), .Q(hist_bank));
// switch bank at the start of frame
FDE i_hist_bank (.C(pclk2x), .CE(init_hist & ~init_hist_d), .D(~hist_bank), .Q(hist_bank));
always @ (posedge pclk2x) begin
frame_run_s[2:0] <= {frame_run_s[1:0],frame_run};
line_run_s[2:0] <= {line_run_s[1:0], line_run};
line_start <= line_run_s[1] && !line_run_s[2];
line_start_posl_zero <= line_run_s[1] && !line_run_s[2] && pos_left_is_zero;
line_start_posl_nzero <= line_run_s[1] && !line_run_s[2] && !pos_left_is_zero;
line_end <= line_run_s[2] && !line_run_s[1];
frame_start <= frame_run_s[1] && !frame_run_s[2];
// frame_end <= (frame_ended && !frame_ended_d);
bayer_en <= frame_start || (bayer_en && !line_start);
if (bayer_en) bayer_phase_latched[1:0] <=bayer_phase[1:0];
if (!frame_run_s[2]) hist_init_cntr[9:0] <= 10'b0;
else if (init_hist) hist_init_cntr[9:0] <= hist_init_cntr[9:0] + 1;
// 256*R, 256*Gr, 256*Gb, 256*B
wd, // [31:0] PIO data to write
frame_run, // frame active - @posedge pclk
line_run_a, // hact_out @posedge pclk
di_a, // [15:0] @posedge pclk
di_vld_a, // di[15:0] valid @posedge pclk
bayer_phase // [1:0]
);
input pclk;
input pclk2x;
input sclk;
input wen;
input rnext;
input [ 2:0] wa;
output [31:0] hist_do;
// input [15:0] wd;
input [15:0] wd;
input frame_run;
input line_run_a;
input [15:0] di_a;
input di_vld_a;
input [ 1:0] bayer_phase;
parameter correct_bayer=2'b11; //AF2015: Correct Bayer to have histogram [2'b00] matcsh even row, even column data
wire [17:0] hist_do0;
// extra layer of registers
reg line_run;
reg [15:0] di;
reg pre_di_vld, di_vld;
always @(posedge pclk) begin
line_run <= line_run_a;
di[15:0] <= di_a[15:0];
// di_vld <= di_vld_a;
end
always @ (posedge pclk2x) begin
pre_di_vld <= di_vld_a;
di_vld <= pre_di_vld; // so di_vld can be duplicated
end
// In Model 353 switching to 2x multipled pixel clock without it did not work when sclk < 2 * pclk
// pixels always go in pairs (low/high byte of di)
reg [15:0] di2x;
reg [ 3:0] dvld2x; // dvld2x[0] is valid second half di_vld, dvld2x[1] - 1 pclk2x cycle later, dvld2x[2] - 2 cycles
reg [ 1:0] bayer;
reg [ 1:0] bayer_phase_latched;
reg [ 9:0] hist_waddr; // histogram memory address (write side) - {color,pixel_value}
reg [ 9:0] hist_waddr_hold1; // hist_waddr - first hold register (latency read-increment-write)
reg [ 9:0] hist_waddr_hold2; // hist_waddr - second hold register (latency read-increment-write)
reg same_waddr; // same pixel value (use previous result instead of memory as it is not written yet)
reg pre_same_addr;
reg [ 2:0] frame_run_s;
reg [ 2:0] line_run_s;
reg line_start,line_end;
reg frame_start;
// reg frame_end;
reg [ 5:0] hist_seq; // delay line for the histogram calculation sequencer (each other bit can be active)
reg [ 9:0] hist_init_cntr;
reg end_hist_init;
reg [17:0] hist_pre; // previous value of the histogram - before increment
reg [17:0] hist_post; // new value of the histogram - after increment
wire hist_bank; // use FD so it will be reset at power up for simulation
reg odd_line;
reg [13:1] pix_cntr;
reg [13:1] line_cntr;
reg line_started, // left margin over
line_ended; // right margin
reg frame_started;// top margin over
reg frame_ended; // bottom margin
// reg frame_ended_d;
reg init_hist; // write zeros to all hist elements.
reg init_hist_d;
reg window_on; // window active
// increased dimesions to 8K
reg [13:1] pos_left; // all dimensions will be even (to simplify processing pixel data packed in pairs)
reg [13:1] pos_top;
reg [13:1] size_width;
reg [13:1] size_height;
reg [1:0] we_pos;
reg [1:0] we_size;
reg we_addr;
reg we_addr_d;
// reg rd_hist;
wire rd_hist;
reg [ 9:0] hist_raddr; // histogram memory address (read side) - {color,pixel_value}
reg hist_wea;
reg hist_ena;
reg bayer_en; // enable latching bayer
reg last_line;
wire [17:0] hist_doa; // RAM output
wire [17:0] hist_dia= hist_post[17:0]; // RAM input
reg [15:0] wdd; // wd[15:0] delayed by 1 clock
reg [13:1] minus_pos_left; // TIG
reg pos_left_is_zero; // TIG
reg line_start_posl_zero; // start with pos_left_is_zero
reg line_start_posl_nzero; // start with !pos_left_is_zero
assign rd_hist = rnext || we_addr_d;
assign hist_do[31:0]={14'h0,hist_do0[17:0]};
/*
//debug
reg [9:0] test_cntr;
always @ (posedge pclk2x) if (frame_run_s[1] && !frame_run_s[2]) begin
test_cntr[9:0] <= test_cntr[9:0]+1;
end
assign hist_do[31:0]={1'h0,frame_run_s[1],hist_bank,test_cntr[9:0],frame_run,hist_do0[17:0]}; /// Temporary testing !!!
// assign hist_do[31:0]={1'h0,hist_bank,hist_raddr[9:0],2'h0,hist_do0[17:0]}; /// Temporary testing !!!
*/
// FDE i_hist_bank (.C(pclk2x), .CE(frame_end), .D(~hist_bank), .Q(hist_bank));
// switch bank at the start of frame
FDE i_hist_bank (.C(pclk2x), .CE(init_hist & ~init_hist_d), .D(~hist_bank), .Q(hist_bank));
always @ (posedge pclk2x) begin
frame_run_s[2:0] <= {frame_run_s[1:0],frame_run};
line_run_s[2:0] <= {line_run_s[1:0], line_run};
line_start <= line_run_s[1] && !line_run_s[2];
line_start_posl_zero <= line_run_s[1] && !line_run_s[2] && pos_left_is_zero;
line_start_posl_nzero <= line_run_s[1] && !line_run_s[2] && !pos_left_is_zero;
line_end <= line_run_s[2] && !line_run_s[1];
frame_start <= frame_run_s[1] && !frame_run_s[2];
// frame_end <= (frame_ended && !frame_ended_d);
bayer_en <= frame_start || (bayer_en && !line_start);
if (bayer_en) bayer_phase_latched[1:0] <=bayer_phase[1:0];
if (!frame_run_s[2]) hist_init_cntr[9:0] <= 10'b0;
else if (init_hist) hist_init_cntr[9:0] <= hist_init_cntr[9:0] + 1;
end_hist_init <= (hist_init_cntr[9:1]==9'h1ff);
init_hist <= frame_run_s[1] && (init_hist?(~end_hist_init):~frame_run_s[2]);
init_hist_d <= init_hist;
if (!init_hist) hist_init_cntr[9:0] <= 10'h0;
init_hist <= frame_run_s[1] && (init_hist?(~end_hist_init):~frame_run_s[2]);
init_hist_d <= init_hist;
if (!init_hist) hist_init_cntr[9:0] <= 10'h0;
else hist_init_cntr[9:0] <= hist_init_cntr[9:0] + 1;
dvld2x[3:0] <= {dvld2x[2:0], ~(|dvld2x[2:0]) & di_vld };
// include window_on (don't start if not)
// hist_seq[5:0] <= {hist_seq[4:0], dvld2x[1] | dvld2x[3]};
hist_seq[5:0] <= {hist_seq[4:0], window_on && (dvld2x[1] | dvld2x[3])};
hist_ena <= hist_seq[0] || hist_seq[5] || init_hist; // read, write, clear
hist_wea <= hist_seq[5] || init_hist; // write, clear
// get 8-bit pixels from 16-bit packed words
if (dvld2x[0]) di2x[15:8] <= di[15:8];
if (dvld2x[0]) di2x[ 7:0] <= di[ 7:0];
else if (dvld2x[2]) di2x[ 7:0] <= di2x[15:8];
// calculate bayer phase of the pixel
// reg [ 1:0] bayer_phase_latched;
// if (dvld2x[0]) bayer[0] <= bayer_phase[0];
if (dvld2x[0]) bayer[0] <= 1'b0;
else if (dvld2x[2]) bayer[0] <= ~bayer[0];
// if (frame_start) bayer[1] <= bayer_phase[1];
if (frame_start) bayer[1] <= 1'b0;
else if (line_start) bayer[1] <= ~bayer[1];
if (hist_seq[1]) hist_waddr_hold1[9:0] <= hist_waddr[9:0];
if (hist_seq[3]) hist_waddr_hold2[9:0] <= hist_waddr_hold1[9:0];
// we need to clear all histogram at the begining of a frame (will not work if the window is too small)
if (init_hist) hist_waddr[9:0] <= hist_init_cntr[9:0]; // to clear histogram memory
else if (hist_seq[0]) hist_waddr[9:0] <= {bayer[1:0]^bayer_phase_latched[1:0],di2x[7:0]};
else if (hist_seq[5]) hist_waddr[9:0] <= {hist_waddr_hold2[9:0]};
/* same_waddr <= hist_seq[0] && // next cycle - read from memory
hist_seq[4] && // second next cycle - write modified
(di2x[7:0] == hist_waddr_hold2[7:0]); // same address (colors should be the same - same line, over one pixel)
*/
pre_same_addr <= (di2x[7:0] == hist_waddr_hold2[7:0]);
same_waddr <= hist_seq[1] && // next cycle - read from memory
hist_seq[5] && // second next cycle - write modified
pre_same_addr;
if (hist_seq[2]) hist_pre[17:0] <= same_waddr? hist_post[17:0] : hist_doa[17:0]; // bypass memory for the same histogram count/color
// hist_pre[17:0] -> hist_post[17:0] - dual cycle
// data to write to histogram memory
if (init_hist) hist_post[17:0] <= 18'h0; // to write 0 to all histogram page memory locations
else if (hist_seq[4] && (hist_pre[17:0]!=18'h3ffff)) hist_post[17:0] <= hist_pre[17:0] + 1; // saturate
// odd/even scan lines
if (frame_start) odd_line <= 1'b1;
else if (line_end) odd_line <= ~odd_line;
minus_pos_left[13:1] <= -pos_left[13:1]; // TIG
pos_left_is_zero <= (pos_left[13:1]==13'h0); // TIG
// count pixels (in pairs) to determine active window
// if (line_start) pix_cntr[13:1] <= ~pos_left[13:1];
// else if (dvld2x[1]) pix_cntr[13:1] <= pix_cntr[13:1]+1; // window_on will switch right after dvld2x[3]
if (line_start) pix_cntr[13:1] <= minus_pos_left[13:1]; // @dvld2x[0]
else if (dvld2x[0]) pix_cntr[13:1] <= pix_cntr[13:1]+1; // (may change to dvld2x[2])window_on will switch right after dvld2x[3]
if (line_start_posl_nzero || !frame_run_s[2]) line_started <= 1'h0;
else if (line_start_posl_zero || (dvld2x[2] &&((~pix_cntr[13:1])== 13'h0))) line_started <= 1'h1; // Doublecycle
if (line_start || !frame_run_s[2]) line_ended <= 1'h0;
else if (dvld2x[2] && line_started && (pix_cntr[13:1] == size_width[13:1])) line_ended <= 1'h1; // Doublecycle
if (frame_start) line_cntr[13:1] <= ~pos_top[13:1];
else if (line_end && !odd_line) line_cntr[13:1] <= line_cntr[13:1]+1;
if (!frame_run_s[2]) frame_started <= 1'h0;
else if ((~line_cntr[13:1])== 13'h0) frame_started <= 1'h1;
last_line <= (line_cntr[13:1] == size_height[13:1]);
if (!frame_run_s[2]) frame_ended <= 1'h0;
else if ((line_start && frame_started && last_line) || (frame_run_s[2] && ! frame_run_s[1])) frame_ended <= 1'h1;
// frame_ended_d <= frame_ended;
// window_on <= (line_start_posl_zero || line_started) && !line_ended && frame_started && !frame_ended;
window_on <= (line_start_posl_zero || (line_started && !line_ended)) && frame_started && !frame_ended;
end
always @ (negedge sclk) begin
wdd[15:0] <= wd[15:0];
we_pos[1:0] <= {wen && (wa[2:0]==3'h1), wen && (wa[2:0]==3'h0)};
we_size[1:0] <= {wen && (wa[2:0]==3'h3), wen && (wa[2:0]==3'h2)};
we_addr <= wen && (wa[2:0]==3'h4);
we_addr_d <= we_addr;
if (we_pos[0]) pos_left[13:1] <= wdd[13: 1];
if (we_pos[1]) pos_top[13:1] <= wdd[13: 1];
if (we_size[0]) size_width[13:1] <= wdd[13: 1];
if (we_size[1]) size_height[13:1] <= wdd[13: 1];
if (we_addr) hist_raddr[9:0] <= wdd[9:0];
else if (rd_hist) hist_raddr[9:0] <= hist_raddr[9:0] + 1;
end
// port A - histogram calculation
// port B - histogram readout
RAMB16_S9_S9 i_hist_low (
.DOA(hist_doa[7:0]), // Port A 8-bit Data Output
.DOPA(hist_doa[8]), // Port A 1-bit Parity Output
.ADDRA({hist_bank,hist_waddr[9:0]}), // Port A 11-bit Address Input
.CLKA( pclk2x), // Port A Clock
.DIA(hist_dia[7:0]), // Port A 8-bit Data Input
.DIPA(hist_dia[8]), // Port A 1-bit parity Input
.ENA(hist_ena), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(hist_wea), // Port A Write Enable Input
.DOB(hist_do0[7:0]), // Port B 8-bit Data Output
.DOPB(hist_do0[8]), // Port B 1-bit Parity Output
.ADDRB({~hist_bank,hist_raddr[9:0]}), // Port B 11-bit Address Input
.CLKB(!sclk), // Port B Clock
.DIB(8'h0), // Port B 8-bit Data Input
.DIPB(1'h0), // Port-B 1-bit parity Input
.ENB(rd_hist), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
RAMB16_S9_S9 i_hist_high (
.DOA(hist_doa[16:9]), // Port A 8-bit Data Output
.DOPA(hist_doa[17]), // Port A 1-bit Parity Output
.ADDRA({hist_bank,hist_waddr[9:0]}), // Port A 11-bit Address Input
.CLKA( pclk2x), // Port A Clock
.DIA(hist_dia[16:9]), // Port A 8-bit Data Input
.DIPA(hist_dia[17]), // Port A 1-bit parity Input
.ENA(hist_ena), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(hist_wea), // Port A Write Enable Input
.DOB(hist_do0[16:9]), // Port B 8-bit Data Output
.DOPB(hist_do0[17]), // Port B 1-bit Parity Output
.ADDRB({~hist_bank,hist_raddr[9:0]}), // Port B 11-bit Address Input
.CLKB(!sclk), // Port B Clock
.DIB(8'h0), // Port B 8-bit Data Input
.DIPB(1'h0), // Port-B 1-bit parity Input
.ENB(rd_hist), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
endmodule
dvld2x[3:0] <= {dvld2x[2:0], ~(|dvld2x[2:0]) & di_vld };
// include window_on (don't start if not)
// hist_seq[5:0] <= {hist_seq[4:0], dvld2x[1] | dvld2x[3]};
hist_seq[5:0] <= {hist_seq[4:0], window_on && (dvld2x[1] | dvld2x[3])};
hist_ena <= hist_seq[0] || hist_seq[5] || init_hist; // read, write, clear
hist_wea <= hist_seq[5] || init_hist; // write, clear
// get 8-bit pixels from 16-bit packed words
if (dvld2x[0]) di2x[15:8] <= di[15:8];
if (dvld2x[0]) di2x[ 7:0] <= di[ 7:0];
else if (dvld2x[2]) di2x[ 7:0] <= di2x[15:8];
// calculate bayer phase of the pixel
// reg [ 1:0] bayer_phase_latched;
// if (dvld2x[0]) bayer[0] <= bayer_phase[0];
if (dvld2x[0]) bayer[0] <= 1'b0;
else if (dvld2x[2]) bayer[0] <= ~bayer[0];
// if (frame_start) bayer[1] <= bayer_phase[1];
if (frame_start) bayer[1] <= 1'b0;
else if (line_start) bayer[1] <= ~bayer[1];
if (hist_seq[1]) hist_waddr_hold1[9:0] <= hist_waddr[9:0];
if (hist_seq[3]) hist_waddr_hold2[9:0] <= hist_waddr_hold1[9:0];
// we need to clear all histogram at the begining of a frame (will not work if the window is too small)
if (init_hist) hist_waddr[9:0] <= hist_init_cntr[9:0]; // to clear histogram memory
else if (hist_seq[0]) hist_waddr[9:0] <= {bayer[1:0]^bayer_phase_latched[1:0] ^ correct_bayer,di2x[7:0]};
else if (hist_seq[5]) hist_waddr[9:0] <= {hist_waddr_hold2[9:0]};
/* same_waddr <= hist_seq[0] && // next cycle - read from memory
hist_seq[4] && // second next cycle - write modified
(di2x[7:0] == hist_waddr_hold2[7:0]); // same address (colors should be the same - same line, over one pixel)
*/
pre_same_addr <= (di2x[7:0] == hist_waddr_hold2[7:0]);
same_waddr <= hist_seq[1] && // next cycle - read from memory
hist_seq[5] && // second next cycle - write modified
pre_same_addr;
if (hist_seq[2]) hist_pre[17:0] <= same_waddr? hist_post[17:0] : hist_doa[17:0]; // bypass memory for the same histogram count/color
// hist_pre[17:0] -> hist_post[17:0] - dual cycle
// data to write to histogram memory
if (init_hist) hist_post[17:0] <= 18'h0; // to write 0 to all histogram page memory locations
else if (hist_seq[4] && (hist_pre[17:0]!=18'h3ffff)) hist_post[17:0] <= hist_pre[17:0] + 1; // saturate
// odd/even scan lines
if (frame_start) odd_line <= 1'b1;
else if (line_end) odd_line <= ~odd_line;
minus_pos_left[13:1] <= -pos_left[13:1]; // TIG
pos_left_is_zero <= (pos_left[13:1]==13'h0); // TIG
// count pixels (in pairs) to determine active window
// if (line_start) pix_cntr[13:1] <= ~pos_left[13:1];
// else if (dvld2x[1]) pix_cntr[13:1] <= pix_cntr[13:1]+1; // window_on will switch right after dvld2x[3]
if (line_start) pix_cntr[13:1] <= minus_pos_left[13:1]; // @dvld2x[0]
else if (dvld2x[0]) pix_cntr[13:1] <= pix_cntr[13:1]+1; // (may change to dvld2x[2])window_on will switch right after dvld2x[3]
if (line_start_posl_nzero || !frame_run_s[2]) line_started <= 1'h0;
else if (line_start_posl_zero || (dvld2x[2] &&((~pix_cntr[13:1])== 13'h0))) line_started <= 1'h1; // Doublecycle
if (line_start || !frame_run_s[2]) line_ended <= 1'h0;
else if (dvld2x[2] && line_started && (pix_cntr[13:1] == size_width[13:1])) line_ended <= 1'h1; // Doublecycle
if (frame_start) line_cntr[13:1] <= ~pos_top[13:1];
else if (line_end && !odd_line) line_cntr[13:1] <= line_cntr[13:1]+1;
if (!frame_run_s[2]) frame_started <= 1'h0;
else if ((~line_cntr[13:1])== 13'h0) frame_started <= 1'h1;
last_line <= (line_cntr[13:1] == size_height[13:1]);
if (!frame_run_s[2]) frame_ended <= 1'h0;
else if ((line_start && frame_started && last_line) || (frame_run_s[2] && ! frame_run_s[1])) frame_ended <= 1'h1;
// frame_ended_d <= frame_ended;
// window_on <= (line_start_posl_zero || line_started) && !line_ended && frame_started && !frame_ended;
//AF2015 window_on <= (line_start_posl_zero || (line_started && !line_ended)) && frame_started && !frame_ended;
window_on <= (line_start_posl_zero || (line_started && !line_ended)) && frame_started && !frame_ended && !(line_start && last_line) ;
end
always @ (negedge sclk) begin
wdd[15:0] <= wd[15:0];
we_pos[1:0] <= {wen && (wa[2:0]==3'h1), wen && (wa[2:0]==3'h0)};
we_size[1:0] <= {wen && (wa[2:0]==3'h3), wen && (wa[2:0]==3'h2)};
we_addr <= wen && (wa[2:0]==3'h4);
we_addr_d <= we_addr;
if (we_pos[0]) pos_left[13:1] <= wdd[13: 1];
if (we_pos[1]) pos_top[13:1] <= wdd[13: 1];
if (we_size[0]) size_width[13:1] <= wdd[13: 1];
if (we_size[1]) size_height[13:1] <= wdd[13: 1];
if (we_addr) hist_raddr[9:0] <= wdd[9:0];
else if (rd_hist) hist_raddr[9:0] <= hist_raddr[9:0] + 1;
end
// port A - histogram calculation
// port B - histogram readout
RAMB16_S9_S9 i_hist_low (
.DOA(hist_doa[7:0]), // Port A 8-bit Data Output
.DOPA(hist_doa[8]), // Port A 1-bit Parity Output
.ADDRA({hist_bank,hist_waddr[9:0]}), // Port A 11-bit Address Input
.CLKA( pclk2x), // Port A Clock
.DIA(hist_dia[7:0]), // Port A 8-bit Data Input
.DIPA(hist_dia[8]), // Port A 1-bit parity Input
.ENA(hist_ena), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(hist_wea), // Port A Write Enable Input
.DOB(hist_do0[7:0]), // Port B 8-bit Data Output
.DOPB(hist_do0[8]), // Port B 1-bit Parity Output
.ADDRB({~hist_bank,hist_raddr[9:0]}), // Port B 11-bit Address Input
.CLKB(!sclk), // Port B Clock
.DIB(8'h0), // Port B 8-bit Data Input
.DIPB(1'h0), // Port-B 1-bit parity Input
.ENB(rd_hist), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
RAMB16_S9_S9 i_hist_high (
.DOA(hist_doa[16:9]), // Port A 8-bit Data Output
.DOPA(hist_doa[17]), // Port A 1-bit Parity Output
.ADDRA({hist_bank,hist_waddr[9:0]}), // Port A 11-bit Address Input
.CLKA( pclk2x), // Port A Clock
.DIA(hist_dia[16:9]), // Port A 8-bit Data Input
.DIPA(hist_dia[17]), // Port A 1-bit parity Input
.ENA(hist_ena), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(hist_wea), // Port A Write Enable Input
.DOB(hist_do0[16:9]), // Port B 8-bit Data Output
.DOPB(hist_do0[17]), // Port B 1-bit Parity Output
.ADDRB({~hist_bank,hist_raddr[9:0]}), // Port B 11-bit Address Input
.CLKB(!sclk), // Port B Clock
.DIB(8'h0), // Port B 8-bit Data Input
.DIPB(1'h0), // Port-B 1-bit parity Input
.ENB(rd_hist), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
endmodule
sensor/sensorpix353.v
View file @ 49896216
......@@ -229,6 +229,7 @@ module sensorpix( pclk, // clock (==pclk)
assign interp_data[9:0] = table_base_r[9:0]+table_mult_r[17:8]+table_mult_r[7]; //round
assign cdata[7:0] = interp_data[9:2]; //truncate
reg [7:0] pd_lenscorr_out_d2; // AF2015
always @ (posedge pclk) begin
table_base[9:0] <= table_base_w[9:0];
table_diff[10:0] <= table_diff_w[7]?
......@@ -236,6 +237,7 @@ module sensorpix( pclk, // clock (==pclk)
{{4{table_diff_w[6]}},table_diff_w[6:0]};
/// dsat_r[7:0] <= dsat[7:0];
pd_lenscorr_out_d[7:0] <= pd_lenscorr_out[7:0];
pd_lenscorr_out_d2 <= pd_lenscorr_out_d; // AF2015 - one more cycle delay
table_mult_r[17:7] <= table_mult[17:7];
table_base_r[ 9:0] <= table_base[ 9:0];
end
......@@ -244,7 +246,8 @@ module sensorpix( pclk, // clock (==pclk)
MULT18X18 i_table_mult (
.P(table_mult), // 36-bit multiplier output
.A({{7{table_diff[10]}},table_diff[10:0]}), // 18-bit multiplier input
.B({10'b0,pd_lenscorr_out_d[7:0]}) // 18-bit multiplier input
// .B({10'b0,pd_lenscorr_out_d[7:0]}) // 18-bit multiplier input
.B({10'b0,pd_lenscorr_out_d2[7:0]}) // 18-bit multiplier input // AF2015 - one more cycle delay
);
......@@ -360,7 +363,8 @@ module sensorpix( pclk, // clock (==pclk)
/// NOTE: adding 5 cycles here
SRL16 i_hact_dly3 (.Q(hact_dly3), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CLK(pclk), .D(hact_m)); // dly=2+1+5
SRL16 i_en_out (.Q(en_out), .A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(en)); // dly=5+1+5
SRL16 i_hact_outp (.Q(hact_outp), .A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(hact_m)); // dly=5+1+5
//AF2015 SRL16 i_hact_outp (.Q(hact_outp), .A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(hact_m)); // dly=5+1+5
SRL16 i_hact_outp (.Q(hact_outp), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b1), .CLK(pclk), .D(hact_m)); // dly=5+1+5
assign incbwa= (dwe && (wa[7:0]==8'hff)) || (|wa[7:0] && !hact_out);
always @ (posedge pclk) begin
wpage <= incbwa;
......
x353_1.sav
View file @ 49896216
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sun Aug 9 03:27:09 2015
[*] Wed Aug 12 02:48:35 2015
[*]
[dumpfile] "/home/andrey/git/x353/simulation/x353_1-20150808211805694.fst"
[dumpfile_mtime] "Sun Aug 9 03:23:39 2015"
[dumpfile_size] 21847559
[dumpfile] "/home/andrey/git/x353/simulation/x353_1-20150811203732083.fst"
[dumpfile_mtime] "Wed Aug 12 02:43:52 2015"
[dumpfile_size] 21019007
[savefile] "/home/andrey/git/x353/x353_1.sav"
[timestart] 584523000
[timestart] 496214500
[size] 1823 1180
[pos] 1917 0
*-19.677540 584994800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] 0 0
*-14.654496 496288000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] testbench353.
[treeopen] testbench353.i_x353.
[treeopen] testbench353.i_x353.i_sensorpads.i_sensor_phase.
[treeopen] testbench353.i_x353.i_sensorpix.
[treeopen] testbench353.i_x353.i_sensorpix.i_lens_flat.
[treeopen] testbench353.i_x353.i_sysinterface.i_we.
[sst_width] 335
[sst_width] 317
[signals_width] 322
[sst_expanded] 1
[sst_vpaned_height] 625
[sst_vpaned_height] 624
@820
testbench353.TEST_TITLE[639:0]
@800200
-sensor_in
@800022
@c00022
testbench353.PXD[11:0]
@28
(0)testbench353.PXD[11:0]
......@@ -39,13 +39,13 @@ testbench353.PXD[11:0]
(9)testbench353.PXD[11:0]
(10)testbench353.PXD[11:0]
(11)testbench353.PXD[11:0]
@1001200
@1401200
-group_end
@28
testbench353.i_x353.HACT
testbench353.i_x353.VACT
testbench353.DCLK
@c00023
@c00022
>-128600
testbench353.i_x353.ipxd[15:0]
@28
......@@ -66,7 +66,7 @@ testbench353.i_x353.ipxd[15:0]
(13)testbench353.i_x353.ipxd[15:0]
(14)testbench353.i_x353.ipxd[15:0]
(15)testbench353.i_x353.ipxd[15:0]
@1401201
@1401200
-group_end
@c00022
>-149600
......@@ -132,9 +132,8 @@ testbench353.i_x353.i_timestamp353.use_ts
-
@1000200
-timestamp353
@800200
-lens_flat
@c00200
-lens_flat
-line_xy
@22
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.A0[18:0]
......@@ -186,7 +185,64 @@ testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.preERR[23:0]
-line_y
@200
-
@800022
@28
testbench353.i_x353.i_sensorpix.i_lens_flat.fstart
@200
-
@800200
-i_fy
@22
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.A0[18:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.A2X[23:1]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.A[18:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.ApB[23:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.B0[20:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.ERR0[23:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.ERR[23:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.F0[18:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.F1[18:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.F[18:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.dF[10:0]
@28
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.first
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.first_d
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.inc[1:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.next
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.next_d
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.pclk
@22
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fy.preERR[23:0]
@1000200
-i_fy
@c00200
-i_fxy
@22
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.A0[18:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.A2X[23:1]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.A[18:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.ApB[23:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.B0[20:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.ERR0[23:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.ERR[23:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.F0[18:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.F1[18:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.F[18:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.dF[10:0]
@28
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.first
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.first_d
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.inc[1:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.next
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.next_d
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.pclk
@22
testbench353.i_x353.i_sensorpix.i_lens_flat.i_fxy.preERR[23:0]
@1401200
-i_fxy
@28
testbench353.i_x353.i_sensorpix.i_lens_flat.wen
testbench353.i_x353.i_sensorpix.i_lens_flat.linerun
@c00022
testbench353.i_x353.i_sensorpix.i_lens_flat.pixdi[15:0]
@28
(0)testbench353.i_x353.i_sensorpix.i_lens_flat.pixdi[15:0]
......@@ -205,9 +261,11 @@ testbench353.i_x353.i_sensorpix.i_lens_flat.pixdi[15:0]
(13)testbench353.i_x353.i_sensorpix.i_lens_flat.pixdi[15:0]
(14)testbench353.i_x353.i_sensorpix.i_lens_flat.pixdi[15:0]
(15)testbench353.i_x353.i_sensorpix.i_lens_flat.pixdi[15:0]
@1001200
@1401200
-group_end
@800022
@28
(0)testbench353.i_x353.i_sensorpix.i_lens_flat.lens_corr_out[4:0]
@c00022
testbench353.i_x353.i_sensorpix.i_lens_flat.pixdo[15:0]
@28
(0)testbench353.i_x353.i_sensorpix.i_lens_flat.pixdo[15:0]
......@@ -226,8 +284,14 @@ testbench353.i_x353.i_sensorpix.i_lens_flat.pixdo[15:0]
(13)testbench353.i_x353.i_sensorpix.i_lens_flat.pixdo[15:0]
(14)testbench353.i_x353.i_sensorpix.i_lens_flat.pixdo[15:0]
(15)testbench353.i_x353.i_sensorpix.i_lens_flat.pixdo[15:0]
@1001200
@1401200
-group_end
@22
testbench353.i_x353.i_sensorpix.i_lens_flat.mult_first_res[35:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.mult_first_scaled[17:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.mult_second_res[35:0]
@200
-
@28
testbench353.i_x353.i_sensorpix.i_lens_flat.pclk
testbench353.i_x353.i_sensorpix.i_lens_flat.fstart
......@@ -236,7 +300,6 @@ testbench353.i_x353.i_sensorpix.i_lens_flat.linerun
@800022
testbench353.i_x353.i_sensorpix.i_lens_flat.lens_corr_out[4:0]
@28
(0)testbench353.i_x353.i_sensorpix.i_lens_flat.lens_corr_out[4:0]
(1)testbench353.i_x353.i_sensorpix.i_lens_flat.lens_corr_out[4:0]
(2)testbench353.i_x353.i_sensorpix.i_lens_flat.lens_corr_out[4:0]
(3)testbench353.i_x353.i_sensorpix.i_lens_flat.lens_corr_out[4:0]
......@@ -273,6 +336,7 @@ testbench353.i_x353.i_sensorpix.i_lens_flat.lens_corr_out[4:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.linerun
@22
testbench353.i_x353.i_sensorpix.i_lens_flat.mult_first_res[35:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.pix_zero[17:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.mult_first_scaled[17:0]
testbench353.i_x353.i_sensorpix.i_lens_flat.mult_second_res[35:0]
@28
......@@ -298,7 +362,7 @@ testbench353.i_x353.i_sensorpix.i_lens_flat.we_post_scale
testbench353.i_x353.i_sensorpix.i_lens_flat.we_scales
testbench353.i_x353.i_sensorpix.i_lens_flat.wen
testbench353.i_x353.i_sensorpix.i_lens_flat.wen_d[1:0]
@1000200
@1401200
-lens_flat
@c00200
-sensor12b
......@@ -317,9 +381,9 @@ testbench353.i_sensor12bits.state[3:0]
testbench353.i_sensor12bits.stated[3:0]
@1401200
-sensor12b
@800200
@c00200
-debug_sensorpads
@1000200
@1401200
-debug_sensorpads
@200
-
......@@ -591,10 +655,10 @@ testbench353.i_x353.i_sensorpads.pxdi[11:0]
testbench353.i_x353.i_sensorpads.xpgmen_d[1:0]
@1401200
-sensorpads
@200
-
@800200
@c00200
-sensorpix
@28
testbench353.i_x353.i_sensorpix.hact
@c00022
testbench353.i_x353.i_sensorpix.pxd[15:0]
@28
......@@ -617,6 +681,47 @@ testbench353.i_x353.i_sensorpix.pxd[15:0]
@1401200
-group_end
@28
testbench353.i_x353.i_sensorpix.bayer[1:0]
testbench353.i_x353.i_sensorpix.en
testbench353.i_x353.i_sensorpix.bayer_nset
testbench353.i_x353.i_sensorpix.bayer0_latched
@c00022
testbench353.i_x353.i_sensorpix.color[1:0]
@28
(0)testbench353.i_x353.i_sensorpix.color[1:0]
(1)testbench353.i_x353.i_sensorpix.color[1:0]
@1401200
-group_end
@200
-
@28
testbench353.i_x353.i_sensorpix.hact_outp
testbench353.i_x353.i_sensorpix.hact_out
@22
testbench353.i_x353.i_sensorpix.pd_lenscorr_out[15:0]
testbench353.i_x353.i_sensorpix.i_cstableh.ADDRA[10:0]
testbench353.i_x353.i_sensorpix.table_base_w[9:0]
testbench353.i_x353.i_sensorpix.table_diff_w[7:0]
testbench353.i_x353.i_sensorpix.table_base[9:0]
@200
-
@22
testbench353.i_x353.i_sensorpix.pd_lenscorr_out_d[7:0]
testbench353.i_x353.i_sensorpix.table_diff[10:0]
testbench353.i_x353.i_sensorpix.table_mult[35:0]
testbench353.i_x353.i_sensorpix.table_mult_r[17:7]
testbench353.i_x353.i_sensorpix.table_base_r[9:0]
testbench353.i_x353.i_sensorpix.interp_data[9:0]
testbench353.i_x353.i_sensorpix.cdata[7:0]
@200
-
@22
testbench353.i_x353.i_sensorpix.do[15:0]
@28
testbench353.i_x353.i_sensorpix.dwe
@200
-
@28
testbench353.i_x353.i_sensorpix.twce_d
testbench353.i_x353.i_sensorpix.i_cstableh.DIPB
@22
......@@ -769,8 +874,159 @@ testbench353.i_x353.i_sensorpix.we_lensff
testbench353.i_x353.i_sensorpix.wfpn
testbench353.i_x353.i_sensorpix.wpage
testbench353.i_x353.i_sensorpix.wthrsh
@1000200
@1401200
-sensorpix
@200
-
@800200
-histogram
@28
testbench353.i_x353.i_histogram.bayer_phase[1:0]
@c00023
testbench353.i_x353.i_histogram.hist_seq[5:0]
@29
(0)testbench353.i_x353.i_histogram.hist_seq[5:0]
(1)testbench353.i_x353.i_histogram.hist_seq[5:0]
(2)testbench353.i_x353.i_histogram.hist_seq[5:0]
(3)testbench353.i_x353.i_histogram.hist_seq[5:0]
(4)testbench353.i_x353.i_histogram.hist_seq[5:0]
(5)testbench353.i_x353.i_histogram.hist_seq[5:0]
@1401201
-group_end
@c00022
testbench353.i_x353.i_histogram.bayer[1:0]
@28
(0)testbench353.i_x353.i_histogram.bayer[1:0]
(1)testbench353.i_x353.i_histogram.bayer[1:0]
@1401200
-group_end
@22
testbench353.histogram_count[9:0]
testbench353.histogram_total
testbench353.i_x353.i_histogram.di_a[15:0]
@28
testbench353.i_x353.i_histogram.di_vld_a
testbench353.i_x353.i_histogram.line_start
testbench353.i_x353.i_histogram.line_started
testbench353.i_x353.i_histogram.line_ended
testbench353.i_x353.i_histogram.line_run
testbench353.i_x353.i_histogram.frame_started
testbench353.i_x353.i_histogram.frame_ended
testbench353.i_x353.i_histogram.last_line
testbench353.i_x353.i_histogram.line_start_posl_zero
testbench353.i_x353.i_histogram.window_on
@22
testbench353.i_x353.i_histogram.pos_left[13:1]
testbench353.i_x353.i_histogram.pos_top[13:1]
testbench353.i_x353.i_histogram.size_width[13:1]
testbench353.i_x353.i_histogram.size_height[13:1]
@28
testbench353.i_x353.i_histogram.hist_ena
testbench353.i_x353.i_histogram.hist_wea
@22
testbench353.i_x353.i_histogram.hist_waddr[9:0]
testbench353.i_x353.i_histogram.hist_waddr_hold1[9:0]
testbench353.i_x353.i_histogram.hist_waddr_hold2[9:0]
testbench353.i_x353.i_histogram.hist_dia[17:0]
testbench353.i_x353.i_histogram.hist_doa[17:0]
@28
testbench353.i_x353.i_histogram.same_waddr
@200
-
@22
testbench353.i_x353.i_histogram.di[15:0]
@28
testbench353.i_x353.i_histogram.bayer[1:0]
testbench353.i_x353.i_histogram.bayer_en
testbench353.i_x353.i_histogram.bayer_phase[1:0]
testbench353.i_x353.i_histogram.bayer_phase_latched[1:0]
@22
testbench353.i_x353.i_histogram.di2x[15:0]
testbench353.i_x353.i_histogram.di[15:0]
testbench353.i_x353.i_histogram.di_a[15:0]
@28
testbench353.i_x353.i_histogram.di_vld
testbench353.i_x353.i_histogram.di_vld_a
@22
testbench353.i_x353.i_histogram.dvld2x[3:0]
@28
testbench353.i_x353.i_histogram.end_hist_init
testbench353.i_x353.i_histogram.frame_ended
testbench353.i_x353.i_histogram.frame_run
testbench353.i_x353.i_histogram.frame_run_s[2:0]
testbench353.i_x353.i_histogram.frame_start
testbench353.i_x353.i_histogram.frame_started
testbench353.i_x353.i_histogram.hist_bank
@22
testbench353.i_x353.i_histogram.hist_dia[17:0]
testbench353.i_x353.i_histogram.hist_do0[17:0]
testbench353.i_x353.i_histogram.hist_do[31:0]
testbench353.i_x353.i_histogram.hist_doa[17:0]
@28
testbench353.i_x353.i_histogram.hist_ena
@22
testbench353.i_x353.i_histogram.hist_init_cntr[9:0]
testbench353.i_x353.i_histogram.hist_post[17:0]
testbench353.i_x353.i_histogram.hist_pre[17:0]
testbench353.i_x353.i_histogram.hist_raddr[9:0]
testbench353.i_x353.i_histogram.hist_seq[5:0]
testbench353.i_x353.i_histogram.hist_waddr[9:0]
testbench353.i_x353.i_histogram.hist_waddr_hold1[9:0]
testbench353.i_x353.i_histogram.hist_waddr_hold2[9:0]
@28
testbench353.i_x353.i_histogram.hist_wea
testbench353.i_x353.i_histogram.init_hist
testbench353.i_x353.i_histogram.init_hist_d
testbench353.i_x353.i_histogram.last_line
@22
testbench353.i_x353.i_histogram.line_cntr[13:1]
@28
testbench353.i_x353.i_histogram.line_end
testbench353.i_x353.i_histogram.line_ended
testbench353.i_x353.i_histogram.line_run
testbench353.i_x353.i_histogram.line_run_a
testbench353.i_x353.i_histogram.line_run_s[2:0]
testbench353.i_x353.i_histogram.line_start
testbench353.i_x353.i_histogram.line_start_posl_nzero
testbench353.i_x353.i_histogram.line_start_posl_zero
testbench353.i_x353.i_histogram.line_started
@22
testbench353.i_x353.i_histogram.minus_pos_left[13:1]
@28
testbench353.i_x353.i_histogram.odd_line
testbench353.i_x353.i_histogram.pclk
testbench353.i_x353.i_histogram.pclk2x
@22
testbench353.i_x353.i_histogram.pix_cntr[13:1]
testbench353.i_x353.i_histogram.pos_left[13:1]
@28
testbench353.i_x353.i_histogram.pos_left_is_zero
@22
testbench353.i_x353.i_histogram.pos_top[13:1]
@28
testbench353.i_x353.i_histogram.pre_di_vld
testbench353.i_x353.i_histogram.pre_same_addr
testbench353.i_x353.i_histogram.rd_hist
testbench353.i_x353.i_histogram.rnext
testbench353.i_x353.i_histogram.same_waddr
testbench353.i_x353.i_histogram.sclk
@22
testbench353.i_x353.i_histogram.size_height[13:1]
testbench353.i_x353.i_histogram.size_width[13:1]
@28
testbench353.i_x353.i_histogram.wa[2:0]
@22
testbench353.i_x353.i_histogram.wd[15:0]
testbench353.i_x353.i_histogram.wdd[15:0]
@28
testbench353.i_x353.i_histogram.we_addr
testbench353.i_x353.i_histogram.we_addr_d
testbench353.i_x353.i_histogram.we_pos[1:0]
testbench353.i_x353.i_histogram.we_size[1:0]
testbench353.i_x353.i_histogram.wen
testbench353.i_x353.i_histogram.window_on
@1000200
-histogram
@c00200
-sdram
@22
......
x353_1.tf
View file @ 49896216
......@@ -35,7 +35,8 @@ module testbench353();
parameter SYNC_BIT_LENGTH=8-1; /// 7 pixel clock pulses
parameter FPGA_XTRA_CYCLES= 1500; // 1072+;
parameter HISTOGRAM_LEFT= 0; //2; // left
parameter HISTOGRAM_TOP = 2; // top
// parameter HISTOGRAM_TOP = 2; // top
parameter HISTOGRAM_TOP = 8; // top - otherwise no time to erase
parameter HISTOGRAM_WIDTH= 6; // width
parameter HISTOGRAM_HEIGHT=6; // height
parameter CLK0_PER = 6.25; //160MHz
......@@ -1122,7 +1123,8 @@ $display ("saturation=2");
// cpu_wr('h62,'h0c002400); // JP46 - mode 2
cpu_wr('h62,'h0c000006); // mode - single
cpu_wr('h62, 'h4e000000 | 'h4 );// bayer=0
cpu_wr('h64, 'h4e000000 | 'h5 );// bayer=1
//AF2015 cpu_wr('h64, 'h4e000000 | 'h5 );// bayer=1
cpu_wr('h65, 'h4e000000 | 'h5 );// bayer=1 AF2015 - make it later to compare with 393
/*
AX(0x000000): writing 0x000000 to 0x31
......@@ -1141,11 +1143,13 @@ $display ("saturation=2");
// Lens flat field correction
cpu_wr('h62,'h31000000); // [AX] => 0x0
cpu_wr('h62,'h31080000); // [AY] => 0
// cpu_wr('h62,'h31000000); // [AX] => 0x0
// cpu_wr('h62,'h31080000); // [AY] => 0
cpu_wr('h62,'h31108000); // [C] => 0x8000
cpu_wr('h62,'h31200000); // [BX] => 0
cpu_wr('h62,'h31400000); // [BY] => 0
cpu_wr('h62,'h31380000); // [BX] => 0x180000; // 0
cpu_wr('h62,'h31580000); // [BY] => 0x180000; // 0
// cpu_wr('h62,'h31200000); // [BX] => 0x180000; // 0
// cpu_wr('h62,'h31400000); // [BY] => 0x180000; // 0
cpu_wr('h62,'h31608000); // [scales0] => 32768
cpu_wr('h62,'h31628000); // [scales1] => 32768
......@@ -1155,11 +1159,14 @@ $display ("saturation=2");
cpu_wr('h62,'h31690000); // [fatzero_out] => 0
cpu_wr('h62,'h316a0001); // [post_scale] => 3 - X
cpu_wr('h63,'h31020000); // [AX] => 0x20000
cpu_wr('h63,'h310a0000); // [AY] => 0x20000
// cpu_wr('h63,'h31020000); // [AX] => 0x20000
// cpu_wr('h63,'h310a0000); // [AY] => 0x20000
cpu_wr('h62,'h31020000); // [AX] => 0x20000
cpu_wr('h62,'h310a0000); // [AY] => 0x20000
cpu_wr('h64,'h31200000); // [BX] => 0x180000
cpu_wr('h64,'h31400000); // [BY] => 0x180000
// TODO: move to 'h62 (together with 393)
// cpu_wr('h64,'h31200000); // [BX] => 0x180000
// cpu_wr('h64,'h31400000); // [BY] => 0x180000
`ifdef CONTINUOUS_COMPRESSION
TEST_TITLE = "START_CONTINUOUS_COMPRESSION";
......
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