- 17 Jul, 2026 5 commits
-
-
Andrey Filippov authoredleanMeasure batched branch (JNA + pose_mb_uniform + resident build, no armed pose_corr capture, no debug-fetch holders): gpuTaskBuild runs b3CycleSetup (gc/cv + the 4 LPF/LoG consts + peak de-bias + sensor mask + per-scene descriptor - the same bytes the granular path re-uploaded every cycle) then ONE execPoseMeasureCycle call replaces the whole granular GPU sequence (task_update, geometry/convert x2, consolidate, inter-corr, normalize, peak). Per-cycle D2H stays corr indices + peaks (fetchCorr2DPeaks = D2H-only twin of execCorr2DPeaks). Granular path unchanged and remains the fallback + debug/capture path; new profile stage 'batched measure chain (B3)'. ONE-SHOT ORACLE (pose_lma_debug>=1, first eligible cycle): the batched chain runs FIRST (idempotent - every stage is a deterministic function of resident state + pose), captures indices+peaks, the granular chain re-runs the identical sequence, and the two are compared BIT-EXACT - EXPECT indices IDENTICAL + 0 peak mismatches. Batched production cycles start only after the oracle reports (or pose_lma_debug<1). ImageDtt.setInterCorrLpfs extracted from interCorrTDResident (shared). Requires tile_processor_gpu ee0d275. mvn PASS; run_cases.sh ALL PASS. Co-Authored-By:Claude Fable 5 <noreply@anthropic.com>
-
Andrey Filippov authored
setBayerImages (both float[][] and double[][][] variants) now funnels through uploadBayer: each sensor image is written into the pinned native staging slot (one JNI region copy) and committed with tp_proc_set_image_staged - the async pinned->device DMA of sensor k overlaps the convert/write of sensor k+1 (per-sensor copy/compute pipelining, design B4). Double-buffered slots flip per upload (RT inter-scene overlap provision). Falls back one-time to the legacy pageable path on missing natives or any staged failure (legacy fences first, so a partial staged upload is always fully rewritten). ONE-SHOT ORACLE (first staged upload): reads every uploaded sensor back and counts bit-mismatches vs the Java array - EXPECT 0 EXACTLY, plus the enqueue-side upload ms. Requires tile_processor_gpu 11ccdc2 (libtileproc.so rebuild); older libs downgrade gracefully. mvn PASS; native run_cases.sh ALL PASS incl. new bayer_staged case. Co-Authored-By: -
Andrey Filippov authored
Replace the per-scene one-point getMotionBlur call (~5-6 ms/scene, B0-attributed to IntersceneLma prepareLMA scaffolding + two ~THREADS_MAX thread-array spawns) with OpticalFlow.getMotionBlurPoint: the identical double chain (setupERS x2, getInterRotDeriveMatrices, getDPxSceneDParameters, same-order rate dot product) run serially at the representative point - bit-for-bit the same result at ~us cost. uniformMotionBlur broadcasts it unchanged; degenerate return still falls back to legacy getMotionBlur (per-tile), so non-uniform behavior is untouched. One-shot oracle at pose_lma_debug>=1 (replaces the closed B0 MB warm-repeat): times the fast path, evaluates legacy getMotionBlur at the SAME representative point, prints max|d| (expected 0 exactly). IntersceneLma.INFINITY_DISPARITY becomes the single source for the 0.01 infinity threshold. Gate (design doc B2): oracle max|d| = 0, real-scene poses within the B1 bounds, MB setup ~6 -> <0.5 ms/scene. Needs Andrey's run to close. Co-authored-by:
Claude <claude@elphel.com> Co-Authored-By:
-
Andrey Filippov authored
leanMeasure (uniform-MB lean path, JNA backend): the per-cycle CPU front end - transformToScenePxPyD (full 5120-tile grid), setInterTasksMotionBlur + sort, and the two task H2D uploads - is replaced by ONE gpuQuad.execPoseTaskUpdate() call: pose_task_update projects the per-sequence template on-device from the Java-tracked measure pose and rewrites both resident task slots in place; geometry + convert then run on ACTIVATED slots with no upload (ImageDtt.interCorrTDResident). Per cycle the only H2D left is the 12-float pose vector. Per scene: setupERS + camera-block upload (rung C2 registers, shared with prepare_resident) + skeleton slot re-upload (~120 KB, guards against other pipeline stages using the task slots between scenes). The per-scene uniform-MB 6-float descriptor replicates the exact setInterTasksMotionBlur double crank math; margin/projection failures become task=0 holes (missing peak -> conditioning abstains, D3 design). Fallbacks: JCuda backend, pose_mb_uniform off, NaN/non-uniform MB (degenerate uniformMotionBlur fallback) -> unchanged legacy CPU build. - GpuQuad/GpuQuadJna/TpJna: execPoseTaskUpdate + activateTaskSlot (base returns false; JNA marshals rung-C2 nullable groups). - IntersceneLmaFloat.buildTasks: serial float task-build oracle (the Java float clone of the kernel, worldFromPixel -> pixelFromWorld + descriptor/margin/hole packing). - One-shot oracle at pose_lma_debug>=1: GPU stream vs the legacy Java DOUBLE build (txy-matched field compare, D3 gate <=1e-5 px print) and vs the float-serial clone; once-per-program path-active note. - pose_corr export stays the explicit diagnostic exception: armed runs read the GPU-built pre-offset streams back and capture task words RAW (new iterTasksPre or511 overload - a |511-ed hole would diverge in a tol-0 replay). mvn -DskipTests clean package: BUILD SUCCESS. Real-scene gate (D3, ratified): poses < 0.003 px drift, aggregate RMS unchanged at print precision, same QC count, 497/497 - Andrey's run. CUDA side: tile_processor_gpu lwir16_2 @ ef36688 (kernel + JNA API + two-tier tests, all regressions PASS incl. pose_corr @tol 0). Design: internal handoffs/2026-07-16_3b_measure_chain_residency_design.md. Co-Authored-By: -
Andrey Filippov authored
CLAUDE: 3-B rung B0 - one-shot attribution micro-measurements (grid transform, task build, MB setup, conditioning split) Design: attic/imagej-elphel-internal/handoffs/2026-07-16_3b_measure_chain_residency_design.md (all 4 rulings approved 07/16). B0 = attribute before B1 deletes the stages: - grid transform (pose_lma_debug>=1, once/program): warm re-runs of transformToScenePxPyD full-grid vs selection-only x multi vs single thread - splits thread-array churn / full-grid-for-150-tiles waste / irreducible per-tile ERS work. - task build: warm multi vs single-thread setInterTasksMotionBlur rebuild. - MB setup: warm repeat of uniformMotionBlur (sizes the B2 descriptor win). - conditioning (once/program, both direct and preloaded paths): prepare / cpu-condition / setBayerImages H2D / gpu-condition split - sizes B4's pinned+async overlap honestly (only the H2D share can hide). One-shot: extra runs land in 'leanMeasure other' for a single call, steady state unchanged. No behavior change; mvn -DskipTests package PASS. Co-Authored-By:
-
- 16 Jul, 2026 17 commits
-
-
Andrey Filippov authored
C3b gate (log 191867): azimuth RMS 0.0454 (C2 bar 0.0349, +30%), roll 0.0415 (+54%), NOT-settled 228 (C2: 51). Better than the cycle-1 freeze (0.0518/0.0542/267) but still fails the pre-declared C2-level gate. CONCLUSION: per-cycle conditioning re-derivation carries convergence dynamics through ALL cycles (228 scenes not settled by cycle 4 - 'cycle 2 ~= converged' does not hold for half the sequence); not a noise source to freeze away for ~0.6 ms/scene. pose_freeze_cycle default 0 = per-cycle (restores C2 quality); parameter + bit-exact light-path mechanism stay for DP-era experiments (previous-scene conditioning candidate). Co-Authored-By: -
Andrey Filippov authored
Andrey 07/16: better inter-scene accuracy may pay off - keep the opportunity. New curt.pose_freeze_cycle ('Pose freeze conditioning at cycle'): 0 = never freeze = per-cycle re-derivation (highest accuracy, pre-C3 behavior); 2 = default (freeze at the post-first-correction measurement); 1 = falsified. Runtime-selectable - A/B/revert experiments need no rebuild. Wired via IntersceneLma.setPoseFreezeCycles from leanFitScene. Co-Authored-By: -
Andrey Filippov authored
C3 gate result: freezing at cycle 1 regressed azimuth RMS 0.0349->0.0518 px (+48%), roll 0.0270->0.0542 (+100%), NOT-settled 51->267. Mechanism: cycle-1 peaks are measured at the blurriest, pre-correction pose - freezing them locks in the WORST conditioning; per-cycle re-derivation carried convergence signal, not just noise. Andrey's observation: the first outer cycle absorbs nearly the whole prediction error (single near-GN inner step, lambda=1e-3), so the cycle-2 measurement is at an essentially converged pose. C3b: cycles 1-2 run FULL prepares; the SECOND result freezes; cycles 3+ run light. Context (Andrey): exit_change_atr QC threshold was test-era; the application bar is 0.1 px - C2-level quality remains the gate target, revert to per-cycle stays the fallback. Co-Authored-By: -
Andrey Filippov authored
Design 3-A4i rung C3 (native tile_processor_gpu HEAD): the cycle-1 resident prepare result carries the FROZEN conditioning; later cycles of the same scene run a light prepare (fresh measured offsets + fx/J at the moving pose; weights/eigen/selection/pull/reg/pure_weight untouched). Rulings (Andrey 07/17): eigen freezes WITH the weights (same trust-in-tile nature); a frozen-selected tile with no fresh valid peak abstains (y=fx, zero residual); reg weights + pure_weight freeze from cycle 1. Semantic gain: every cycle optimizes the SAME objective - conditioning no longer wobbles with per-cycle measurement noise. Provider/GpuQuad/GpuQuadJna gain a light flag; the per-scene instance naturally scopes the freeze. Gates: mvn package+test PASS; Stage0 36/36; native suite incl. new LIGHT bit-exact test PASS. Co-Authored-By: -
Andrey Filippov authored
Design 3-A4i rung C2 (native tile_processor_gpu HEAD): - IntersceneLma: per-SEQUENCE cache (reference Camera + flattened centers, keyed on the reference ErsCorrection; the virtual center is static by construction - zero pose, zero rates) with an explicit resetPoseSequenceCache() re-armed at sequence start; per-SCENE cache (scene Camera in the per-scene instance: ERS rates never change across cycles - setupERS depends only on rates/line_time, verified, and the 3 adjusted angles travel in pose_vectors). setupERS + Camera.capture now run once per level instead of 4x/scene; the provider gets null for resident groups. Provider/GpuQuad/GpuQuadJna signatures gain explicit numTiles. - Dead work deleted: the threaded setEigenTransform build at the prepareLMA head runs only on the legacy/capture/MB fall-through (the GPU assemble builds the transform from resident peaks on the production path). - CuasPoseRT: resetPoseSequenceCache() at testPoseSequence start. Expected: prep setup 5.7 -> ~1.5 ms cycle-1 / ~0.3-0.7 cycles 2-4, prepare ~22.9 -> ~3-5 ms/scene; per-cycle PCIe ~120KB -> ~60B + result. Gates: mvn package+test PASS; Stage0 36/36; full native suite PASS. Co-Authored-By: -
Andrey Filippov authored
IntersceneLma is constructed per scene; the pre-existing one-shot flags are static but poseLmaPrepareOracleReported was instance-scoped, so the 13:03:32 run executed a legacy capture cycle + PREPARE compare on EVERY scene (497 bit-exact passes - strong accidental validation, but per-scene legacy cost: prepare 37.3 vs 22.9 ms/scene, capacity 6.67 vs 7.31 scenes/s). Now static. Co-Authored-By: -
Andrey Filippov authored
prepareLMA received imp.debug_level only, so prepare_capture never armed in the debug1 config (pose_lma_debug=1, imp.debug_level<=0) and the C1 gate run went resident from cycle 0 without printing the bit-exact compare. Now the same boost the step oracle gets. Run was otherwise clean: 497/497, both markers, zero anomalies, drift <=0.0023 px, aggregate RMS/QC identical. Co-Authored-By: -
Andrey Filippov authored
Design 3-A4i rung C1 (native tile_processor_gpu 7db7cf6): - IntersceneLma: PoseLmaPrepareProvider + residentPrepare() (mirrors the getFxDerivs head: ERS pokes + setupERS + camera/centers capture; per-cycle H2D = camera state + pose vector + centers + 6 policy floats). Production lean prepare skips setSamplesWeights / both fx passes / WJtJ+reg+normalize / y-build entirely; weights/y stay GPU-resident; initial RMS seeds from the first resident step's packed[19,20] (kills the runLma first-step re-linearization = C0's 'LMA CPU remainder'). Invalid/unavailable falls back loudly to the legacy Java prepare. - One-shot oracle (pose_lma_debug>=1, first prepare): the capture cycle runs FULLY legacy, then the resident prepare captures its buffers and the new IntersceneLmaFloat.prepareResidentOracle (serial float clone) must match BIT-EXACTLY ('resident CUDA vs Java-float PREPARE: ... mismatches=0'). - lmaStep: prepared-resident steps pass NULL weights/y/eigen (no per-step H2D); first-block linearization skipped when prepared. - CuasPoseRT: provider wiring (slot 0xff + CORR_NTILE_SHIFT = host policy), new marker 'resident CUDA prepareLMA active'; cycle_rms_meas moved after runLma reading getInitialRms() (same value on both paths). - Stage0 kernel count 33 -> 36 (3 new prepare kernels). Gates: mvn package + test PASS; Stage0 36/36; full native suite in tile_processor_gpu 7db7cf6 (direct prepare BIT-EXACT, sanitizer 0 errors). Co-Authored-By: -
Andrey Filippov authored
Design 3-A4i rung C0: IntersceneLma gains a null-safe ProfileSink (pattern- consistent with the providers; zero overhead when unset). The production prepareLMA overload emits setup+samples-weights / fx-pass-1 / WJtJ+reg+ normalize / fx-pass-2 samples (LMA path only - MB-vector calls excluded; y+RMS tail = derived remainder). Two cross-cutting probes: the poseFxProvider JNA roundtrip wall (all lean fx sites, incl. runLma's first-step re-linearization) and the setupERS pair. CuasPoseRT routes the sink into RtPoseProfile (6 new stages, printSummary extended). Expected from one run of the same config: split prepare's ~16 ms/call into JNA-roundtrip vs Java-CPU, sizing C1 honestly. Co-Authored-By: -
Andrey Filippov authored
Design 3-A4i rung B (native tile_processor_gpu 5f47326): for the lean three-angle shape the GPU decision drives the Java state machine: - resident-valid production path: accept/stop from packed[23..24], RMS from packed[19..22] (floats widened exactly), parameters_vector from the resident candidate; NO Java candidate projection, NO re-decision, NO rejection-restore projection (GPU retained current state, device-side set-index commit). Decision equivalence was proven over 1,988 steps with zero mismatches (session-43 gate). - invalid resident result (singular solve / non-finite) = REJECTED-STEP semantics: caller raises lambda and retries/exits; no Java-double fallback for the lean shape (fallbacks only where free). General shapes and the no-resident paths are unchanged. - one-shot oracle preserved: at pose_lma_debug>=1 the first step falls through the legacy path once and prints the existing preparation/candidate/ RMS-decision comparisons; production steps never compute the double side. - marker updated: 'resident CUDA float LMA decision AUTHORITATIVE'. Gates: mvn package PASS; mvn test PASS (no test sources); Stage0 33/33; full native suite in tile_processor_gpu 5f47326. Co-Authored-By: -
Andrey Filippov authored
Design 3-A4i rung A (2026-07-16 handoff): the 00:25:48 gate profile's 'leanMeasure other' (26.1 ms/call, 43% of post) was unprofiled debug-save data motion (pose_corr_save/pose_img_save). Changes: - leanFitScene passes corr_pd_out/img_out only on the LAST outer cycle in fixed-cycle mode (legacy convergence mode keeps every-cycle so an early exit still fills the holders). - New DEBUG_FETCH profile stage wraps perSensorImagesFromTD, the no-MB debug re-convert, and fetchNormalizedPD, so debug data motion can never hide in 'leanMeasure other' again (it joins measureAccounted). Armed pose_corr capture unaffected (fetch keyed on isArmed() unchanged). Expected gate: poses/records byte-exact, hyperstacks identical, capacity ~3.9 -> ~5.5 scenes/s in the debug config. Co-Authored-By: -
Andrey Filippov authored
Co-authored-by:Codex <codex@elphel.com>
-
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
Co-authored-by:
-
- 15 Jul, 2026 10 commits
-
-
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
Co-authored-by: -
Andrey Filippov authored
CLAUDE: leanMeasure - drop the just-added JCuda Java-oracle fallback branch (Andrey's ruling: fallbacks only where free) The dual-path else-branch added earlier today (f8df8dce) would silently run a second implementation on the JCuda backend - the exact divergence the JNA-migration-keep-it-clean policy avoids. Now: no GPU peak kernel -> loud 'requires the JNA backend' message, scene returns null. NOT a JCuda purge: all pre-existing JCuda code stays (base execCorr2DPeaks null-return, the consolidation CPU bridge, legacy paths); the double kernel and the Java oracle remain as VALIDATION tiers in tests/export capture. mvn package OK. Co-Authored-By:
-
Andrey Filippov authored
leanMeasure now measures peaks ON the GPU (corr2D_peak_eig_f via GpuQuad.execCorr2DPeaks, float = the ratified production precision; the double kernel stays the validation tier): per LMA iteration only the small task streams go up and [n_corr][8] peak floats come down - the PD download happens ONLY for debug rendering (-POSE-RT-CORR2D), the pose_corr export capture, or the JCuda fallback (the original Java-oracle loop, kept intact). - GpuQuad: execCorr2DPeaks/setPeakDebias base = null/false (JCuda -> Java fallback); PEAK_ROW_FLOATS contract constant. - GpuQuadJna + TpJna: tp_proc_exec_corr2d_peak(use_float)/get_peaks/ set_peak_debias bindings. - TDCorrTile: convertTDtoPDInPlace split - fetchNormalizedPD is now the optional D2H half. - CuasPoseRT.leanMeasure: normalize in place -> float peak kernel -> map rows by packed corr index (valid==0 = kernel reject == oracle null); de-bias uploaded as the float array when pose_debias > 0; once-per-program 'GPU peak kernel active' console line. - PoseCorrExport.iterGpuPeaks: the production float rows land in the case (expected_gpu_peaks_it<k>, corr_indices order) = the TOL-0 peak tier; test_pose_corr_jna compares its float replay bit-exactly when present (tile_processor_gpu companion commit). mvn package OK; CuasTD headless self-test ALL PASSED; run_cases.sh ALL PASS (pre-hookup case: gpu_peaks buffer absent -> skipped gracefully). Co-Authored-By:
-
- 14 Jul, 2026 3 commits
-
-
Andrey Filippov authored
New KEY_DIRS entry (index 12, same pattern as cuasSynth/cuasNoise): SET casesFile <path> in a scene-sequence .list names the GPU-test case manifest (tile_processor_gpu run_cases.sh reads the same SET). A FILE key: exempt from the auto-mkdirs branch; resolved vs rootDirectory and recorded in this.casesFile (informational for now - reserved for in-program use). Parses cleanly instead of the '*********** Unknown SET' console warning. Companion to tile_processor_gpu edc6c4a. mvn compile OK. Co-Authored-By: -
Andrey Filippov authored
Companion to tile_processor_gpu 72e2caf (cases.list + run_cases.sh). Co-Authored-By: -
Andrey Filippov authored
CLAUDE: 3-C rung 2 - 15-arg peak contract in the lean oracle, FZ-norm in place, pose_corr checkpoint-2 export Andrey's ruling 07/13/2026 (frozen GPU contract = 15-arg getMaxXYCmEig superset; recentering runtime knob; de-bias optional, default off): - CuasRtParameters: NEW 'CUAS RT' knobs pose_recenter (recentering passes, 0 = validated single-pass baseline) + pose_debias (window-autocorr envelope de-bias fraction, 0 = off); corr-xml _curt_pose_recenter/_curt_pose_debias. - CuasPoseRT.leanMeasure: peak measurement switched to the 15-arg getMaxXYCmEig (eig_fast2x2=true = the contract's closed-form eigen); windowAutocorrDebias() = the single source of the de-bias array (Java oracle, export case, JNA host). - TDCorrTile.convertTDtoPDInPlace: corr2D_normalize runs on the inter corr TD buffer where execCorr2D_inter_TD left it (NULL weights == the repack path's uniform 1.0 -> bit-identical PD); the TD D2H->repack->H2D round trip is gone from the lean chain on both backends. - PoseCorrExport: checkpoint 2 in the same case - expected_corr_pd (GPU-produced normalized PD, the tol-0 target for the in-place replay), expected_peaks (double Java oracle incl. weak-peak rejects as NaN rows), contract params + optional debias array in the manifest; compareResults round-trips corr_pd/peaks when the C++ test writes them. mvn -DskipTests clean package OK; C++ side: tile_processor_gpu same-day commit (corr2D_peak_eig + tests, synthetic gate PASS, regressions PASS). Co-Authored-By:
-
- 13 Jul, 2026 5 commits
-
-
Andrey Filippov authored
Backward step from the first two known stored poses (prev_pose/prev_ts pre-initialized before the loop; the in-loop rate code is untouched): the seed scene's rate becomes exactly (stored[next]-stored[first])/dt instead of the zero-rate special case that left scene 0 with mb=(0,0) and the uncompensated v*tau bias. Using a difference of actual poses avoids any hand-derived rotation rate and its sign-convention risk. In RT production the continuous stream always has a real previous frame; this seam also covers stream (re)starts, where the nominal-rotation config can feed the same prev_pose/prev_ts initialization. Deliberate consequence: the next full-sequence run is NOT digit-identical to the 07/13 baseline in scene 0 (expected equal or better - the seed previously carried the v*tau bias). Co-Authored-By: -
Andrey Filippov authored
Measured on the first real case: an offline nvcc build cannot be bit-exact vs the NVRTC-JIT production module (FMA/codegen divergence) - the direct -G binary is the stepping companion; the NVRTC-module replay (jna/test_pose_corr_jna) PASSed bit-exact @tol 0, all 4 iterations. Co-Authored-By: -
Andrey Filippov authored
CLAUDE: 3-C rung 1 - pose_corr kernel-test export (checkpoint 1 = raw TD corr after correlate2D_inter) curt.kernel_test dropdown entry pose_corr: runs the normal lean pose sequence with a static armed capture (PoseCorrExport) that records, for the FIRST fitted scene, every LMA iteration's task streams exactly as the GPU received them (pre-offsets, task|511) and as the consolidation flattened them (post-offsets, disp_dist tail zero), the conditioned 16-sensor images exactly as uploaded (hook in conditionSceneToGpuInner - the data never lands in QuadCLT), geometry/correction-vector floats, aberration-kernel flatten, the four LPF/HPF constant payloads, the resident center TD (gpu_clt_ref cam 0) and the expected packed corr indices + raw TD correlation (captured right after execCorr2D_inter_TD, before FZ-normalize = the rung-2 boundary). The sequence stops early once the case is written; the TILE-CALIB save is additionally gated on !captureDone() so a truncated max-over-scenes calibration can never be written, and kernelTest refuses to run without an existing -POSE-RT-TILE-CALIB (the bootstrap FULL pass must never be capture- truncated). Requires pose_lean+pose_raw ON, pose_stored/pose_full OFF. C++ side: tile_processor_gpu tests_bin/test_pose_corr --data <case> --tol 0 (newly exercises calculate_tiles_offsets + correlate2D_inter; results/ are saved reordered into oracle index order for the Java round-trip compare). Co-Authored-By: -
Andrey Filippov authored
CLAUDE: 3-A3 fix - pure border-ring interior gate (morphological shrink annihilated the patchy selection) First attempt (8fb0eea4) shrank the finite-calibration mask morphologically - but the calibration is NaN wherever a tile was not STRENGTH-selected (whole sky + scattered terrain holes, ~21% finite density), so a 2-tile 8-dir shrink left ~2 tiles per scene: num=2 fits, dstored 6-10 px, LMA failures (07/13 run, killed). Andrey's ruling: pure border ring - the OOB-missing band is geometrically confined to the frame border (margin-dropped ring 1-2 tiles + partial-OOB soft band 12 px = 1.5 tiles), so excluding tiles within curt.pose_shrink (default now 4) tiles of the array border covers hard+soft+slack with zero collateral on interior strength holes. No TileNeibs, no morphology. Dialog label now "Pose tile selection border ring (tiles)"; key _curt_pose_shrink unchanged. Co-Authored-By:
-
Andrey Filippov authored
Tile selection (deriveSelection): new interior gate per Andrey's 07/13 ruling - usable = finite calibration (measured in EVERY scene) shrunk by curt.pose_shrink tiles (TileNeibs 8-dir, default 2; array-border ring cleared explicitly). Excludes the partial-OOB band (soft margin 12 px = 1.5 tiles) so every selected tile keeps all 16 sensors interior at every scene pose - enables the fixed per-sequence GPU tile list with the consolidation OOB pass bypassed by host policy. leanMeasure: sort task streams by (tileY, tileX) - setInterTasks* fill from worker threads, so tile order was nondeterministic run-to-run; the fixed selection + sort = the static task-stream contract for the pose_corr checkpoint (rung 1). New dialog knob (CUAS RT tab): "Pose tile selection shrink (tiles)" (curt.pose_shrink, corr-xml _curt_pose_shrink). Co-Authored-By:
-