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.settings troubleshooting lack of DONE during loading of the bitfile
axi debugging hardware
ddr3 modified include path
hardware_tests eye pattern tests at 400MHz
phy implemented read leveling, eye measurement for DDR3 on random data
python code to align bit delays on random data
simulation_modules debugging
unisims_patches patch to work with Icarus Verilog simulator
util_modules debugging hardware
wrap working with hardware
.editor_defines added modules, simulating
.gitignore added glbl.v
.project implemented read leveling, eye measurement for DDR3 on random data
.pydevproject organized new/debug files
OSERDESE1.diff Modifications for Icarus Verilog
README.md Added link to the blog post
ddr_refresh.v organized new/debug files
ddrc_control.v troubleshooting lack of DONE during loading of the bitfile
ddrc_status.v troubleshooting lack of DONE during loading of the bitfile
ddrc_test01.v debugging hardware
ddrc_test01.xcf added configuration for ISE, timing constraints for Vivado
ddrc_test01.xdc troubleshooting lack of DONE during loading of the bitfile
ddrc_test01_testbench.sav code to align bit delays on random data
ddrc_test01_testbench.tf code to align bit delays on random data
ddrc_test01_timing.xdc troubleshooting lack of DONE during loading of the bitfile
glbl.v Loading commit data...
README.md

eddr3

ddr3 subproject for Elphel 393 camera

This subproject is started to create a DDR3 memory controller for Elphel camera that does not depend on any non-documented features of Xilinx Zynq and can be simulated by Free Software tools (Icarus Verilog + GTKWave) without use of any encrypted modules. Everything in plain Verilog and constraints.

Detailed description of the project is available in the blog post: http://blog.elphel.com/2014/06/ddr3-memory-interface-on-xilinx-zynq-soc-free-software-compatible/