working with hardware (f2c019cd) · Commits · Elphel / eddr3

.project

+14 −14

Original line number	Diff line number	Diff line
		@@ -62,72 +62,72 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140610171311514.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140611121113006.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140610171311514.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140611121113006.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140610171311514.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140611121113006.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140610171311514.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140611121113006.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140610171311514.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140611121113006.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140610171311514.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140611121113006.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140610171153284.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140611121031786.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140610171311514.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140611121113006.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140610171311514.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140611121113006.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140610171311514.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140611121113006.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140610171311514.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140611121113006.log</location>
		</link>
		<link>
		<name>vivado_state/eddr3-opt-phys.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140610171311514.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140611121113006.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-place.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140610171311514.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140611121113006.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-route.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140610171311514.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140611121113006.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-synth.dcp</name>

phy/byte_lane.v

+6 −1

Original line number	Diff line number	Diff line
		@@ -19,7 +19,8 @@
		* along with this program. If not, see <http://www.gnu.org/licenses/> .
		*******************************************************************************/
		`timescale 1ns/1ps

		// minimizing total DQS in delay to match DQ (finedelay stage adds some?)
		`define NOFINEDELAY_DQS 1
		module byte_lane #(
		parameter IODELAY_GRP ="IODELAY_MEMORY",
		parameter IBUF_LOW_PWR ="TRUE",
		@@ -145,7 +146,11 @@ dm_single #(
		.ld_odelay(ld_odly_dm) // clk_div synchronous set odealy value from loaded
		);

		`ifdef NOFINEDELAY_DQS
		dqs_single_nofine #(
		`else
		dqs_single #(
		`endif
		.IODELAY_GRP(IODELAY_GRP),
		.IBUF_LOW_PWR(IBUF_LOW_PWR),
		.IOSTANDARD(IOSTANDARD_DQS),

phy/cmda_single.v

+2 −1

Original line number	Diff line number	Diff line
		@@ -22,6 +22,7 @@

		module cmda_single #(
		parameter IODELAY_GRP ="IODELAY_MEMORY",
		parameter integer ODELAY_VALUE = 0,
		parameter IOSTANDARD = "SSTL15",
		parameter SLEW = "SLOW",
		parameter real REFCLK_FREQUENCY = 300.0,
		@@ -58,7 +59,7 @@ oserdes_mem#(
		);
		odelay_fine_pipe # (
		.IODELAY_GRP(IODELAY_GRP),
		.DELAY_VALUE(0),
		.DELAY_VALUE(ODELAY_VALUE),
		.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
		.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
		) dqs_out_dly_i(

phy/dm_single.v

+3 −1

Original line number	Diff line number	Diff line
		@@ -23,6 +23,8 @@
		`define USE_IOBUF 1
		module dm_single #(
		parameter IODELAY_GRP ="IODELAY_MEMORY",
		// parameter integer IDELAY_VALUE = 0,
		parameter integer ODELAY_VALUE = 0,
		parameter IBUF_LOW_PWR ="TRUE", //SuppressThisWarning VEditor not used in OBUF_DCIEN
		parameter IOSTANDARD = "SSTL15_T_DCI",
		parameter SLEW = "SLOW",
		@@ -58,7 +60,7 @@ oserdes_mem#(
		);
		odelay_fine_pipe # (
		.IODELAY_GRP(IODELAY_GRP),
		.DELAY_VALUE(0),
		.DELAY_VALUE(ODELAY_VALUE),
		.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
		.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
		) dm_out_dly_i(

phy/dq_single.v

+4 −2

Original line number	Diff line number	Diff line
		@@ -22,6 +22,8 @@

		module dq_single #(
		parameter IODELAY_GRP ="IODELAY_MEMORY",
		parameter integer IDELAY_VALUE = 0,
		parameter integer ODELAY_VALUE = 0,
		parameter IBUF_LOW_PWR ="TRUE",
		parameter IOSTANDARD = "SSTL15_T_DCI",
		parameter SLEW = "SLOW",
		@@ -68,7 +70,7 @@ oserdes_mem#(
		);
		odelay_fine_pipe # (
		.IODELAY_GRP(IODELAY_GRP),
		.DELAY_VALUE(0),
		.DELAY_VALUE(ODELAY_VALUE),
		.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
		.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
		) dq_out_dly_i(
		@@ -96,7 +98,7 @@ IOBUF_DCIEN #(

		idelay_fine_pipe # (
		.IODELAY_GRP(IODELAY_GRP),
		.DELAY_VALUE(0),
		.DELAY_VALUE(IDELAY_VALUE),
		.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
		.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
		) dq_in_dly_i(

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