synchronizing with original repo (ea560b4a) · Commits · Elphel / eddr3

.project

+22 −0

Original line number	Diff line number	Diff line
		@@ -42,4 +42,26 @@
		<natures>
		<nature>com.elphel.vdt.veditor.HdlNature</nature>
		</natures>
		<linkedResources>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140429103628186.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140429103628186.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140429103628186.log</location>
		</link>
		<link>
		<name>vivado_state/eddr3-synth.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140429103628186.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

phy/wrap/iserdes_mem.v

+9 −5

Original line number	Diff line number	Diff line
		@@ -20,10 +20,14 @@
		*******************************************************************************/
		`timescale 1ns/1ps
		//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
		module iserdes_mem(
		module iserdes_mem #
		(
		parameter DYN_CLKDIV_INV_EN="FALSE"
		) (
		input iclk, // source-synchronous clock
		input oclk, // system clock, phase should allow iclk-to-oclk jitter with setup/hold margin
		input oclk_div, // oclk divided by 2, front aligned
		input inv_clk_div, // invert oclk_div (this clock is shared between iserdes and oserdes
		input rst, // reset
		input d_direct, // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
		input ddly, // serial input from idelay
		@@ -35,7 +39,7 @@ module iserdes_mem(
		ISERDESE2 #(
		.DATA_RATE ("DDR"),
		.DATA_WIDTH (4),
		.DYN_CLKDIV_INV_EN ("FALSE"),
		.DYN_CLKDIV_INV_EN (DYN_CLKDIV_INV_EN),
		.DYN_CLK_INV_EN ("FALSE"),
		.INIT_Q1 (1'b0),
		.INIT_Q2 (1'b0),
		@@ -74,7 +78,7 @@ module iserdes_mem(
		.CLKDIV (oclk_div),
		.DDLY (ddly),
		.D (d_direct), // direct connection to IOB bypassing idelay
		.DYNCLKDIVSEL (1'b0),
		.DYNCLKDIVSEL (inv_clk_div),
		.DYNCLKSEL (1'b0),
		.OCLK (oclk),
		.OCLKB (!oclk),
		@@ -87,7 +91,7 @@ module iserdes_mem(
		ISERDESE1 #(
		.DATA_RATE ("DDR"),
		.DATA_WIDTH (4),
		.DYN_CLKDIV_INV_EN ("FALSE"),
		.DYN_CLKDIV_INV_EN (DYN_CLKDIV_INV_EN),
		.DYN_CLK_INV_EN ("FALSE"),
		.INIT_Q1 (1'b0),
		.INIT_Q2 (1'b0),
		@@ -123,7 +127,7 @@ module iserdes_mem(
		.CLKDIV (oclk_div),
		.DDLY (ddly),
		.D (d_direct), // direct connection to IOB bypassing idelay
		.DYNCLKDIVSEL (1'b0),
		.DYNCLKDIVSEL (inv_clk_div),
		.DYNCLKSEL (1'b0),
		.OCLK (oclk),
		.OFB (),

phy/wrap/oserdes_mem.v

+26 −20

Original line number	Diff line number	Diff line
		@@ -20,17 +20,23 @@
		*******************************************************************************/
		`timescale 1ns/1ps
		//`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
		module oserdes_mem(
		module oserdes_mem #(
		parameter MODE_DDR="TRUE"
		) (
		input clk, // serial output clock
		input clk_div, // oclk divided by 2, front aligned
		input rst, // reset
		input [3:0] din, // parallel data in
		input [3:0] tin, // parallel tri-state in
		input [((MODE_DDR=="TRUE")?3:1):0] din, // parallel data in
		input [((MODE_DDR=="TRUE")?3:1):0] tin, // parallel tri-state in
		output dout_dly, // data out to be connected to odelay input
		output dout_iob, // data out to be connected directly to the output buffer
		output tout_dly, // tristate out to be connected to odelay input
		output tout_iob // tristate out to be connected directly to the tristate control of the output buffer
		);
		localparam integer MODE_DDR_BIN=(MODE_DDR=="TRUE")?1:0;
		localparam DATA_RATE= (MODE_DDR=="TRUE")?"DDR":"SDR";
		localparam integer DATA_WIDTH= (MODE_DDR=="TRUE")?4:2;
		localparam integer DDR3_DATA= (MODE_DDR=="TRUE")?1:0;
		/*
		Serialized data will go through odelay elements (with fine delay adjustment), tristate output will
		go directly. Luckily the active time for DQ/DQS may be extended (there is at least 1 full clock period
		@@ -40,15 +46,15 @@ module oserdes_mem(

		`ifndef IVERILOG // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )
		OSERDESE2 #(
		.DATA_RATE_OQ ("DDR"),
		.DATA_RATE_TQ ("DDR"),
		.DATA_WIDTH (4),
		.DATA_RATE_OQ (DATA_RATE),
		.DATA_RATE_TQ (DATA_RATE),
		.DATA_WIDTH (DATA_WIDTH),
		.INIT_OQ (1'b0),
		.INIT_TQ (1'b0),
		.SERDES_MODE ("MASTER"),
		.SRVAL_OQ (1'b0),
		.SRVAL_TQ (1'b0),
		.TRISTATE_WIDTH (4),
		.TRISTATE_WIDTH (DATA_WIDTH),
		.TBYTE_CTL ("FALSE"),
		.TBYTE_SRC ("FALSE")
		) oserdes_i (
		@@ -62,8 +68,8 @@ module oserdes_mem(
		.CLKDIV (clk_div),
		.D1 (din[0]),
		.D2 (din[1]),
		.D3 (din[2]),
		.D4 (din[3]),
		.D3 ((MODE_DDR=="TRUE")?din[2]:1'b0),
		.D4 ((MODE_DDR=="TRUE")?din[3]:1'b0),
		.D5 (),
		.D6 (),
		.D7 (),
		@@ -74,18 +80,18 @@ module oserdes_mem(
		.SHIFTIN2 (),
		.T1 (tin[0]),
		.T2 (tin[1]),
		.T3 (tin[2]),
		.T4 (tin[3]),
		.T3 ((MODE_DDR=="TRUE")?tin[2]:1'b0),
		.T4 ((MODE_DDR=="TRUE")?tin[3]:1'b0),
		.TCE (1'b1),
		.TBYTEOUT (),
		.TBYTEIN ()
		);
		`else // Simulating, use Virtex 6 module that does not have encrypted functionality
		OSERDESE1 #(
		.DATA_RATE_OQ ("DDR"),
		.DATA_RATE_TQ ("DDR"),
		.DATA_WIDTH (4),
		.DDR3_DATA (1), //For DDR3 DQ, DQS: 1, Address, ctrl, clock - 0
		.DATA_RATE_OQ (DATA_RATE),
		.DATA_RATE_TQ (DATA_RATE),
		.DATA_WIDTH (DATA_WIDTH),
		.DDR3_DATA (DDR3_DATA), //For DDR3 DQ, DQS: 1, Address, ctrl, clock - 0
		.INIT_OQ (1'b0),
		.INIT_TQ (1'b0),
		.INTERFACE_TYPE ("DEFAULT"), //"DEFAULT", "MEMORY_DDR3"
		@@ -93,7 +99,7 @@ module oserdes_mem(
		.SERDES_MODE ("MASTER"),
		.SRVAL_OQ (1'b0),
		.SRVAL_TQ (1'b0),
		.TRISTATE_WIDTH (4)
		.TRISTATE_WIDTH (DATA_WIDTH)
		) oserdes_i (
		.OFB (dout_dly),
		.OQ (dout_iob),
		@@ -105,8 +111,8 @@ module oserdes_mem(
		.CLKDIV (clk_div),
		.D1 (din[0]),
		.D2 (din[1]),
		.D3 (din[2]),
		.D4 (din[3]),
		.D3 ((MODE_DDR=="TRUE")?din[2]:1'b0),
		.D4 ((MODE_DDR=="TRUE")?din[3]:1'b0),
		.D5 (),
		.D6 (),
		.OCE (1'b1),
		@@ -115,8 +121,8 @@ module oserdes_mem(
		.SHIFTIN2 (),
		.T1 (tin[0]),
		.T2 (tin[1]),
		.T3 (tin[2]),
		.T4 (tin[3]),
		.T3 ((MODE_DDR=="TRUE")?tin[2]:1'b0),
		.T4 ((MODE_DDR=="TRUE")?tin[3]:1'b0),
		.TCE (1'b1),
		// not in OSERDES2E:
		.WC (1'b0),

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