just a snapshot

.gitignore

 unisims
 glbl.v
 vivado_*
+syntax_*

phy/byte_lane.v

@@ -110,8 +110,9 @@ generate
         .dci_disable(dci_disable_dq_r), // disable DCI termination during writes and idle
         .dly_data(dly_data_r),          // delay value (3 LSB - fine delay)
         .din(din_r[4*i+3:4*i]) ,        // parallel data to be sent out
+//        .din(din_r[4*i+3-:4]) ,        // parallel data to be sent out
         .tin(tin_dq_r),                 // tristate for data out (sent out earlier than data!) 
-        .dout(dout[4*i+3:4*i]),         // parallel data received from DDR3 memory
+        .dout(dout[4*i+3:4*i]),          // parallel data received from DDR3 memory
         .set_odelay(set_r),             // clk_div synchronous load odelay value from dly_data
         .ld_odelay(ld_odly[i]),         // clk_div synchronous set odealy value from loaded
         .set_idelay(set_r),             // clk_div synchronous load idelay value from dly_data

phy/cmd_addr.v

@@ -84,7 +84,7 @@ always @ (posedge clk_div or posedge rst) begin
         in_tri_r <= in_tri;
         dly_data_r<=dly_data;set_r<=set;
         ld_dly_cmd <=  {8 { dly_addr[4] & dly_addr[3] & ld_delay}} & decode_sel[7:0];
-        ld_dly_addr <= {(ADDRESS_NUMBER-1) {ld_delay}} & decode_addr;
+        ld_dly_addr <= {(ADDRESS_NUMBER) {ld_delay}} & decode_addr;
     end
 end     
 
@@ -100,7 +100,7 @@ generate
          .REFCLK_FREQUENCY(REFCLK_FREQUENCY),
          .HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
     ) cmda_addr_i (
-    .dq(ddr3_a),               // I/O pad (appears on the output 1/2 clk_div earlier, than DDR data)
+    .dq(ddr3_a[i]),               // I/O pad (appears on the output 1/2 clk_div earlier, than DDR data)
     .clk(clk),          // free-running system clock, same frequency as iclk (shared for R/W)
     .clk_div(clk_div),      // free-running half clk frequency, front aligned to clk (shared for R/W)
     .rst(rst),

phy/phy_top.v

@@ -97,7 +97,7 @@ module  phy_top #(
     .ADDRESS_NUMBER(ADDRESS_NUMBER)
   ) cmd_addr_i(
     .ddr3_a   (ddr3_a[ADDRESS_NUMBER-1:0]), // output address ports (14:0) for 4Gb device
-    .ddr3_ba  (ddr3_ba[2:0]),            // output bank address ports
+    .ddr3_ba  (ddr3_ba[2:0]),             // output bank address ports
     .ddr3_we  (ddr3_we),                 // output WE port
     .ddr3_ras (ddr3_ras),                // output RAS port
     .ddr3_cas (ddr3_cas),                // output CAS port

phy/test_dqs01.v

@@ -20,13 +20,13 @@
  *******************************************************************************/
 `timescale 1ns/1ps
 
-module  test_dqs01(
-    input       dqs_data,
-    inout       dqs,
-    inout       ndqs,
-    output      dqs_received,
-    input       dqs_tri
-    
+module  test_dqs01( 
+    input  [1:0] dqs_data, 
+    inout  [1:0] dqs,
+    inout  [1:0] ndqs,
+    output [1:0] dqs_received,
+    input  [1:0] dqs_tri
+   
 );
 
 
@@ -37,10 +37,10 @@ IOBUFDS #(
     .IOSTANDARD("DEFAULT"),
     .SLEW("SLOW")
 ) iobufs_dqs_i (
-    .O(dqs_received),
-    .IO(dqs),
+    .O(dqs_received), 
+    .IO(dqs[1:0]),
     .IOB(ndqs),
-    .I(dqs_data),
+    .I(123),  //2'b11), //dqs_data),
     .T(dqs_tri));
 
 endmodule

phy/test_dqs02.v

@@ -37,7 +37,7 @@ module  test_dqs02(
     input       dqs_tri_a,
     output      dqs_tri
 //    output      dqs_data
-    
+   
 );
 wire refclk_b=refclk; // use buffer
 wire clk, clk_div;

phy/wrap/mmcm_adv.v

+/*******************************************************************************
+ * Module: mmcm_adv
+ * Date:2014-05-01  
+ * Author: Andrey Filippov
+ * Description: MMCME2_ADV wrapper
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * mmcm_adv.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  mmcm_adv.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  mmcm_adv(
+);
+    /* Instance template for module MMCME2_ADV */
+    MMCME2_ADV #(
+        .BANDWIDTH("OPTIMIZED"),
+        .CLKFBOUT_MULT_F(5.000),
+        .CLKFBOUT_PHASE(0.000),
+        .CLKFBOUT_USE_FINE_PS("FALSE"),
+        .CLKIN1_PERIOD(0.000),
+        .CLKIN2_PERIOD(0.000),
+        .CLKOUT0_DIVIDE_F(1.000),
+        .CLKOUT0_DUTY_CYCLE(0.500),
+        .CLKOUT0_PHASE(0.000),
+        .CLKOUT0_USE_FINE_PS("FALSE"),
+        .CLKOUT1_DIVIDE(1),
+        .CLKOUT1_DUTY_CYCLE(0.500),
+        .CLKOUT1_PHASE(0.000),
+        .CLKOUT1_USE_FINE_PS("FALSE"),
+        .CLKOUT2_DIVIDE(1),
+        .CLKOUT2_DUTY_CYCLE(0.500),
+        .CLKOUT2_PHASE(0.000),
+        .CLKOUT2_USE_FINE_PS("FALSE"),
+        .CLKOUT3_DIVIDE(1),
+        .CLKOUT3_DUTY_CYCLE(0.500),
+        .CLKOUT3_PHASE(0.000),
+        .CLKOUT3_USE_FINE_PS("FALSE"),
+        .CLKOUT4_CASCADE("FALSE"),
+        .CLKOUT4_DIVIDE(1),
+        .CLKOUT4_DUTY_CYCLE(0.500),
+        .CLKOUT4_PHASE(0.000),
+        .CLKOUT4_USE_FINE_PS("FALSE"),
+        .CLKOUT5_DIVIDE(1),
+        .CLKOUT5_DUTY_CYCLE(0.500),
+        .CLKOUT5_PHASE(0.000),
+        .CLKOUT5_USE_FINE_PS("FALSE"),
+        .CLKOUT6_DIVIDE(1),
+        .CLKOUT6_DUTY_CYCLE(0.500),
+        .CLKOUT6_PHASE(0.000),
+        .CLKOUT6_USE_FINE_PS("FALSE"),
+        .COMPENSATION("ZHOLD"),
+        .DIVCLK_DIVIDE(1),
+        .IS_CLKINSEL_INVERTED(1'b0),
+        .IS_PSEN_INVERTED(1'b0),
+        .IS_PSINCDEC_INVERTED(1'b0),
+        .IS_PWRDWN_INVERTED(1'b0),
+        .IS_RST_INVERTED(1'b0),
+        .REF_JITTER1(0.010),
+        .REF_JITTER2(0.010),
+        .SS_EN("FALSE"),
+        .SS_MODE("CENTER_HIGH"),
+        .SS_MOD_PERIOD(10000),
+        .STARTUP_WAIT("FALSE")
+    ) MMCME2_ADV_i (
+        .CLKFBOUT(), // output
+        .CLKFBOUTB(), // output
+        .CLKFBSTOPPED(), // output
+        .CLKINSTOPPED(), // output
+        .CLKOUT0(), // output
+        .CLKOUT0B(), // output
+        .CLKOUT1(), // output
+        .CLKOUT1B(), // output
+        .CLKOUT2(), // output
+        .CLKOUT2B(), // output
+        .CLKOUT3(), // output
+        .CLKOUT3B(), // output
+        .CLKOUT4(), // output
+        .CLKOUT5(), // output
+        .CLKOUT6(), // output
+        .DO(), // output[15:0]
+        .DRDY(), // output
+        .LOCKED(), // output
+        .PSDONE(), // output
+        .CLKFBIN(), // input
+        .CLKIN1(), // input
+        .CLKIN2(), // input
+        .CLKINSEL(), // input
+        .DADDR(), // input[6:0]
+        .DCLK(), // input
+        .DEN(), // input
+        .DI(), // input[15:0]
+        .DWE(), // input
+        .PSCLK(), // input
+        .PSEN(), // input
+        .PSINCDEC(), // input
+        .PWRDWN(), // input
+        .RST() // input
+    );
+
+
+endmodule
+

phy/wrap/oserdes_mem.v

@@ -36,7 +36,7 @@ module  oserdes_mem #(
 //localparam integer MODE_DDR_BIN=(MODE_DDR=="TRUE")?1:0;
 localparam         DATA_RATE=   (MODE_DDR=="TRUE")?"DDR":"SDR";
 localparam integer DATA_WIDTH=  (MODE_DDR=="TRUE")?4:2;
-localparam integer DDR3_DATA=   (MODE_DDR=="TRUE")?1:0;
+//localparam integer DDR3_DATA=   (MODE_DDR=="TRUE")?1:0;
 /*
     Serialized data will go through odelay elements (with fine delay adjustment), tristate output will
     go directly. Luckily the active time for DQ/DQS may be extended (there is at least 1 full clock period