troubleshooting lack of DONE during loading of the bitfile (cd3ccb58) · Commits · Elphel / eddr3

.project

+21 −15

Original line number	Diff line number	Diff line
		@@ -5,6 +5,11 @@
		<projects>
		</projects>
		<buildSpec>
		<buildCommand>
		<name>org.python.pydev.PyDevBuilder</name>
		<arguments>
		</arguments>
		</buildCommand>
		<buildCommand>
		<name>com.elphel.vdt.veditor.simulateBuilder</name>
		<arguments>
		@@ -41,6 +46,7 @@
		</buildSpec>
		<natures>
		<nature>com.elphel.vdt.veditor.HdlNature</nature>
		<nature>org.python.pydev.pythonNature</nature>
		</natures>
		<linkedResources>
		<link>
		@@ -56,77 +62,77 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140602122428009.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140606182315739.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140602122428009.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140606182315739.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140602122428009.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140606182315739.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140602122428009.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140606182315739.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140602122428009.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140606182315739.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140602122428009.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140606182315739.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140602115135083.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140606182054344.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140602122428009.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140606182315739.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140602115135083.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140606182315739.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140602122428009.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140606182315739.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140602115135083.log</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140606182315739.log</location>
		</link>
		<link>
		<name>vivado_state/eddr3-opt-phys.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140602122428009.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140606182315739.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-place.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140602122428009.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140606182315739.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-route.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140602122428009.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140606182315739.dcp</location>
		</link>
		<link>
		<name>vivado_state/eddr3-synth.dcp</name>
		<type>1</type>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140602115135083.dcp</location>
		<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140606171026321.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

.settings/com.elphel.vdt.VivadoBitstream.prefs

+2 −1

Original line number	Diff line number	Diff line
		VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
		VivadoBitstream_105_force=true
		com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->
		com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->
		eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoSynthesis.prefs

+2 −1

Original line number	Diff line number	Diff line
		VivadoSynthesis_102_ConstraintsFiles=ddrc_test01.xdc<-@\#\#@->ddrc_test01_timing.xdc<-@\#\#@->
		VivadoSynthesis_115_flatten_hierarchy=none
		VivadoSynthesis_95_ShowInfo=false
		com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->
		com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->
		eclipse.preferences.version=1

ddrc_control.v

+78 −6

Original line number	Diff line number	Diff line
		@@ -52,8 +52,13 @@ module ddrc_control #(
		parameter DLY_RST_REL = 'h02c, // address to activate('h82d)/deactivate('h82c) delay calibration circuitry
		parameter DLY_RST_REL_MASK = 'h3fe, // address mask for delay calibration circuitry
		parameter EXTRA_REL = 'h02e, // address to set extra parameters (currently just inv_clk_div)
		parameter EXTRA_REL_MASK = 'h3ff // address mask for extra parameters

		parameter EXTRA_REL_MASK = 'h3ff, // address mask for extra parameters
		parameter REFRESH_EN_REL = 'h030, // address to enable('h31) and disable ('h30) DDR refresh
		parameter REFRESH_EN_REL_MASK = 'h3fe, // address mask to enable/disable DDR refresh
		parameter REFRESH_PER_REL = 'h032, // address to set refresh period in 32 x tCK
		parameter REFRESH_PER_REL_MASK = 'h3ff, // address mask set refresh period
		parameter REFRESH_ADDR_REL = 'h033, // address to set sequencer start address for DDR refresh
		parameter REFRESH_ADDR_REL_MASK = 'h3ff // address mask set refresh sequencer address
		)(
		input clk,
		input mclk,
		@@ -69,6 +74,17 @@ module ddrc_control #(
		output [10:0] run_addr, // Start address of the physical sequencer (MSB = 0 - "manual", 1 -"auto")
		output [ 3:0] run_chn, // channel number to use for I/O buffers
		output run_seq, // single mclk pulse to start sequencer
		// simple arbitration (should not start if higher priority, busy or run_seq)
		input run_seq_rq_in, // higher priority request to run sequence
		output run_seq_rq_gen,// this wants to run sequencer
		input run_seq_busy, // sequencer is busy or access granted to other master (should be on staring nearest cycle)
		output [10:0] refresh_address,
		output [ 7:0] refresh_period,
		output refresh_set,
		output refresh_en,

		// output run_seq_granted, // this module got sequencer access granted

		// input run_done; // output - will go through other channel - sequencer done (add busy?)
		// control: delays and mmcm setup
		output [ 7:0] dly_data, // 8-bit IDELAY/ODELAY (fine) and MMCM phase shift
		@@ -138,16 +154,37 @@ module ddrc_control #(
		localparam EXTRA_ADDR = CONTROL_ADDR \| EXTRA_REL; // address to set extra parameters (currently just inv_clk_div)
		localparam EXTRA_ADDR_MASK = CONTROL_ADDR_MASK \| EXTRA_REL_MASK; // address mask for extra parameters

		localparam REFRESH_EN_ADDR = CONTROL_ADDR \| REFRESH_EN_REL; // address to enable('h31) and disable ('h30) DDR refresh
		localparam REFRESH_EN_ADDR_MASK = CONTROL_ADDR_MASK \| REFRESH_EN_REL_MASK; // address mask to enable/disable DDR refresh

		localparam REFRESH_PER_ADDR = CONTROL_ADDR \| REFRESH_PER_REL; // address to set refresh period in 32 x tCK
		localparam REFRESH_PER_ADDR_MASK = CONTROL_ADDR_MASK \| REFRESH_PER_REL_MASK; // address mask set refresh period

		localparam REFRESH_ADDR_ADDR = CONTROL_ADDR \| REFRESH_ADDR_REL; // address to set sequencer start address for DDR refresh
		localparam REFRESH_ADDR_ADDR_MASK = CONTROL_ADDR_MASK \| REFRESH_ADDR_REL_MASK; // address mask set refresh sequencer address

		reg [10:0] refresh_address_r;
		reg [ 7:0] refresh_period_r;
		reg refresh_set_r, refresh_set_r0;
		reg refresh_ld_addr;
		reg refresh_en_r;
		wire refresh_set_w; // just decoded

		assign refresh_address = refresh_address_r;
		assign refresh_period = refresh_period_r;
		assign refresh_set = refresh_set_r;
		assign refresh_en = refresh_en_r;

		reg busy_r=0;
		reg selected=0;
		reg selected_busy=0;
		//(* keep = "true" *)

		wire fifo_half_empty; // just debugging with (* keep = "true" *)
		wire [AXI_WR_ADDR_BITS-1:0] waddr_fifo_out;
		wire [31:0] wdata_fifo_out;
		// reg fifo_re; // wrong, need to have (fifo!=1) \|\| !re
		wire fifo_nempty;
		wire fifo_re=fifo_nempty; // try simpler
		wire fifo_re;
		reg [AXI_WR_ADDR_BITS-1:0] waddr_fifo_out_r;
		reg [31:0] wdata_fifo_out_r;
		reg dly_ld_r=0;
		@@ -170,6 +207,20 @@ module ddrc_control #(
		reg [15:0] dqs_tri_pattern_r;
		reg [ 3:0] wbuf_delay_r;

		wire decoded_run_seq;

		assign refresh_set_w= fifo_re && (((waddr_fifo_out ^ REFRESH_PER_ADDR) & REFRESH_PER_ADDR_MASK)==0);
		// reg this_granted;
		// assign run_seq_granted=this_granted;
		assign decoded_run_seq= (((waddr_fifo_out ^ RUN_CHN_ADDR) & RUN_CHN_ADDR_MASK)==0) && !ddr_rst; // without ddr_rst 'bx
		assign run_seq_rq_gen=decoded_run_seq && fifo_nempty ; //
		// assign fifo_re=fifo_nempty; // try simpler
		// need a way to reset if run_seq_busy is forever busy? Will it work to just repeat the same command w/o busy to overrun fifo?
		// ddr_rst_r should reset seqencer?

		// watch higher priority and busy for run_seq command, always ready - for others
		assign fifo_re= fifo_nempty && (decoded_run_seq? (!run_seq_rq_in && !run_seq_busy && !run_seq_r): 1'b1);

		assign wbuf_delay= wbuf_delay_r;
		assign {
		dqs_tri_off_pattern[3:0],
		@@ -236,7 +287,8 @@ module ddrc_control #(
		if (rst) dly_set_r <= 1'b0;
		else dly_set_r <= fifo_re && (((waddr_fifo_out ^ DLY_SET_ADDR) & DLY_SET_ADDR_MASK)==0);
		if (rst) run_seq_r <= 1'b0;
		else run_seq_r <= fifo_re && (((waddr_fifo_out ^ RUN_CHN_ADDR) & RUN_CHN_ADDR_MASK)==0);
		// else run_seq_r <= fifo_re && (((waddr_fifo_out ^ RUN_CHN_ADDR) & RUN_CHN_ADDR_MASK)==0);
		else run_seq_r <= fifo_nempty && decoded_run_seq && !run_seq_rq_in && !run_seq_busy && !run_seq_r;

		if (rst) {dqm_pattern_r,dqs_pattern_r} <= 16'h0055;
		else if (fifo_re && (((waddr_fifo_out ^ PATTERNS_ADDR) & PATTERNS_ADDR_MASK)==0))
		@@ -279,6 +331,26 @@ module ddrc_control #(
		if (rst) wbuf_delay_r <= WBUF_DLY_DFLT;
		else if (fifo_re && (((waddr_fifo_out ^ WBUF_DELAY_ADDR) & WBUF_DELAY_ADDR_MASK)==0))
		wbuf_delay_r <= wdata_fifo_out[3:0];

		if (rst) refresh_en_r <= 1'b0;
		else if (fifo_re && (((waddr_fifo_out ^ REFRESH_EN_ADDR) & REFRESH_EN_ADDR_MASK)==0))
		refresh_en_r <= waddr_fifo_out[0];

		if (rst) refresh_address_r <= 0;
		else if (refresh_ld_addr) refresh_address_r <= wdata_fifo_out_r[10:0];

		if (rst) refresh_period_r <= 0;
		else if (refresh_set_r0) refresh_period_r <= wdata_fifo_out_r[7:0];

		if (rst) refresh_set_r0 <= 0;
		else refresh_set_r0 <= refresh_set_w;

		if (rst) refresh_set_r <= 0;
		else refresh_set_r <= refresh_set_r0;

		if (rst) refresh_ld_addr <= 0;
		else refresh_ld_addr <= fifo_re && (((waddr_fifo_out ^ REFRESH_ADDR_ADDR) & REFRESH_ADDR_ADDR_MASK)==0);

		end
		always @ (posedge mclk) begin
		waddr_fifo_out_r <= waddr_fifo_out;

ddrc_status.v

+6 −3

Original line number	Diff line number	Diff line
		@@ -41,13 +41,16 @@ module ddrc_status
		// status/readback signals
		// input run_done, // sequencer done (add busy?)
		input run_busy, // sequencer busy

		input locked, // MMCM and PLL locked
		input locked_mmcm,
		input locked_pll,
		input dly_ready,
		input dci_ready,
		input ps_rdy, // MMCM phase shift control ready
		input [ 7:0] ps_out // MMCM phase shift value (in 1/56 of the Fvco period)
		);
		assign busy=0;
		assign rdata={21'b0,run_busy,locked,ps_rdy,ps_out[7:0]};
		assign rdata={17'b0,dly_ready,dci_ready, locked_mmcm, locked_pll, run_busy,locked,ps_rdy,ps_out[7:0]};


		endmodule

Admin message