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Commit cd3ccb58 authored by Andrey Filippov's avatar Andrey Filippov
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troubleshooting lack of DONE during loading of the bitfile

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.project
View file @ cd3ccb58
......@@ -5,6 +5,11 @@
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.python.pydev.PyDevBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>com.elphel.vdt.veditor.simulateBuilder</name>
<arguments>
......@@ -41,6 +46,7 @@
</buildSpec>
<natures>
<nature>com.elphel.vdt.veditor.HdlNature</nature>
<nature>org.python.pydev.pythonNature</nature>
</natures>
<linkedResources>
<link>
......@@ -56,77 +62,77 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140602122428009.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140606182315739.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140602122428009.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140606182315739.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140602122428009.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140606182315739.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140602122428009.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140606182315739.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140602122428009.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140606182315739.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140602122428009.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140606182315739.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140602115135083.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140606182054344.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140602122428009.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140606182315739.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140602115135083.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140606182315739.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140602122428009.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140606182315739.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140602115135083.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140606182315739.log</location>
</link>
<link>
<name>vivado_state/eddr3-opt-phys.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140602122428009.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140606182315739.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-place.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140602122428009.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140606182315739.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-route.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140602122428009.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140606182315739.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-synth.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140602115135083.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140606171026321.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ cd3ccb58
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ cd3ccb58
VivadoSynthesis_102_ConstraintsFiles=ddrc_test01.xdc<-@\#\#@->ddrc_test01_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->
eclipse.preferences.version=1
ddrc_control.v
View file @ cd3ccb58
......@@ -52,8 +52,13 @@ module ddrc_control #(
parameter DLY_RST_REL = 'h02c, // address to activate('h82d)/deactivate('h82c) delay calibration circuitry
parameter DLY_RST_REL_MASK = 'h3fe, // address mask for delay calibration circuitry
parameter EXTRA_REL = 'h02e, // address to set extra parameters (currently just inv_clk_div)
parameter EXTRA_REL_MASK = 'h3ff // address mask for extra parameters
parameter EXTRA_REL_MASK = 'h3ff, // address mask for extra parameters
parameter REFRESH_EN_REL = 'h030, // address to enable('h31) and disable ('h30) DDR refresh
parameter REFRESH_EN_REL_MASK = 'h3fe, // address mask to enable/disable DDR refresh
parameter REFRESH_PER_REL = 'h032, // address to set refresh period in 32 x tCK
parameter REFRESH_PER_REL_MASK = 'h3ff, // address mask set refresh period
parameter REFRESH_ADDR_REL = 'h033, // address to set sequencer start address for DDR refresh
parameter REFRESH_ADDR_REL_MASK = 'h3ff // address mask set refresh sequencer address
)(
input clk,
input mclk,
......@@ -63,12 +68,23 @@ module ddrc_control #(
input [AXI_WR_ADDR_BITS-1:0] waddr, // write address, valid with wr_en
input wr_en, // write enable
input [31:0] wdata, // write data, valid with waddr and wr_en
output busy, // interface busy (combinatorial delay from start_wburst and pre_addr
output busy, // interface busy (combinatorial delay from start_wburst and pre_addr
// control signals
// control: sequencer run
output [10:0] run_addr, // Start address of the physical sequencer (MSB = 0 - "manual", 1 -"auto")
output [ 3:0] run_chn, // channel number to use for I/O buffers
output run_seq, // single mclk pulse to start sequencer
// simple arbitration (should not start if higher priority, busy or run_seq)
input run_seq_rq_in, // higher priority request to run sequence
output run_seq_rq_gen,// this wants to run sequencer
input run_seq_busy, // sequencer is busy or access granted to other master (should be on staring nearest cycle)
output [10:0] refresh_address,
output [ 7:0] refresh_period,
output refresh_set,
output refresh_en,
// output run_seq_granted, // this module got sequencer access granted
// input run_done; // output - will go through other channel - sequencer done (add busy?)
// control: delays and mmcm setup
output [ 7:0] dly_data, // 8-bit IDELAY/ODELAY (fine) and MMCM phase shift
......@@ -138,16 +154,37 @@ module ddrc_control #(
localparam EXTRA_ADDR = CONTROL_ADDR | EXTRA_REL; // address to set extra parameters (currently just inv_clk_div)
localparam EXTRA_ADDR_MASK = CONTROL_ADDR_MASK | EXTRA_REL_MASK; // address mask for extra parameters
localparam REFRESH_EN_ADDR = CONTROL_ADDR | REFRESH_EN_REL; // address to enable('h31) and disable ('h30) DDR refresh
localparam REFRESH_EN_ADDR_MASK = CONTROL_ADDR_MASK | REFRESH_EN_REL_MASK; // address mask to enable/disable DDR refresh
localparam REFRESH_PER_ADDR = CONTROL_ADDR | REFRESH_PER_REL; // address to set refresh period in 32 x tCK
localparam REFRESH_PER_ADDR_MASK = CONTROL_ADDR_MASK | REFRESH_PER_REL_MASK; // address mask set refresh period
localparam REFRESH_ADDR_ADDR = CONTROL_ADDR | REFRESH_ADDR_REL; // address to set sequencer start address for DDR refresh
localparam REFRESH_ADDR_ADDR_MASK = CONTROL_ADDR_MASK | REFRESH_ADDR_REL_MASK; // address mask set refresh sequencer address
reg [10:0] refresh_address_r;
reg [ 7:0] refresh_period_r;
reg refresh_set_r, refresh_set_r0;
reg refresh_ld_addr;
reg refresh_en_r;
wire refresh_set_w; // just decoded
assign refresh_address = refresh_address_r;
assign refresh_period = refresh_period_r;
assign refresh_set = refresh_set_r;
assign refresh_en = refresh_en_r;
reg busy_r=0;
reg selected=0;
reg selected_busy=0;
//(* keep = "true" *)
wire fifo_half_empty; // just debugging with (* keep = "true" *)
wire [AXI_WR_ADDR_BITS-1:0] waddr_fifo_out;
wire [31:0] wdata_fifo_out;
// reg fifo_re; // wrong, need to have (fifo!=1) || !re
wire fifo_nempty;
wire fifo_re=fifo_nempty; // try simpler
wire fifo_re;
reg [AXI_WR_ADDR_BITS-1:0] waddr_fifo_out_r;
reg [31:0] wdata_fifo_out_r;
reg dly_ld_r=0;
......@@ -170,6 +207,20 @@ module ddrc_control #(
reg [15:0] dqs_tri_pattern_r;
reg [ 3:0] wbuf_delay_r;
wire decoded_run_seq;
assign refresh_set_w= fifo_re && (((waddr_fifo_out ^ REFRESH_PER_ADDR) & REFRESH_PER_ADDR_MASK)==0);
// reg this_granted;
// assign run_seq_granted=this_granted;
assign decoded_run_seq= (((waddr_fifo_out ^ RUN_CHN_ADDR) & RUN_CHN_ADDR_MASK)==0) && !ddr_rst; // without ddr_rst 'bx
assign run_seq_rq_gen=decoded_run_seq && fifo_nempty ; //
// assign fifo_re=fifo_nempty; // try simpler
// need a way to reset if run_seq_busy is forever busy? Will it work to just repeat the same command w/o busy to overrun fifo?
// ddr_rst_r should reset seqencer?
// watch higher priority and busy for run_seq command, always ready - for others
assign fifo_re= fifo_nempty && (decoded_run_seq? (!run_seq_rq_in && !run_seq_busy && !run_seq_r): 1'b1);
assign wbuf_delay= wbuf_delay_r;
assign {
dqs_tri_off_pattern[3:0],
......@@ -236,7 +287,8 @@ module ddrc_control #(
if (rst) dly_set_r <= 1'b0;
else dly_set_r <= fifo_re && (((waddr_fifo_out ^ DLY_SET_ADDR) & DLY_SET_ADDR_MASK)==0);
if (rst) run_seq_r <= 1'b0;
else run_seq_r <= fifo_re && (((waddr_fifo_out ^ RUN_CHN_ADDR) & RUN_CHN_ADDR_MASK)==0);
// else run_seq_r <= fifo_re && (((waddr_fifo_out ^ RUN_CHN_ADDR) & RUN_CHN_ADDR_MASK)==0);
else run_seq_r <= fifo_nempty && decoded_run_seq && !run_seq_rq_in && !run_seq_busy && !run_seq_r;
if (rst) {dqm_pattern_r,dqs_pattern_r} <= 16'h0055;
else if (fifo_re && (((waddr_fifo_out ^ PATTERNS_ADDR) & PATTERNS_ADDR_MASK)==0))
......@@ -279,6 +331,26 @@ module ddrc_control #(
if (rst) wbuf_delay_r <= WBUF_DLY_DFLT;
else if (fifo_re && (((waddr_fifo_out ^ WBUF_DELAY_ADDR) & WBUF_DELAY_ADDR_MASK)==0))
wbuf_delay_r <= wdata_fifo_out[3:0];
if (rst) refresh_en_r <= 1'b0;
else if (fifo_re && (((waddr_fifo_out ^ REFRESH_EN_ADDR) & REFRESH_EN_ADDR_MASK)==0))
refresh_en_r <= waddr_fifo_out[0];
if (rst) refresh_address_r <= 0;
else if (refresh_ld_addr) refresh_address_r <= wdata_fifo_out_r[10:0];
if (rst) refresh_period_r <= 0;
else if (refresh_set_r0) refresh_period_r <= wdata_fifo_out_r[7:0];
if (rst) refresh_set_r0 <= 0;
else refresh_set_r0 <= refresh_set_w;
if (rst) refresh_set_r <= 0;
else refresh_set_r <= refresh_set_r0;
if (rst) refresh_ld_addr <= 0;
else refresh_ld_addr <= fifo_re && (((waddr_fifo_out ^ REFRESH_ADDR_ADDR) & REFRESH_ADDR_ADDR_MASK)==0);
end
always @ (posedge mclk) begin
waddr_fifo_out_r <= waddr_fifo_out;
......
ddrc_status.v
View file @ cd3ccb58
......@@ -40,14 +40,17 @@ module ddrc_status
output busy, // interface busy (combinatorial delay from start_wburst and pre_addr
// status/readback signals
// input run_done, // sequencer done (add busy?)
input run_busy, // sequencer busy
input run_busy, // sequencer busy
input locked, // MMCM and PLL locked
input locked_mmcm,
input locked_pll,
input dly_ready,
input dci_ready,
input ps_rdy, // MMCM phase shift control ready
input [ 7:0] ps_out // MMCM phase shift value (in 1/56 of the Fvco period)
);
assign busy=0;
assign rdata={21'b0,run_busy,locked,ps_rdy,ps_out[7:0]};
assign rdata={17'b0,dly_ready,dci_ready, locked_mmcm, locked_pll, run_busy,locked,ps_rdy,ps_out[7:0]};
endmodule
......
ddrc_test01.v
View file @ cd3ccb58
This diff is collapsed.
ddrc_test01.xdc
View file @ cd3ccb58
......@@ -203,6 +203,16 @@ set_property PACKAGE_PIN L5 [get_ports {SDDML}]
set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
# output DUMMY_TO_KEEP, // to keep PS7 signals from "optimization"
set_property IOSTANDARD SSTL15 [get_ports {DUMMY_TO_KEEP}]
set_property PACKAGE_PIN E3 [get_ports {DUMMY_TO_KEEP}]
#not yet used, just for debugging
# input MEMCLK, // to keep PS7 signals from "optimization"
set_property IOSTANDARD SSTL15 [get_ports {MEMCLK}]
set_property PACKAGE_PIN M5 [get_ports {MEMCLK}]
# Global constraints
......
ddrc_test01_testbench.sav
View file @ cd3ccb58
This diff is collapsed.
ddrc_test01_testbench.tf
View file @ cd3ccb58
This diff is collapsed.
ddrc_test01_timing.xdc
View file @ cd3ccb58
......@@ -32,11 +32,49 @@ create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
#clkfb_ref 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKFBOUT}
#clk_ref_pre 3.33333 {0.00000 1.66667} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKOUT0}
create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
#Each list contains 2 elements - warning later in DRC
#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
#create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
#Not available initially
#create_generated_clock -name ddr3_sdclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre]
#create_generated_clock -name ddr3_clk [get_netsddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_pre]
#create_generated_clock -name ddr3_clk_div [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/clk_div_pre]
#create_generated_clock -name ddr3_mclk [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/clk_ref_pre]
# try use first from list - seems that 2 are created from the same name
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/sdclk_pre
# ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/sdclk_pre
# lindex is not supported in xdc
#create_generated_clock -name ddr3_sdclk [lindex [get_nets -hierarchical sdclk_pre] 0 ]
#create_generated_clock -name ddr3_clk [lindex [get_nets -hierarchical clk_pre] 0 ]
#create_generated_clock -name ddr3_clk_div [lindex [get_nets -hierarchical clk_div_pre] 0 ]
#create_generated_clock -name ddr3_mclk [lindex [get_nets -hierarchical mclk_pre] 0 ]
#create_generated_clock -name ddr3_clk_ref [lindex [get_nets -hierarchical clk_ref_pre] 0 ]
##create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre -filter {NAME !~ */mmcm_phase_cntr_i*} ]
##create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre -filter {NAME !~ */pll_base_i*} ]
create_generated_clock -name ddr3_sdclk [get_nets */sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets */clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets */clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
#create_generated_clock -name ddr3_sdclk [get_nets -hierarchical *sdclk_pre ]
#create_generated_clock -name ddr3_clk [get_nets -hierarchical *clk_pre ]
#create_generated_clock -name ddr3_clk_div [get_nets -hierarchical *clk_div_pre ]
#create_generated_clock -name ddr3_mclk [get_nets -hierarchical *mclk_pre ]
#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical *clk_ref_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
phy/cmda_single.v
View file @ cd3ccb58
......@@ -50,7 +50,7 @@ oserdes_mem#(
.rst(rst), // reset
.din(din[1:0]), // parallel data in
// .tin(tin[1:0]), // parallel tri-state in
.tin(tin), // parallel tri-state in
.tin(tin), // parallel tri-state in
.dout_dly(d_ser), // data out to be connected to odelay input
.dout_iob(), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
......
phy/ddrc_sequencer.v
View file @ cd3ccb58
......@@ -90,7 +90,17 @@ module ddrc_sequencer #(
input [6:0] dly_addr, // select which delay to program
input ld_delay, // load delay data to selected iodelayl (clk_div synchronous)
input set, // clk_div synchronous set all delays from previously loaded values
output locked,
// output locked,
output locked_mmcm,
output locked_pll,
output dly_ready,
output dci_ready,
output phy_locked_mmcm,
output phy_locked_pll,
output phy_dly_ready,
output phy_dci_ready,
output [7:0] tmp_debug,
output ps_rdy,
output [PHASE_WIDTH-1:0] ps_out,
// read port 0
......@@ -162,6 +172,18 @@ module ddrc_sequencer #(
reg [3:0] run_chn_d;
reg run_seq_d;
// reg tmp_dbg7=0;
wire [7:0] tmp_debug_a;
/*
always @ (posedge clk_in) begin
tmp_dbg7 <= ~tmp_dbg7;
end
assign tmp_debug[7:0] = {tmp_dbg7,tmp_debug_a[6:0]};
*/
assign tmp_debug[7:0] = tmp_debug_a[7:0];
// clk_in
assign run_done=sequence_done;
assign run_busy=cmd_busy[0]; //earliest
assign pause=cmd_fetch? (phy_cmd_add_pause || (phy_cmd_nop && (pause_len != 0))): (cmd_busy[2] && (pause_cntr[CMD_PAUSE_BITS-1:1]!=0));
......@@ -174,6 +196,8 @@ module ddrc_sequencer #(
always @ (posedge mclk or posedge rst) begin
if (rst) cmd_busy <= 0;
// else if (sequence_done) cmd_busy <= 0;
else if (ddr_rst) cmd_busy <= 0; // *************** reset sequencer with DDR reset
else if (sequence_done && cmd_busy[2]) cmd_busy <= 0;
else cmd_busy <= {cmd_busy[1:0],run_seq | cmd_busy[0]};
// Pause counter
......@@ -364,7 +388,19 @@ module ddrc_sequencer #(
.dly_addr (dly_addr[6:0]), // input[6:0]
.ld_delay (ld_delay), // input
.set (set), // input
.locked (locked), // output
// .locked (locked), // output
.locked_mmcm (locked_mmcm), // output
.locked_pll (locked_pll), // output
.dly_ready (dly_ready), // output
.dci_ready (dci_ready), // output
.phy_locked_mmcm (phy_locked_mmcm), // output
.phy_locked_pll (phy_locked_pll), // output
.phy_dly_ready (phy_dly_ready), // output
.phy_dci_ready (phy_dci_ready), // output
.tmp_debug (tmp_debug_a[7:0]),
.ps_rdy (ps_rdy), // output
.ps_out (ps_out[7:0]), // output[7:0]
/// debugging
......
phy/dm_single.v
View file @ cd3ccb58
......@@ -19,10 +19,10 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
//`define use_iobuf 1
module dm_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
parameter IBUF_LOW_PWR ="TRUE", //SuppressThisWarning VEditor not used in OBUF_DCIEN
parameter IOSTANDARD = "SSTL15_T_DCI",
parameter SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
......@@ -60,7 +60,7 @@ odelay_fine_pipe # (
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
) dm_out_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_odelay),
......@@ -69,14 +69,14 @@ odelay_fine_pipe # (
.data_in(d_ser),
.data_out(dq_data_dly)
);
`ifdef use_iobuf
IOBUF_DCIEN #(
.IBUF_LOW_PWR(IBUF_LOW_PWR), //
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.USE_IBUFDISABLE("FALSE")
// SuppressWarnings VivadoSynthesis : VivadoSynthesis: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed
) iobufs_dqs_i (
) iobufs_dm_i (
// .O(dq_di),
.O(),
.IO(dm),
......@@ -84,5 +84,18 @@ IOBUF_DCIEN #(
.IBUFDISABLE(1'b0),
.I(dq_data_dly), //dqs_data),
.T(dq_tri));
`else
/* Instance template for module OBUFT_DCIEN */
OBUFT_DCIEN #(
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW)
) iobufs_dm_i (
.O(dm), // output
.DCITERMDISABLE(dci_disable), // input
.I(dq_data_dly), // input
.T(dq_tri) // input
);
`endif
endmodule
phy/dq_single.v
View file @ cd3ccb58
......@@ -71,7 +71,7 @@ odelay_fine_pipe # (
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_out_dly_i(
) dq_out_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_odelay),
......@@ -86,7 +86,7 @@ IOBUF_DCIEN #(
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.USE_IBUFDISABLE("FALSE")
) iobufs_dqs_i (
) iobufs_dq_i (
.O(dq_di),
.IO(dq),
.DCITERMDISABLE(dci_disable),
......@@ -99,7 +99,7 @@ idelay_fine_pipe # (
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE)
) dqs_in_dly_i(
) dq_in_dly_i(
.clk(clk_div),
.rst(rst),
.set(set_idelay),
......
phy/dqs_single.v
View file @ cd3ccb58
......@@ -19,7 +19,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module dqs_single #(
parameter IODELAY_GRP ="IODELAY_MEMORY",
parameter IBUF_LOW_PWR ="TRUE",
......@@ -34,6 +33,9 @@ module dqs_single #(
input clk_div,
input rst,
output dqs_received_dly,
// output dqs_di, // debugging:
//Input buffer ddrc_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_S (in ddrc_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i macro) has no loads. An input buffer must drive an internal load.
input dci_disable, // disable DCI termination during writes and idle
input [7:0] dly_data,
input [3:0] din,
......@@ -90,7 +92,6 @@ IOBUFDS_DCIEN #(
.IBUFDISABLE(1'b0),
.I(dqs_data_dly), //dqs_data),
.T(dqs_tri));
idelay_fine_pipe # (
.IODELAY_GRP(IODELAY_GRP),
.DELAY_VALUE(0),
......@@ -105,6 +106,5 @@ idelay_fine_pipe # (
.data_in(dqs_di),
.data_out(dqs_received_dly)
);
endmodule
phy/phy_cmd.v
View file @ cd3ccb58
......@@ -76,7 +76,19 @@ module phy_cmd#(
input [6:0] dly_addr, // select which delay to program
input ld_delay, // load delay data to selected iodelayl (clk_div synchronous)
input set, // clk_div synchronous set all delays from previously loaded values
output locked,
// output locked,
output locked_mmcm,
output locked_pll,
output dly_ready,
output dci_ready,
output phy_locked_mmcm,
output phy_locked_pll,
output phy_dly_ready,
output phy_dci_ready,
output [7:0] tmp_debug,
output ps_rdy,
output [PHASE_WIDTH-1:0] ps_out,
// command port
......@@ -161,11 +173,17 @@ module phy_cmd#(
wire phy_dci_dis_dqs;
reg dqs_tri_prev, dq_tri_prev;
wire phy_locked;
// wire phy_locked;
wire phy_ps_rdy;
wire [PHASE_WIDTH-1:0] phy_ps_out;
reg locked_r1,locked_r2;
// reg locked_r1,locked_r2;
reg ps_rdy_r1,ps_rdy_r2;
reg locked_mmcm_r1,locked_mmcm_r2;
reg locked_pll_r1, locked_pll_r2;
reg dly_ready_r1, dly_ready_r2;
reg dci_ready_r1, dci_ready_r2;
reg [PHASE_WIDTH-1:0] ps_out_r1,ps_out_r2;
wire [63:0] phy_rdata; // data read from ddr3 iserdese2 at posedge clk_div
reg [63:0] phy_rdata_r; // registered @ posedge mclk
......@@ -175,6 +193,11 @@ module phy_cmd#(
wire [ADDRESS_NUMBER-1:0] phy_addr_calm;
wire [ 2:0] phy_bank_calm;
reg [ 8:0] extra_prev;
// assign phy_locked= phy_locked_mmcm && phy_locked_pll; // no dci and dly here
// output [63:0] buf_wdata, // data to be written to the buffer (from DDR3)
// SuppressWarnings VEditor
(* keep = "true" *) wire phy_spare;
......@@ -252,10 +275,15 @@ module phy_cmd#(
assign phy_dci_dis_dq = phy_dci_in; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
assign phy_dci_dis_dqs = phy_dci_in || phy_odt_cur; // In write leveling mode phy_dci_in = 0, phy_odt_cur=1 - use DCI on DQ only, no DQS
assign locked = locked_r2;
// assign locked = locked_r2;
assign ps_rdy = ps_rdy_r2;
assign ps_out = ps_out_r2;
assign locked_mmcm = locked_mmcm_r2;
assign locked_pll = locked_pll_r2;
assign dly_ready = dly_ready_r2;
assign dci_ready = dci_ready_r2;
assign buf_wdata[63:0] = phy_rdata_r[63:0];
assign cmda_tri=!cmda_en;
......@@ -307,14 +335,25 @@ module phy_cmd#(
// cross clock boundary posedge posedge clk_div->negedge clk_div -> posedge mclk (mclk is later than clk_div)
always @ (negedge clk_div) begin
locked_r1 <= phy_locked;
// locked_r1 <= phy_locked;
ps_rdy_r1 <= phy_ps_rdy;
ps_out_r1 <= phy_ps_out;
ps_out_r1 <= phy_ps_out;
locked_mmcm_r1 <= phy_locked_mmcm;
locked_pll_r1 <= phy_locked_pll;
dly_ready_r1 <= phy_dly_ready;
dci_ready_r1 <= phy_dci_ready;
end
always @ (posedge mclk) begin
locked_r2 <= locked_r1;
// locked_r2 <= locked_r1;
ps_rdy_r2 <= ps_rdy_r1;
ps_out_r2 <= ps_out_r1;
locked_mmcm_r2 <= locked_mmcm_r1;
locked_pll_r2 <= locked_pll_r1;
dly_ready_r2 <= dly_ready_r1;
dci_ready_r2 <= dci_ready_r1;
end
......@@ -405,7 +444,12 @@ module phy_cmd#(
.dly_addr (dly_addr_r), // input[6:0]
.ld_delay (ld_delay_r), // input
.set (set_r), // input
.locked (phy_locked), // output
// .locked (phy_locked), // output
.locked_mmcm (phy_locked_mmcm), // output
.locked_pll (phy_locked_pll), // output
.dly_ready (phy_dly_ready), // output
.dci_ready (phy_dci_ready), // output
.tmp_debug (tmp_debug[7:0]),
.ps_rdy (phy_ps_rdy), // output
.ps_out (phy_ps_out) // output[7:0]
);
......
phy/phy_top.v
View file @ cd3ccb58
......@@ -106,25 +106,63 @@ module phy_top #(
input [6:0] dly_addr, // select which delay to program
input ld_delay, // load delay data to selected iodelayl (clk_div synchronous)
input set, // clk_div synchronous set all delays from previously loaded values
output locked,
// output locked,
output locked_mmcm,
output locked_pll,
output dly_ready,
output dci_ready,
output [7:0] tmp_debug,
output ps_rdy,
output [PHASE_WIDTH-1:0] ps_out
);
reg rst=1'b0;
reg rst= 1'b1;
// reg rst_dbg=1'b1;
// always @(posedge clk_div or posedge rst_in) begin // got min hold violation
always @(negedge clk_div or posedge rst_in) begin
if (rst_in) rst <= 1'b1;
else rst <= 1'b0;
end
// always @(posedge clk_div or posedge rst_in) begin
// if (rst_in) rst_dbg <= 1'b1;
// else rst_dbg <= 1'b0;
// end
wire ld_data_l = (dly_addr[6:5] == 2'h0) && ld_delay ;
wire ld_data_h = (dly_addr[6:5] == 2'h1) && ld_delay ;
wire ld_cmda = (dly_addr[6:5] == 2'h2) && ld_delay ;
wire ld_mmcm= (dly_addr[6:0] == 7'h60) && ld_delay ;
wire clkfb_ref, clk_ref_pre;
wire clk_ref; // 200MHz/300Mhz to calibrate I/O delays
wire locked_mmcm,locked_pll, dly_ready, dci_ready;
assign locked=locked_mmcm && locked_pll && dly_ready && dci_ready; // both PLL ready, I/O delay calibrated
// wire locked_mmcm,locked_pll, dly_ready, dci_ready;
// assign locked=locked_mmcm && locked_pll && dly_ready && dci_ready; // both PLL ready, I/O delay calibrated
wire clkin_stopped_mmcm;
wire clkfb_stopped_mmcm;
/*
reg dbg_reg1=1;
reg dbg_reg2=1;
reg dbg_reg3=1;
*/
assign tmp_debug ={
dly_addr[1],
dly_addr[0],
clkin_stopped_mmcm,
clkfb_stopped_mmcm,
ddr_rst,
rst_in,
dci_rst,
dly_rst
};
/*
always @ (posedge clk_in) begin
dbg_reg1 <= ~dbg_reg1;
end
always @ (posedge clk_ref) begin
dbg_reg2 <= ~dbg_reg2;
end
always @ (posedge clk_div) begin
dbg_reg3 <= ~dbg_reg3;
end
*/
/* memory reset */
obuf #(
.CAPACITANCE("DONT_CARE"),
......@@ -241,9 +279,10 @@ wire sdclk; // BUFIO
) oddr_ds_i (
.clk(sdclk), // input
.ce(1'b1), // input
.rst(1'b0), // input
.rst(rst), // input
.set(1'b0), // input
.din(2'b01), // input[1:0]
.tin(rst), // tristate at reset
.dq(ddr3_clk), // output
.ndq(ddr3_nclk) // output
);
......@@ -321,9 +360,12 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
.clkout1b(), // output
.clkout2b(), // output
.clkout3b(), // output
.clkfbout(clk_fb), // output
.clkfbout (clk_fb), // output
.clkfboutb(), // output
.locked(locked_mmcm) // output
.locked (locked_mmcm),
.clkin_stopped (clkin_stopped_mmcm), // output
.clkfb_stopped (clkfb_stopped_mmcm) // output
// output
);
// Generate reference clock for the I/O delays
......@@ -357,11 +399,10 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
.rst(rst || dly_rst),
.rdy(dly_ready)
);
dci_reset dci_reset_i (
.reset(rst || dci_rst), // input
.ready(dci_ready) // output
);
//assign dci_ready= !(rst || dci_rst);
endmodule
wrap/mmcm_phase_cntr.v
View file @ cd3ccb58
......@@ -95,7 +95,9 @@ module mmcm_phase_cntr#(
output clkout3b, // output 3, inverted
output clkfbout, // dedicate feedback output
output clkfboutb,// inverted feedback output
output locked // PLL locked output
output locked, // PLL locked output
output clkin_stopped,
output clkfb_stopped
);
reg [PHASE_WIDTH-1:0] ps_dout_r;
wire psen; // phase shift enable input
......@@ -185,8 +187,8 @@ module mmcm_phase_cntr#(
) MMCME2_ADV_i (
.CLKFBOUT (clkfbout), // output
.CLKFBOUTB (clkfboutb), // output
.CLKFBSTOPPED (), // output
.CLKINSTOPPED (), // output
.CLKFBSTOPPED (clkfb_stopped), // output
.CLKINSTOPPED (clkin_stopped), // output
.CLKOUT0 (clkout0), // output
.CLKOUT0B (clkout0b), // output
.CLKOUT1 (clkout1), // output
......
wrap/oddr_ds.v
View file @ cd3ccb58
......@@ -33,6 +33,7 @@ module oddr_ds # (
input rst,
input set,
input [1:0] din,
input tin, // tristate control
output dq,
output ndq
);
......@@ -53,6 +54,7 @@ module oddr_ds # (
);
/* Instance template for module OBUFDS */
/*
OBUFDS #(
.CAPACITANCE(CAPACITANCE),
.IOSTANDARD(IOSTANDARD),
......@@ -62,7 +64,19 @@ module oddr_ds # (
.OB(ndq), // output
.I(idq) // input
);
*/
/* Instance template for module OBUFTDS */
OBUFTDS #(
.CAPACITANCE (CAPACITANCE),
.IOSTANDARD (IOSTANDARD),
.SLEW (SLEW)
) OBUFDS_i (
.O (dq), // output
.OB (ndq), // output
.I (idq), // input
// .T (tin || rst) // input
.T (tin) // input
);
endmodule
wrap/oserdes_mem.v
View file @ cd3ccb58
......@@ -51,11 +51,11 @@ localparam integer DATA_WIDTH_TRI= (MODE_DDR=="TRUE")?4:1;
.DATA_RATE_OQ (DATA_RATE),
.DATA_RATE_TQ (DATA_RATE),
.DATA_WIDTH (DATA_WIDTH),
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.INIT_OQ (1'b1),
.INIT_TQ (1'b1),
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.SRVAL_OQ (1'b1),
.SRVAL_TQ (1'b1),
.TRISTATE_WIDTH (DATA_WIDTH_TRI),
.TBYTE_CTL ("FALSE"),
.TBYTE_SRC ("FALSE")
......@@ -94,13 +94,13 @@ localparam integer DATA_WIDTH_TRI= (MODE_DDR=="TRUE")?4:1;
.DATA_RATE_TQ (DATA_RATE),
.DATA_WIDTH (DATA_WIDTH),
// .DDR3_DATA (DDR3_DATA), //For DDR3 DQ, DQS: 1, Address, ctrl, clock - 0
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.INIT_OQ (1'b1),
.INIT_TQ (1'b1),
.INTERFACE_TYPE ("DEFAULT"), //"DEFAULT", "MEMORY_DDR3"
.ODELAY_USED (0), // 1 available only for MEMORY_DDR3
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.SRVAL_OQ (1'b1),
.SRVAL_TQ (1'b1),
.TRISTATE_WIDTH (DATA_WIDTH_TRI)
) oserdes_i (
.OFB (dout_dly),
......
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