Commit 8b1e18d4 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

debugging

parent c8904b67

.project

+8 −8
Original line number Original line Diff line number Diff line
@@ -51,7 +51,7 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140520232524498.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140522152648076.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<name>vivado_logs/VivadoOptPhys.log</name>
@@ -61,12 +61,12 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140520232524498.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140522152648076.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140520232524498.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140522152648076.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<name>vivado_logs/VivadoRoute.log</name>
@@ -76,7 +76,7 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140520232242973.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140522152648076.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
@@ -86,7 +86,7 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140520232524498.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140522152648076.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
@@ -96,7 +96,7 @@ 
		<link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140520232524498.log</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140522152648076.log</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_state/eddr3-opt-phys.dcp</name>

			<name>vivado_state/eddr3-opt-phys.dcp</name>
@@ -106,7 +106,7 @@ 
		<link>

		<link>

			<name>vivado_state/eddr3-place.dcp</name>

			<name>vivado_state/eddr3-place.dcp</name>

			<type>1</type>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140520232524498.dcp</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140522152648076.dcp</location>

		</link>

		</link>

		<link>

		<link>

			<name>vivado_state/eddr3-route.dcp</name>

			<name>vivado_state/eddr3-route.dcp</name>
@@ -116,7 +116,7 @@ 
		<link>

		<link>

			<name>vivado_state/eddr3-synth.dcp</name>

			<name>vivado_state/eddr3-synth.dcp</name>

			<type>1</type>

			<type>1</type>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140520204515091.dcp</location>

			<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140522152648076.dcp</location>

		</link>

		</link>

	</linkedResources>

	</linkedResources>

</projectDescription>
 
</projectDescription>

.settings/com.elphel.vdt.iverilog.prefs

0 → 100644
+8 −0
Original line number Original line Diff line number Diff line 
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->

eclipse.preferences.version=1

iverilog_77_Param_Exe=/usr/local/bin/iverilog

iverilog_78_VVP_Exe=/usr/local/bin/vvp

iverilog_81_TopModulesOther=glbl<-@\#\#@->

iverilog_83_ExtraFiles=glbl.v<-@\#\#@->

iverilog_88_ShowNoProblem=true

iverilog_99_GrepFindErrWarn=error|warning|sorry

ddrc_control.v

+2 −1
Original line number Original line Diff line number Diff line
@@ -114,7 +114,8 @@ module ddrc_control #( 
    reg busy_r=0;

    reg busy_r=0;

    reg selected=0;

    reg selected=0;

    reg selected_busy=0;

    reg selected_busy=0;

(* keep = "true" *)    wire fifo_half_empty; // just debugging with (* keep = "true" *)

//(* keep = "true" *)

    wire fifo_half_empty; // just debugging with (* keep = "true" *)

    wire [AXI_WR_ADDR_BITS-1:0] waddr_fifo_out;

    wire [AXI_WR_ADDR_BITS-1:0] waddr_fifo_out;

    wire                 [31:0] wdata_fifo_out;

    wire                 [31:0] wdata_fifo_out;

//    reg                         fifo_re; // wrong, need to have (fifo!=1) || !re 

//    reg                         fifo_re; // wrong, need to have (fifo!=1) || !re

ddrc_test01.v

+11 −6
Original line number Original line Diff line number Diff line
@@ -35,7 +35,7 @@ module ddrc_test01 #( 
    parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock

    parameter CLKFBOUT_DIV_REF =    3, // To get 300MHz for the reference clock

    parameter DIVCLK_DIVIDE=        1,

    parameter DIVCLK_DIVIDE=        1,

    parameter CLKFBOUT_PHASE =      0.000,

    parameter CLKFBOUT_PHASE =      0.000,

    parameter ICLK_PHASE =          0.000,

    parameter SDCLK_PHASE =         0.000,

    parameter CLK_PHASE =           0.000,

    parameter CLK_PHASE =           0.000,

    parameter CLK_DIV_PHASE =       0.000,

    parameter CLK_DIV_PHASE =       0.000,

    parameter MCLK_PHASE =          90.000,

    parameter MCLK_PHASE =          90.000,
@@ -99,14 +99,18 @@ module ddrc_test01 #( 
);

);

    localparam ADDRESS_NUMBER=15;

    localparam ADDRESS_NUMBER=15;

// Source for reset and clock

// Source for reset and clock

(* keep = "true" *)

   wire    [3:0]     fclk;      // PL Clocks [3:0], output

   wire    [3:0]     fclk;      // PL Clocks [3:0], output

(* keep = "true" *)

   wire    [3:0]     frst;      // PL Clocks [3:0], output

   wire    [3:0]     frst;      // PL Clocks [3:0], output

   

   

   

   

    

    

// AXI write interface signals

// AXI write interface signals

(* keep = "true" *)

   wire           axi_aclk;    // clock - should be buffered

   wire           axi_aclk;    // clock - should be buffered

//   wire           axi_aresetn; // reset, active low

//   wire           axi_aresetn; // reset, active low

(* keep = "true" *)

   wire           axi_rst;     // reset, active high

   wire           axi_rst;     // reset, active high

// AXI Write Address

// AXI Write Address

   wire   [31:0]  axi_awaddr;  // AWADDR[31:0], input

   wire   [31:0]  axi_awaddr;  // AWADDR[31:0], input
@@ -238,8 +242,9 @@ always @ (posedge axi_rst or posedge axi_aclk) begin 
end

end

   

   

// Clock and reset from PS

// Clock and reset from PS

BUFG axi_rst_i  (.O(axi_rst),.I(~frst[0]));

BUFG bufg_axi_rst_i  (.O(axi_rst),.I(~frst[0]));

BUFG axi_aclk_i (.O(axi_aclk),.I(~fclk[0]));

BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));



    axibram_write #(

    axibram_write #(

        .ADDRESS_BITS(AXI_WR_ADDR_BITS)

        .ADDRESS_BITS(AXI_WR_ADDR_BITS)

    ) axibram_write_i (

    ) axibram_write_i (
@@ -390,7 +395,7 @@ BUFG axi_aclk_i (.O(axi_aclk),.I(~fclk[0])); 
        .CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),

        .CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),

        .DIVCLK_DIVIDE    (DIVCLK_DIVIDE),

        .DIVCLK_DIVIDE    (DIVCLK_DIVIDE),

        .CLKFBOUT_PHASE   (CLKFBOUT_PHASE),

        .CLKFBOUT_PHASE   (CLKFBOUT_PHASE),

        .ICLK_PHASE       (ICLK_PHASE),

        .SDCLK_PHASE      (SDCLK_PHASE),

        .CLK_PHASE        (CLK_PHASE),

        .CLK_PHASE        (CLK_PHASE),

        .CLK_DIV_PHASE    (CLK_DIV_PHASE),

        .CLK_DIV_PHASE    (CLK_DIV_PHASE),

        .MCLK_PHASE       (MCLK_PHASE),

        .MCLK_PHASE       (MCLK_PHASE),

ddrc_test01_testbench.sav

+11 −10
Original line number Original line Diff line number Diff line 
[*]

[*]

[*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI

[*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI

[*] Thu May 22 07:54:47 2014

[*] Thu May 22 08:13:51 2014

[*]

[*]

[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140522015055672.lxt"

[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140522015451433.lxt"

[dumpfile_mtime] "Thu May 22 07:51:58 2014"

[dumpfile_mtime] "Thu May 22 07:55:55 2014"

[dumpfile_size] 63157569

[dumpfile_size] 62511235

[savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav"

[savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav"

[timestart] 98147000

[timestart] 103533370

[size] 1920 1180

[size] 1830 1145

[pos] -1921 -1

[pos] -1 -1

*-20.053656 101463750 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

*-11.053656 103539375 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

[treeopen] ddrc_test01_testbench.

[treeopen] ddrc_test01_testbench.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.

[treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.
@@ -742,7 +742,9 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_ph 
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfbout[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfbout[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfboutb[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkfboutb[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkin[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkin[0]

@29

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0[0]

@28

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0b[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout0b[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout1[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout1[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout1b[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.clkout1b[0]
@@ -762,9 +764,8 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_ph 
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_din[7:0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_din[7:0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_dout[7:0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_dout[7:0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_dout_r[7:0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_dout_r[7:0]

@29

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_ready[0]

@28

@28

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_ready[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start0[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start0[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start[0]

ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.mmcm_phase_cntr_i.ps_start[0]

@22

@22