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eddr3
Commit 7e44243b authored by Andrey Filippov's avatar Andrey Filippov
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organized new/debug files

parent cd437a8f
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.gitignore
View file @ 7e44243b
......@@ -4,4 +4,6 @@ vivado_*
syntax_*
simulation/*
ise_*
attic/*
IVERILOG_INCLUDE.v
eddr3.prj
\ No newline at end of file
.project
View file @ 7e44243b
......@@ -62,77 +62,77 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140607160728042.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140607175804607.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140607160728042.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140607175804607.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140607160728042.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140607175804607.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140607160728042.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140607175804607.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140607160728042.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140607175804607.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140607160728042.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140607175804607.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140607160650782.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140607173533434.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140607160728042.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140607175804607.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140607160728042.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140607173533434.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140607160728042.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140607175804607.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140607160728042.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140607173533434.log</location>
</link>
<link>
<name>vivado_state/eddr3-opt-phys.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140607160728042.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140607175804607.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-place.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140607160728042.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140607175804607.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-route.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140607160728042.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140607175804607.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-synth.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140607005118430.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140607173533434.dcp</location>
</link>
</linkedResources>
</projectDescription>
.pydevproject 0 → 100644
View file @ 7e44243b
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?eclipse-pydev version="1.0"?><pydev_project>
<pydev_property name="org.python.pydev.PYTHON_PROJECT_INTERPRETER">Default</pydev_property>
<pydev_property name="org.python.pydev.PYTHON_PROJECT_VERSION">python 2.7</pydev_property>
</pydev_project>
ddr_refresh.v 0 → 100644
View file @ 7e44243b
/*******************************************************************************
* Module: ddr_refresh
* Date:2014-06-02
* Author: Andrey Filippov
* Description: DDR3 memory refresh request module
*
* Copyright (c) 2014 Elphel, Inc.
* ddr_refresh.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ddr_refresh.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module ddr_refresh(
input rst,
input clk,
input [7:0] refresh_period, // in 16*clk
input set, // and reset counters
output want, // turns off next cycle after grant (or stays on if more are needed)
output need,
input grant // 1 cycle
);
reg [3:0] pre_div;
reg [4:0] pending_rq; // can accumulate up to 31 requests, datasheet allows up to 16
reg [7:0] period_cntr;
reg cry;
wire over=(period_cntr == 0) && cry;
reg refresh_due;
assign want = pending_rq != 0;
assign need = pending_rq[4:3] != 0;
always @ (posedge rst or posedge clk) begin
if (rst) pre_div <= 0;
else if (set) pre_div <= 0;
else pre_div <= pre_div +1;
if (rst) cry <= 0;
else if (set) cry <= 0;
else cry <= (pre_div == 4'hf);
if (rst) period_cntr <= 0;
else if (set) period_cntr <= 0;
else if (over) period_cntr <= refresh_period;
else if (cry) period_cntr <= period_cntr -1;
if (rst) refresh_due <= 0;
else refresh_due <= over;
if (rst) pending_rq <= 0;
else if (set) pending_rq <= 0;
else if ( refresh_due && !grant) pending_rq <= pending_rq+1;
else if (!refresh_due && grant) pending_rq <= pending_rq-1;
end
endmodule
ddrc_test01.v
View file @ 7e44243b
......@@ -369,13 +369,13 @@ assign gpio_in={
phy_locked_mmcm, // 1 1
phy_locked_pll, // 1 1
phy_dly_ready, // 1 0
phy_dci_ready, // 1 0
phy_dly_ready, // 1 0
locked_mmcm, // 1 1
locked_pll, // 1 1
dly_ready, // 1 0
dci_ready, // 1 0
dly_ready, // 1 0
ps_out[7:4], // 4'b0 input[7:0] 4'b0
......
py/exp_gpio.py 0 → 100755
View file @ 7e44243b
#!/usr/bin/env python
from __future__ import print_function
import sys
if len(sys.argv) < 3 or (sys.argv[1] != "in" and sys.argv[1] != "out") :
print ("Usage: ", sys.argv[0]+" <in|out> <gpio_number>[<gpio_max_number>]")
exit (0)
mode = sys.argv[1]
gpio_low_n=int(sys.argv[2])
if len(sys.argv)>3:
gpio_high_n=int(sys.argv[3])
else:
gpio_high_n=gpio_low_n
print ("exporting as \""+mode+"\":", end=""),
for gpio_n in range (gpio_low_n, gpio_high_n+1):
print (" %d"%gpio_n, end="")
print()
# bash> echo 240 > /sys/class/gpio/export
# bash> echo out > /sys/class/gpio/gpio240/direction
# bash> echo 1 > /sys/class/gpio/gpio240/value
for gpio_n in range (gpio_low_n, gpio_high_n+1):
try:
with open ("/sys/class/gpio/export","w") as f:
print (gpio_n,file=f)
except:
print ("failed \"echo %d > /sys/class/gpio/export"%gpio_n)
try:
with open ("/sys/class/gpio/gpio%d/direction"%gpio_n,"w") as f:
print (mode,file=f)
except:
print ("failed \"echo %s > /sys/class/gpio/gpio%d/direction"%(mode,gpio_n))
py/mem.py 0 → 100755
View file @ 7e44243b
#!/usr/bin/env python
import mmap
import sys
import struct
PAGE_SIZE=4096
endian="<" # little, ">" for big
if len(sys.argv)<2:
print "Usage: ", sys.argv[0]+" address [data]"
exit (0)
addr=int(sys.argv[1],16) & 0xfffffffc
data=0
writeMode=len(sys.argv)>2
if (writeMode):
data=int(sys.argv[2],16)
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), PAGE_SIZE, offset=page_addr)
if writeMode:
packedData=struct.pack(endian+"L",data)
d=struct.unpack(endian+"L",packedData)[0]
mm[page_offs:page_offs+4]=packedData
print ("0x%08x <== 0x%08x (%d)"%(addr,d,d))
else:
data=struct.unpack(endian+"L",mm[page_offs:page_offs+4])
d=data[0]
print ("0x%08x ==> 0x%08x (%d)"%(addr,d,d))
mm.close()
py/memdump.py 0 → 100755
View file @ 7e44243b
#!/usr/bin/env python
import mmap
import sys
import struct
PAGE_SIZE=4096
endian="<" # little, ">" for big
if len(sys.argv)<=1:
print "Usage: ", sys.argv[0]+" start_address end_address"
exit (0)
start_addr=int(sys.argv[1],16) & 0xfffffffc
if len(sys.argv)>2:
end_addr=int(sys.argv[2],16) & 0xfffffffc
else:
end_addr=start_addr
data=0
writeMode=len(sys.argv)>2
with open("/dev/mem", "r+b") as f:
for addr in range (start_addr,end_addr+4,4):
page_addr=addr & (~(PAGE_SIZE-1))
if (addr == start_addr) or ((addr & 0x3f) == 0):
print ("\n0x%08x:"%addr),
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), PAGE_SIZE, offset=page_addr)
data=struct.unpack(endian+"L",mm[page_offs:page_offs+4])
d=data[0]
print ("%08x"%d),
mm.close()
py/mon_gpio.py 0 → 100755
View file @ 7e44243b
#!/usr/bin/env python
from __future__ import print_function
import sys
if len(sys.argv) < 2 :
print ("Usage: ", sys.argv[0]+" <gpio_number>[<gpio_max_number>]")
exit (0)
gpio_low_n=int(sys.argv[1])
if len(sys.argv)>2:
gpio_high_n=int(sys.argv[2])
else:
gpio_high_n=gpio_low_n
print ("gpio %d.%d: "%(gpio_high_n,gpio_low_n), end=""),
# bash> echo 240 > /sys/class/gpio/export
# bash> echo out > /sys/class/gpio/gpio240/direction
# bash> echo 1 > /sys/class/gpio/gpio240/value
for gpio_n in range (gpio_high_n, gpio_low_n-1,-1):
if gpio_n != gpio_high_n and ((gpio_n-gpio_low_n+1) % 4) == 0:
print (".",end="")
try:
with open ("/sys/class/gpio/gpio%d/value"%gpio_n,"r") as f:
print (f.read(1),end="")
except:
print ("X",end="")
print()
wrap/dci_reset.v 0 → 100644
View file @ 7e44243b
/*******************************************************************************
* Module: dci_reset
* Date:2014-06-01
* Author: Andrey Filippov
* Description: DCIRESET primitivbe wrapper
*
* Copyright (c) 2014 Elphel, Inc.
* dci_reset.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dci_reset.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module dci_reset(
input reset,
output ready
);
DCIRESET DCIRESET_i (
.LOCKED(ready), // output
.RST(reset) // input
);
endmodule
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