Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
E
eddr3
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Wiki
Wiki
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Elphel
eddr3
Commits
52b99362
Commit
52b99362
authored
Jun 15, 2014
by
Andrey Filippov
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
added glbl.v
parent
e00b15e3
Changes
2
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
36 additions
and
1 deletion
+36
-1
.gitignore
.gitignore
+0
-1
glbl.v
glbl.v
+36
-0
No files found.
.gitignore
View file @
52b99362
unisims
unisims
glbl.v
vivado_*
vivado_*
syntax_*
syntax_*
simulation/*
simulation/*
...
...
glbl.v
0 → 100644
View file @
52b99362
`timescale
1
ps
/
1
ps
module
glbl
()
;
parameter
ROC_WIDTH
=
100000
;
parameter
TOC_WIDTH
=
0
;
//SuppressWarnings VEditor - this value is used in other modules through global reference
wire
GSR
;
//SuppressWarnings VEditor - this value is used in other modules through global reference
wire
GTS
;
//SuppressWarnings VEditor - this value is used in other modules through global reference
wire
PRLD
;
//SuppressWarnings VEditor - this value is used in other modules through global reference
wire
PLL_LOCKG
;
reg
GSR_int
;
reg
GTS_int
;
reg
PRLD_int
;
assign
(
weak1
,
weak0
)
GSR
=
GSR_int
;
assign
(
weak1
,
weak0
)
GTS
=
GTS_int
;
assign
(
weak1
,
weak0
)
PRLD
=
PRLD_int
;
initial
begin
GSR_int
=
1'b1
;
PRLD_int
=
1'b1
;
#(
ROC_WIDTH
)
GSR_int
=
1'b0
;
PRLD_int
=
1'b0
;
end
initial
begin
GTS_int
=
1'b1
;
#(
TOC_WIDTH
)
GTS_int
=
1'b0
;
end
endmodule
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment