Commit 407c39ca authored by Andrey Filippov's avatar Andrey Filippov

fixed warnings

parent e9a79158
...@@ -34,7 +34,7 @@ module test_dqs( ...@@ -34,7 +34,7 @@ module test_dqs(
inout ndqs, inout ndqs,
output dqs_received, output dqs_received,
output dly_ready, output dly_ready,
input dqs_tri_a, // input dqs_tri_a,
output dqs_tri output dqs_tri
); );
......
...@@ -36,12 +36,24 @@ IOBUFDS #( ...@@ -36,12 +36,24 @@ IOBUFDS #(
.IBUF_LOW_PWR("TRUE"), .IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"), .IOSTANDARD("DEFAULT"),
.SLEW("SLOW") .SLEW("SLOW")
) iobufs_dqs_i ( ) iobufs_dqs_i0 (
.O(dqs_received), .O(dqs_received[0]),
.IO(dqs[1:0]), .IO(dqs[0]),
.IOB(ndqs), .IOB(ndqs[0]),
.I(123), //2'b11), //dqs_data), .I(dqs_data[0]),
.T(dqs_tri)); .T(dqs_tri[0]));
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i1 (
.O(dqs_received[1]),
.IO(dqs[1]),
.IOB(ndqs[1]),
.I(dqs_data[1]),
.T(dqs_tri[1]));
endmodule endmodule
...@@ -24,18 +24,18 @@ module test_dqs02( ...@@ -24,18 +24,18 @@ module test_dqs02(
input rst, // reset input rst, // reset
input refclk, // 200MHz/300MHz for delay calibration input refclk, // 200MHz/300MHz for delay calibration
input clk_in, input clk_in,
input set, // input set,
input ld_dly_data, // input ld_dly_data,
input ld_dly_tri, // input ld_dly_tri,
input [7:0] dly_data, // input [7:0] dly_data,
input [3:0] data_in, input [3:0] data_in,
input [3:0] tri_in, // input [3:0] tri_in,
inout dqs, inout dqs,
inout ndqs, // inout ndqs,
output dqs_received, output dqs_received,
output dly_ready, output dly_ready
input dqs_tri_a, // input dqs_tri_a,
output dqs_tri // output dqs_tri
// output dqs_data // output dqs_data
); );
...@@ -43,7 +43,7 @@ wire refclk_b=refclk; // use buffer ...@@ -43,7 +43,7 @@ wire refclk_b=refclk; // use buffer
wire clk, clk_div; wire clk, clk_div;
//wire dqs_data,dqs_tri; // after odelay //wire dqs_data,dqs_tri; // after odelay
//wire dqs_data; // after odelay //wire dqs_data; // after odelay
wire pre_dqs_data,pre_dqs_tri; // before odelay //wire pre_dqs_data,pre_dqs_tri; // before odelay
wire dqs_data; wire dqs_data;
BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1)); BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1));
BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1)); BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1));
...@@ -58,7 +58,8 @@ oserdes_mem oserdes_dqs_i( ...@@ -58,7 +58,8 @@ oserdes_mem oserdes_dqs_i(
.dout_dly(), //pre_dqs_data), // data out to be connected to odelay input .dout_dly(), //pre_dqs_data), // data out to be connected to odelay input
.dout_iob(dqs_data), // data out to be connected directly to the output buffer .dout_iob(dqs_data), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input .tout_dly(), // tristate out to be connected to odelay input
.tout_iob(pre_dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer // .tout_iob(pre_dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer
.tout_iob() // tristate out to be connected directly to the tristate control of the output buffer
); );
idelay_ctrl# ( idelay_ctrl# (
......
...@@ -36,7 +36,9 @@ module test_dqs03( ...@@ -36,7 +36,9 @@ module test_dqs03(
input ld input ld
); );
wire clk,clk_div,clk_ref; //SuppressWarnings all
wire clk;
wire clk_div,clk_ref;
wire dqs_data_dly; wire dqs_data_dly;
BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1)); BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1));
BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1)); BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1));
......
...@@ -28,7 +28,7 @@ module test_dqs04( ...@@ -28,7 +28,7 @@ module test_dqs04(
input clk_ref_in, input clk_ref_in,
input rst, input rst,
output dqs_received, output dqs_received,
input dqs_tri, // input dqs_tri,
output dly_ready, output dly_ready,
input [4:0] dly_data, input [4:0] dly_data,
......
...@@ -44,7 +44,7 @@ assign dly_ready= dly_ready_0 && dqs_data; ...@@ -44,7 +44,7 @@ assign dly_ready= dly_ready_0 && dqs_data;
wire d_ser; wire d_ser;
wire dqs_tri1; wire dqs_tri1;
wire d_tri; //wire d_tri;
BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1)); BUFR #(.BUFR_DIVIDE("2")) clk_div_i (.I(clk_in),.O(clk_div),.CLR(rst), .CE(1'b1));
BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1)); BUFR #(.BUFR_DIVIDE("BYPASS")) clk_i (.I(clk_in),.O(clk), .CLR(1'b0),.CE(1'b1));
...@@ -65,9 +65,10 @@ BUFG ref_clk_i (.I(clk_ref_in),.O(clk_ref)); ...@@ -65,9 +65,10 @@ BUFG ref_clk_i (.I(clk_ref_in),.O(clk_ref));
.TBYTE_SRC ("FALSE") .TBYTE_SRC ("FALSE")
) oserdes_i ( ) oserdes_i (
.OFB (d_ser), .OFB (d_ser),
.OQ (), // dout_iob), .OQ (),
.SHIFTOUT1 (), .SHIFTOUT1 (),
.SHIFTOUT2 (), .SHIFTOUT2 (),
.TFB (),
// .TFB (d_tri), // .TFB (d_tri),
// .TQ (dqs_tri1), // .TQ (dqs_tri1),
.TQ (), .TQ (),
......
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