parameterWBUF_DELAY_REL_MASK='h3ff,// address mask to set extra delay
// parameter EXTRA_ADDR = 'h824, // address to set extra parameters (currently just inv_clk_div)
parameterPAGES_REL='h023,// address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
// parameter EXTRA_ADDR_MASK = 'hbff // address mask for extra parameters
parameterPAGES_REL_MASK='h3ff,// address mask to set DQM and DQS patterns
parameterCMDA_EN_REL='h024,// address to enable('h823)/disable('h822) command/address outputs
parameterDLY_LD_REL='h080,// address to generate delay load
parameterCMDA_EN_REL_MASK='h3fe,// address mask for command/address outputs
parameterDLY_LD_REL_MASK='h380,// address mask to generate delay load
parameterSDRST_ACT_REL='h026,// address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory
parameterDLY_SET_REL='h070,// address to generate delay set
parameterSDRST_ACT_REL_MASK='h3fe,// address mask for reset DDR3
parameterDLY_SET_REL_MASK='h3ff,// address mask to generate delay set
parameterCKE_EN_REL='h028,// address to enable('h827)/disable('h826) CKE signal to memory
parameterRUN_CHN_REL='h000,// address to set sequnecer channel and run (4 LSB-s - channel)
parameterCKE_EN_REL_MASK='h3fe,// address mask for command/address outputs
parameterRUN_CHN_REL_MASK='h3f0,// address mask to generate sequencer channel/run
parameterEXTRA_REL='h02a,// address to set extra parameters (currently just inv_clk_div)
parameterPATTERNS_REL='h020,// address to set DQM and DQS patterns (16'h0055)
parameterEXTRA_REL_MASK='h3ff// address mask for extra parameters
parameterPATTERNS_REL_MASK='h3ff,// address mask to set DQM and DQS patterns
parameterPAGES_REL='h021,// address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
parameterPAGES_REL_MASK='h3ff,// address mask to set DQM and DQS patterns
parameterCMDA_EN_REL='h022,// address to enable('h823)/disable('h822) command/address outputs
parameterCMDA_EN_REL_MASK='h3fe,// address mask for command/address outputs
parameterSDRST_ACT_REL='h024,// address to activate('h825)/deactivate('h8242) active-low reset signal to DDR3 memory
parameterSDRST_ACT_REL_MASK='h3fe,// address mask for reset DDR3
parameterCKE_EN_REL='h026,// address to enable('h827)/disable('h826) CKE signal to memory
parameterCKE_EN_REL_MASK='h3fe,// address mask for command/address outputs
parameterEXTRA_REL='h028,// address to set extra parameters (currently just inv_clk_div)
parameterEXTRA_REL_MASK='h3ff// address mask for extra parameters
)(
)(
inputclk,
inputclk,
inputmclk,
inputmclk,
...
@@ -96,6 +78,11 @@ module ddrc_control #(
...
@@ -96,6 +78,11 @@ module ddrc_control #(
outputinv_clk_div,// invert clk_div to ISERDES
outputinv_clk_div,// invert clk_div to ISERDES
output[7:0]dqs_pattern,// DQS pattern during write (normally 8'h55)
output[7:0]dqs_pattern,// DQS pattern during write (normally 8'h55)
output[7:0]dqm_pattern,// DQM pattern (just for testing, should be 8'h0)
output[7:0]dqm_pattern,// DQM pattern (just for testing, should be 8'h0)
output[3:0]dq_tri_on_pattern,
output[3:0]dq_tri_off_pattern,
output[3:0]dqs_tri_on_pattern,
output[3:0]dqs_tri_off_pattern,
output[3:0]wbuf_delay,
// control: buffers pages
// control: buffers pages
output[1:0]port0_page,// port 0 buffer read page (to be controlled by arbiter later, set to 2'b0)
output[1:0]port0_page,// port 0 buffer read page (to be controlled by arbiter later, set to 2'b0)
output[1:0]port0_int_page,// port 0 PHY-side write to buffer page (to be controlled by arbiter later, set to 2'b0)
output[1:0]port0_int_page,// port 0 PHY-side write to buffer page (to be controlled by arbiter later, set to 2'b0)
...
@@ -103,6 +90,13 @@ module ddrc_control #(
...
@@ -103,6 +90,13 @@ module ddrc_control #(
output[1:0]port1_int_page// port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0)
output[1:0]port1_int_page// port 1 PHY-side buffer read page (to be controlled by arbiter later, set to 2'b0)
);
);
localparamDQSTRI_FIRST=4'h3;// DQS tri-state control word, first when enabling output
localparamDQSTRI_LAST=4'hc;// DQS tri-state control word, first after disabling output
localparamDQTRI_FIRST=4'h7;// DQ tri-state control word, first when enabling output
localparamDQTRI_LAST=4'he;// DQ tri-state control word, first after disabling output
localparamWBUF_DLY_DFLT=4'h6;// extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
localparamDLY_LD_ADDR=CONTROL_ADDR|DLY_LD_REL;// address to generate delay load
localparamDLY_LD_ADDR=CONTROL_ADDR|DLY_LD_REL;// address to generate delay load
localparamDLY_LD_ADDR_MASK=CONTROL_ADDR_MASK|DLY_LD_REL_MASK;// address mask to generate delay load
localparamDLY_LD_ADDR_MASK=CONTROL_ADDR_MASK|DLY_LD_REL_MASK;// address mask to generate delay load
localparamDLY_SET_ADDR=CONTROL_ADDR|DLY_SET_REL;// address to generate delay set
localparamDLY_SET_ADDR=CONTROL_ADDR|DLY_SET_REL;// address to generate delay set
...
@@ -111,6 +105,12 @@ module ddrc_control #(
...
@@ -111,6 +105,12 @@ module ddrc_control #(
localparamRUN_CHN_ADDR_MASK=CONTROL_ADDR_MASK|RUN_CHN_REL_MASK;// address mask to generate sequencer channel/run
localparamRUN_CHN_ADDR_MASK=CONTROL_ADDR_MASK|RUN_CHN_REL_MASK;// address mask to generate sequencer channel/run
localparamPATTERNS_ADDR=CONTROL_ADDR|PATTERNS_REL;// address to set DQM and DQS patterns (16'h0055)
localparamPATTERNS_ADDR=CONTROL_ADDR|PATTERNS_REL;// address to set DQM and DQS patterns (16'h0055)
localparamPATTERNS_ADDR_MASK=CONTROL_ADDR_MASK|PATTERNS_REL_MASK;// address mask to set DQM and DQS patterns
localparamPATTERNS_ADDR_MASK=CONTROL_ADDR_MASK|PATTERNS_REL_MASK;// address mask to set DQM and DQS patterns
localparamPATTERNS_TRI_ADDR=CONTROL_ADDR|PATTERNS_TRI_REL;//address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
localparamPATTERNS_TRI_ADDR_MASK=CONTROL_ADDR_MASK|PATTERNS_TRI_REL_MASK;// address mask to set DQM and DQS tristate patterns
localparamWBUF_DELAY_ADDR=CONTROL_ADDR|WBUF_DELAY_REL;// extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
localparamWBUF_DELAY_ADDR_MASK=CONTROL_ADDR_MASK|WBUF_DELAY_REL_MASK;// address mask to set extra delay
localparamPAGES_ADDR=CONTROL_ADDR|PAGES_REL;// address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
localparamPAGES_ADDR=CONTROL_ADDR|PAGES_REL;// address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
localparamPAGES_ADDR_MASK=CONTROL_ADDR_MASK|PAGES_REL_MASK;// address mask to set DQM and DQS patterns
localparamPAGES_ADDR_MASK=CONTROL_ADDR_MASK|PAGES_REL_MASK;// address mask to set DQM and DQS patterns
localparamCMDA_EN_ADDR=CONTROL_ADDR|CMDA_EN_REL;// address to enable('h823)/disable('h822) command/address outputs
localparamCMDA_EN_ADDR=CONTROL_ADDR|CMDA_EN_REL;// address to enable('h823)/disable('h822) command/address outputs
