Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393_sata
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393_sata
Commits
f8f4013f
Commit
f8f4013f
authored
Feb 03, 2016
by
Andrey Filippov
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
got first FIS from the SSD
parent
4626e2cd
Changes
3
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
32 additions
and
25 deletions
+32
-25
.project
.project
+17
-17
gtx_wrap.v
host/gtx_wrap.v
+12
-5
link.v
host/link.v
+3
-3
No files found.
.project
View file @
f8f4013f
...
@@ -52,87 +52,87 @@
...
@@ -52,87 +52,87 @@
<link>
<link>
<name>
vivado_logs/VivadoBitstream.log
</name>
<name>
vivado_logs/VivadoBitstream.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-201602021
71857055
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-201602021
94431938
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoOpt.log
</name>
<name>
vivado_logs/VivadoOpt.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-201602021
71857055
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-201602021
94431938
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoOptPhys.log
</name>
<name>
vivado_logs/VivadoOptPhys.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-201602021
71857055
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-201602021
94431938
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoOptPower.log
</name>
<name>
vivado_logs/VivadoOptPower.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-201602021
71857055
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-201602021
94431938
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoPlace.log
</name>
<name>
vivado_logs/VivadoPlace.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-201602021
71857055
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-201602021
94431938
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoRoute.log
</name>
<name>
vivado_logs/VivadoRoute.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-201602021
71857055
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-201602021
94431938
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoSynthesis.log
</name>
<name>
vivado_logs/VivadoSynthesis.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-201602021
71857055
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-201602021
94431938
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoTimimgSummaryReportImplemented.log
</name>
<name>
vivado_logs/VivadoTimimgSummaryReportImplemented.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-201602021
71857055
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-201602021
94431938
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoTimimgSummaryReportSynthesis.log
</name>
<name>
vivado_logs/VivadoTimimgSummaryReportSynthesis.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-201602021
71857055
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-201602021
94431938
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoTimingReportImplemented.log
</name>
<name>
vivado_logs/VivadoTimingReportImplemented.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-201602021
71857055
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-201602021
94431938
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoTimingReportSynthesis.log
</name>
<name>
vivado_logs/VivadoTimingReportSynthesis.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-201602021
71857055
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-201602021
94431938
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_state/x393_sata-opt-phys.dcp
</name>
<name>
vivado_state/x393_sata-opt-phys.dcp
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-201602021
71857055
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-201602021
94431938
.dcp
</location>
</link>
</link>
<link>
<link>
<name>
vivado_state/x393_sata-opt-power.dcp
</name>
<name>
vivado_state/x393_sata-opt-power.dcp
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-201602021
71857055
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-201602021
94431938
.dcp
</location>
</link>
</link>
<link>
<link>
<name>
vivado_state/x393_sata-opt.dcp
</name>
<name>
vivado_state/x393_sata-opt.dcp
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-201602021
71857055
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-201602021
94431938
.dcp
</location>
</link>
</link>
<link>
<link>
<name>
vivado_state/x393_sata-place.dcp
</name>
<name>
vivado_state/x393_sata-place.dcp
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-place-201602021
71857055
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-place-201602021
94431938
.dcp
</location>
</link>
</link>
<link>
<link>
<name>
vivado_state/x393_sata-route.dcp
</name>
<name>
vivado_state/x393_sata-route.dcp
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-route-201602021
71857055
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-route-201602021
94431938
.dcp
</location>
</link>
</link>
<link>
<link>
<name>
vivado_state/x393_sata-synth.dcp
</name>
<name>
vivado_state/x393_sata-synth.dcp
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-201602021
71857055
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-201602021
94431938
.dcp
</location>
</link>
</link>
</linkedResources>
</linkedResources>
</projectDescription>
</projectDescription>
host/gtx_wrap.v
View file @
f8f4013f
...
@@ -510,10 +510,12 @@ end
...
@@ -510,10 +510,12 @@ end
wire
txoutclk_gtx
;
wire
txoutclk_gtx
;
wire
xclk_gtx
;
wire
xclk_gtx
;
wire
xclk_mr
;
//
wire xclk_mr;
BUFG
bufg_txoutclk
(
.
O
(
txoutclk
)
,.
I
(
txoutclk_gtx
))
;
BUFG
bufg_txoutclk
(
.
O
(
txoutclk
)
,.
I
(
txoutclk_gtx
))
;
BUFR
bufr_xclk
(
.
O
(
xclk
)
,.
I
(
xclk_mr
)
,.
CE
(
1'b1
)
,.
CLR
(
1'b0
))
;
//BUFR bufr_xclk (.O(xclk),.I(xclk_mr),.CE(1'b1),.CLR(1'b0));
BUFMR
bufmr_xclk
(
.
O
(
xclk_mr
)
,.
I
(
xclk_gtx
))
;
//BUFMR bufmr_xclk (.O(xclk_mr),.I(xclk_gtx));
BUFG
bug_xclk
(
.
O
(
xclk
)
,.
I
(
xclk_gtx
))
;
gtxe2_channel_wrapper
#(
gtxe2_channel_wrapper
#(
.
SIM_RECEIVER_DETECT_PASS
(
"TRUE"
)
,
.
SIM_RECEIVER_DETECT_PASS
(
"TRUE"
)
,
...
@@ -777,8 +779,13 @@ gtxe2_channel_wrapper(
...
@@ -777,8 +779,13 @@ gtxe2_channel_wrapper(
.
RXCDRRESETRSV
(
1'b0
)
,
.
RXCDRRESETRSV
(
1'b0
)
,
.
RXCLKCORCNT
()
,
.
RXCLKCORCNT
()
,
.
RX8B10BEN
(
1'b0
)
,
.
RX8B10BEN
(
1'b0
)
,
.
RXUSRCLK
(
rxusrclk
)
,
.
RXUSRCLK2
(
rxusrclk
)
,
/// .RXUSRCLK (rxusrclk),
/// .RXUSRCLK2 (rxusrclk),
/// When internal elastic buffer is bypassed, these clocks should be restored clock synchronous
.
RXUSRCLK
(
xclk
)
,
.
RXUSRCLK2
(
xclk
)
,
.
RXDATA
(
rxdata_gtx
)
,
.
RXDATA
(
rxdata_gtx
)
,
.
RXPRBSERR
()
,
.
RXPRBSERR
()
,
.
RXPRBSSEL
(
3'd0
)
,
.
RXPRBSSEL
(
3'd0
)
,
...
...
host/link.v
View file @
f8f4013f
...
@@ -854,11 +854,11 @@ end
...
@@ -854,11 +854,11 @@ end
///assign debug_out[31:20] = debug_num_other[11:0];
///assign debug_out[31:20] = debug_num_other[11:0];
///assign debug_out = debug_unknown_dword; // first unknown dword
///assign debug_out = debug_unknown_dword; // first unknown dword
//
assign debug_out[15: 0] = debug_to_first_err[19:4];
assign
debug_out
[
15
:
0
]
=
debug_to_first_err
[
19
:
4
]
;
//
assign debug_out[31:16] = debug_rcvd_dword;
assign
debug_out
[
31
:
16
]
=
debug_rcvd_dword
;
assign
debug_out
[
STATES_COUNT
-
1
:
0
]
=
debug_states_visited
;
//
assign debug_out[STATES_COUNT - 1:0] = debug_states_visited;
/*
/*
//assign debug_out[PRIM_NUM - 1:0] = debug_rcvd_dword;
//assign debug_out[PRIM_NUM - 1:0] = debug_rcvd_dword;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment