Commit 4626e2cd authored by Andrey Filippov's avatar Andrey Filippov
Browse files

hardware debugging

parent 57b218aa

.project

+17 −17
Original line number Diff line number Diff line
@@ -52,87 +52,87 @@ 
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			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160201011135425.log</location>

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ahci/ahci_sata_layers.v

+30 −13
Original line number Diff line number Diff line
@@ -107,7 +107,8 @@ module ahci_sata_layers #( 
    localparam H2D_TYPE_FIS_HEAD = 1;

    localparam H2D_TYPE_FIS_LAST = 2;

    

    wire               phy_ready;

    wire               phy_ready;        // active when GTX gets aligned output

    wire               link_established; // Received 3 back-to-back non-ALIGNp 

    wire        [31:0] ll_h2d_data_in;

    wire         [1:0] ll_h2d_mask_in;

    wire               ll_strobe_out;
@@ -168,9 +169,18 @@ module ahci_sata_layers #( 
    wire                           d2h_fifo_wr = ll_d2h_valid || fis_over_r; // fis_over_r will push FIS end to FIFO

    reg                            h2d_pending;    // HBA started sending FIS to fifo

    

    assign ll_h2d_last =  (h2d_type_out == H2D_TYPE_FIS_LAST); 

    wire                    [31:0] debug_phy;

    wire                    [31:0] debug_link;

    

    wire debug_detected_alignp; // oob detects ALIGNp, but not the link layer

    

    

//    assign debug_sata = {link_established, phy_ready, debug_phy[29:16],debug_link[15:0]}; // 

    assign debug_sata = debug_link[31:0]; // 

///    assign debug_sata = debug_phy;

    

    

    assign ll_h2d_last =  (h2d_type_out == H2D_TYPE_FIS_LAST); 

    assign d2h_valid = d2h_nempty;

    assign d2h_many =  |d2h_fill[FIFO_ADDR_WIDTH:3]; //
@@ -180,15 +190,21 @@ module ahci_sata_layers #( 
//    assign ll_frame_req_w = !ll_frame_busy && h2d_pending && (((h2d_type == H2D_TYPE_FIS_LAST) && h2d_fifo_wr ) || (|h2d_fill[FIFO_ADDR_WIDTH : BITS_TO_START_XMIT]));

// Separating different types of errors, sync_escape from other problems. TODO: route individual errors to set SERR bits

//assign  incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr_data   & dword_val &  rcvd_dword[CODE_WTRMP];

    assign phy_speed = phy_ready ? PHY_SPEED:0;



    assign serr_DB = phy_ready && (|ph2ll_err_out);

    assign serr_DH = phy_ready && (xmit_err);

//    assign phy_speed = phy_ready ? PHY_SPEED:0;

//    assign serr_DB = phy_ready && (|ph2ll_err_out);

//    assign serr_DH = phy_ready && (xmit_err);

    assign phy_speed = link_established ? PHY_SPEED:0;

    assign serr_DB =   link_established && (|ph2ll_err_out);

    assign serr_DH =   link_established && (xmit_err);

    //

    

// not yet assigned errors

    assign serr_DT = phy_ready && (comreset_send); // RWC: Transport state transition error

    assign serr_DS = phy_ready && (cominit_got);   // RWC: Link sequence error

    assign serr_DC = phy_ready && (serr_DW);       // RWC: CRC error in Link layer

///    assign serr_DT = phy_ready && (comreset_send); // RWC: Transport state transition error

///    assign serr_DS = phy_ready && (cominit_got);   // RWC: Link sequence error

///    assign serr_DC = phy_ready && (serr_DW);       // RWC: CRC error in Link layer

    assign serr_DT = phy_ready && (0); // RWC: Transport state transition error

    assign serr_DS = phy_ready && (0);   // RWC: Link sequence error

    assign serr_DC = phy_ready && (0);       // RWC: CRC error in Link layer

//    assign serr_DB = phy_ready && (0);   // RWC: 10B to 8B decode error

    assign serr_DI = phy_ready && (0);   // RWC: PHY Internal Error

    assign serr_EP = phy_ready && (0);   // RWC: Protocol Error - a violation of SATA protocol detected
@@ -239,6 +255,7 @@ module ahci_sata_layers #( 
        .sync_escape_req  (syncesc_send),          // input wire  // TL demands to brutally cancel current transaction

        .sync_escape_ack  (syncesc_send_done),     // output wire // acknowlegement of a successful reception?

        .incom_stop_req   (pcmd_st_cleared),          // input wire  // TL demands to stop current recieving session

        .link_established (link_established),

        // inputs from phy

        .phy_ready        (phy_ready),             // input wire        // phy is ready - link is established

        // data-primitives stream from phy
@@ -247,7 +264,8 @@ module ahci_sata_layers #( 
        .phy_err_in       (ph2ll_err_out),         // input[3:0] wire   // disperr | notintable

        // to phy

        .phy_data_out     (ll2ph_data_in),         // output[31:0] wire 

        .phy_isk_out      (ll2ph_charisk_in)       // output[3:0] wire   // charisk

        .phy_isk_out      (ll2ph_charisk_in),       // output[3:0] wire   // charisk

        .debug_out        (debug_link)

    );

    

    always @ (posedge clk) begin
@@ -304,9 +322,8 @@ module ahci_sata_layers #( 
        .comwake_got     (serr_DW),            // output wire 

        .cplllock_debug  (),

        .usrpll_locked_debug(),

        .debug_sata      (debug_sata)  

        

        

        .debug_sata      (debug_phy)  

        ,.debug_detected_alignp(debug_detected_alignp)

    );



    fifo_sameclock_control #(

ahci/ahci_top.v

+2 −1
Original line number Diff line number Diff line
@@ -690,7 +690,8 @@ module ahci_top#( 
        .afi_cache_set    (set_axi_cache_mode), // output

        .was_hba_rst      (was_hba_rst),     // output 

        .was_port_rst     (was_port_rst),     // output 

        .debug_in         ({2'b0, last_jump_addr[9:0], debug_in[19:0]})

//        .debug_in         ({2'b0, last_jump_addr[9:0], debug_in[19:0]})

        .debug_in         (debug_in[31:0])

    );

    ahci_ctrl_stat #(

        .ADDRESS_BITS            (ADDRESS_BITS)

device/sata_device.v

+24 −1
Original line number Diff line number Diff line
@@ -60,6 +60,24 @@ reg [31:0] dev2phy_data = 32'hB5B5957C; // SYNCP 
reg     [3:0]   dev2phy_isk     = 4'h1;



reg     [2:0]   phy_ready_syncp_r;  // allow device to send 3 SYNCp before getting ready

reg     [4:0]   serial_delay = 7;  // delay output to check host alignment



localparam DEV_ALIGN_PERIOD = 32; // make it more frequent than 250

//integer    align_cntr = DEV_ALIGN_PERIOD;

reg     [7:0]  align_cntr = DEV_ALIGN_PERIOD;

initial forever @ (posedge clk) begin

    if (align_cntr > 0) align_cntr = align_cntr - 1;

end



task send_align_pair_if_needed;

    if (align_cntr ==0) begin

        dev2phy_data    <= PRIM_ALIGNP;

        dev2phy_isk     <= 4'h1;

        align_cntr = DEV_ALIGN_PERIOD;

        @ (posedge clk);

        @ (posedge clk);

    end

endtask    



sata_phy_dev phy(

    // pll reset
@@ -84,7 +102,9 @@ sata_phy_dev phy( 
    .ll_err_out         (phy2dev_err),



    .ll_data_in         (dev2phy_data),

    .ll_charisk_in      (dev2phy_isk)

    .ll_charisk_in      (dev2phy_isk),

    .serial_delay       (serial_delay) // delay output to check host alignment

    

);



localparam [31:0] PRIM_SYNCP    = {3'd5, 5'd21, 3'd5, 5'd21, 3'd4, 5'd21, 3'd3, 5'd28};
@@ -1186,6 +1206,7 @@ endfunction 
task linkSendData;

    input [31:0] data;

    begin

        send_align_pair_if_needed;

        dev2phy_data    <= data;

        dev2phy_isk     <= 4'h0;

    end
@@ -1198,9 +1219,11 @@ endtask 
task linkSendPrim;

    input [111:0] type;

    begin

//        send_align_pair_if_needed;

        case (type)

            "SYNC": 

            begin

                send_align_pair_if_needed;            

                dev2phy_data    <= PRIM_SYNCP;

                dev2phy_isk     <= 4'h1;

            end

device/sata_phy_dev.v

+19 −3
Original line number Diff line number Diff line
@@ -62,7 +62,10 @@ module sata_phy_dev #( 


    // from link layer

    input   wire    [31:0]  ll_data_in,

    input   wire    [3:0]   ll_charisk_in

    input   wire    [3:0]   ll_charisk_in,

    

    input           [4:0]  serial_delay // delay output to check host alignment



);



wire    [31:0]  txdata;
@@ -739,6 +742,15 @@ gtx_wrapper( 
    .TXSYNCALLIN                    (1'b0),

    .TXSYNCIN                       (1'b0)*/

);

// Serial data bit shift to check host alignment

wire tx_serial_clk=gtx_wrapper.gtx_gpl.channel.tx_serial_clk;

//reg  [4:0] serial_delay = 0;

reg [31:0] txp_r;

reg [31:0] txn_r;

always @(posedge tx_serial_clk) begin

    txp_r = {txp_r[30:0],txp};

    txn_r = {txn_r[30:0],txn};

end



// align to 4-byte boundary

reg twobytes_shift;
@@ -761,8 +773,12 @@ assign drpclk = gtrefclk; 
assign  clk             = usrclk2;

assign  rxn             = rxn_in;

assign  rxp             = rxp_in;

assign  txn_out         = txn;

assign  txp_out         = txp;



///assign  txn_out         = txn;

///assign  txp_out         = txp;

assign  txn_out         = txn_r[serial_delay];

assign  txp_out         = txp_r[serial_delay];



//assign  ll_data_out     = rxdata_out;

//assign  ll_charisk_out  = rxcharisk_out;

//assign  txdata_in       = ll_data_in;