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Commit f5b1c7a6 authored by Andrey Filippov's avatar Andrey Filippov
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driver debugging

parent 8ce6dc0e
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.project
View file @ f5b1c7a6
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160223233437781.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160227133528220.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160223233437781.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160227133528220.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160223233437781.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160227133528220.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160223233437781.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160227133528220.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160223233437781.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160227133528220.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160223233437781.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160227133528220.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160223232408227.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160227133414136.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160223233437781.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160227133528220.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160223232408227.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160227133414136.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160223233437781.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160227133528220.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160223232408227.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160227133414136.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160223233437781.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160227133528220.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160223233437781.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160227133528220.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160223233437781.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160227133528220.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160223233437781.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160227133528220.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-route.dcp</name> <name>vivado_state/x393_sata-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160223233437781.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160227133528220.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160223232408227.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160227133414136.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ahci/ahci_ctrl_stat.v
View file @ f5b1c7a6
...@@ -60,7 +60,7 @@ module ahci_ctrl_stat #( ...@@ -60,7 +60,7 @@ module ahci_ctrl_stat #(
/// input st_pending_reset,// reset both st01_pending and st10_pending /// input st_pending_reset,// reset both st01_pending and st10_pending
// PxCMD // PxCMD
input pcmd_clear_icc, // clear PxCMD.ICC field // input pcmd_clear_icc, // clear PxCMD.ICC field (generated here)
input pcmd_esp, // external SATA port (just forward value) input pcmd_esp, // external SATA port (just forward value)
output pcmd_cr, // command list run - current output pcmd_cr, // command list run - current
input pcmd_cr_set, // command list run set input pcmd_cr_set, // command list run set
...@@ -225,7 +225,12 @@ module ahci_ctrl_stat #( ...@@ -225,7 +225,12 @@ module ahci_ctrl_stat #(
wire [ 3:0] sssts_det = ({4{ssts_det_dnp}} & 4'h1) | wire [ 3:0] sssts_det = ({4{ssts_det_dnp}} & 4'h1) |
({4{ssts_det_dp}} & 4'h3) | ({4{ssts_det_dp}} & 4'h3) |
({4{ssts_det_offline}} & 4'h4); ({4{ssts_det_offline}} & 4'h4);
reg pcmd_clear_icc_r;
wire pcmd_clear_icc = !pcmd_clear_icc_r &&
((PxCMD_r & HBA_PORT__PxCMD__ICC__MASK) == 32'h10000000) &&
((PxSSTS_r & HBA_PORT__PxSSTS__IPM__MASK) == 12'h100) ;
// PxSSTS_r[11:8] HBA_PORT__PxSSTS__IPM__MASK ;
// to update only HBA/async changed bits (not by the software) // to update only HBA/async changed bits (not by the software)
wire set_ssts_ipm = ssts_ipm_dnp || ssts_ipm_active || ssts_ipm_part || ssts_ipm_slumb || ssts_ipm_devsleep; wire set_ssts_ipm = ssts_ipm_dnp || ssts_ipm_active || ssts_ipm_part || ssts_ipm_slumb || ssts_ipm_devsleep;
...@@ -377,6 +382,10 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; ...@@ -377,6 +382,10 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
assign pcmd_cr = PxCMD_r[15]; // command list run - current assign pcmd_cr = PxCMD_r[15]; // command list run - current
assign pcmd_clo = PxCMD_r[3]; // causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit assign pcmd_clo = PxCMD_r[3]; // causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit
assign pcmd_st = PxCMD_r[0]; // current value assign pcmd_st = PxCMD_r[0]; // current value
always @(posedge mclk) begin
pcmd_clear_icc_r <=pcmd_clear_icc;
end
always @(posedge mclk) begin // Here we do not have data written by soft, only the result (cleared). If bit is 0, it is always @(posedge mclk) begin // Here we do not have data written by soft, only the result (cleared). If bit is 0, it is
// either cleared, or was 0. If it was 0, then IS bit was also 0, so clearing will not hurt. // either cleared, or was 0. If it was 0, then IS bit was also 0, so clearing will not hurt.
......
ahci/ahci_top.v
View file @ f5b1c7a6
...@@ -809,7 +809,7 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0] ...@@ -809,7 +809,7 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0]
.update_pci (1'b0), // update_HBA_PORT__PxCI), // input .update_pci (1'b0), // update_HBA_PORT__PxCI), // input
.update_ghc (1'b0), // update _GHC_GHC, // input .update_ghc (1'b0), // update _GHC_GHC, // input
.pcmd_clear_icc (1'b0), // pcmd_clear_icc), // input // .pcmd_clear_icc (1'b0), // pcmd_clear_icc), // input
.pcmd_esp (pcmd_esp), // input .pcmd_esp (pcmd_esp), // input
.pcmd_cr (), //pcmd_cr), // output .pcmd_cr (), //pcmd_cr), // output
.pcmd_cr_set (pcmd_cr_set), // input .pcmd_cr_set (pcmd_cr_set), // input
......
py393sata/x393sata.py
View file @ f5b1c7a6
...@@ -45,7 +45,7 @@ SI5338_PATH_OLD = '/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070' ...@@ -45,7 +45,7 @@ SI5338_PATH_OLD = '/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070'
MEM_PATH_OLD = '/sys/devices/elphel393-mem.2/' MEM_PATH_OLD = '/sys/devices/elphel393-mem.2/'
#new System #new System
SI5338_PATH_NEW = '/sys/devices/soc0/amba@0/e0004000.ps7-i2c/i2c-0/0-0070' SI5338_PATH_NEW = '/sys/devices/soc0/amba@0/e0004000.ps7-i2c/i2c-0/0-0070'
MEM_PATH_NEW = '/sys/devices/soc0/elphel393-mem@0/' MEM_PATH_NEW = ''
DEFAULT_BITFILE="/usr/local/verilog/x393_sata.bit" DEFAULT_BITFILE="/usr/local/verilog/x393_sata.bit"
BUFFER_ADDRESS_NAME = 'buffer_address' BUFFER_ADDRESS_NAME = 'buffer_address'
......
tb/tb_ahci.tf
View file @ f5b1c7a6
...@@ -1179,6 +1179,13 @@ initial begin //Host ...@@ -1179,6 +1179,13 @@ initial begin //Host
maxigp1_print (PXSIG_OFFS32 << 2,"PXSIG_OFFS32"); maxigp1_print (PXSIG_OFFS32 << 2,"PXSIG_OFFS32");
maxigp1_print (PXTFD_OFFS32 << 2,"PXTFD_OFFS32"); maxigp1_print (PXTFD_OFFS32 << 2,"PXTFD_OFFS32");
maxigp1_print (HBA_PORT__PxSERR__DIAG__X__ADDR,"HBA_PORT__PxSERR__DIAG__X__ADDR"); maxigp1_print (HBA_PORT__PxSERR__DIAG__X__ADDR,"HBA_PORT__PxSERR__DIAG__X__ADDR");
// Request ACTIVE, see it will be cleared
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, 32'h10000000); //
repeat (3) begin
maxigp1_print (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__ after ACTIVE request");
end
maxigp1_print (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__FRE__ADDR"); maxigp1_print (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__FRE__ADDR");
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, some RO bits already set maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, some RO bits already set
maxigp1_print (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__FRE__ADDR"); maxigp1_print (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__FRE__ADDR");
......
tb_ahci_01.sav
View file @ f5b1c7a6
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Tue Feb 23 00:04:34 2016 [*] Sat Feb 27 20:28:49 2016
[*] [*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160222150448690.fst" [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160227132249405.fst"
[dumpfile_mtime] "Mon Feb 22 22:05:55 2016" [dumpfile_mtime] "Sat Feb 27 20:25:12 2016"
[dumpfile_size] 7768068 [dumpfile_size] 14933340
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 35797800 [timestart] 27691200
[size] 1823 1173 [size] 1823 1173
[pos] 2026 0 [pos] 2026 0
*-15.135801 35895886 62346574 72998842 74025406 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-17.135801 28083334 62346574 72998842 74025406 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci. [treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr. [treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.linkMonitorFIS. [treeopen] tb_ahci.dev.linkMonitorFIS.
...@@ -1159,7 +1159,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tfd_err[7:0] ...@@ -1159,7 +1159,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tfd_err[7:0]
-ahci_fis_receive -ahci_fis_receive
@1401200 @1401200
-ahci_top -ahci_top
@c00200 @800200
-ahci_ctrl_stat -ahci_ctrl_stat
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_addr[9:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_addr[9:0]
...@@ -1456,6 +1456,48 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq_changed ...@@ -1456,6 +1456,48 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.sirq_changed
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.irq tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.irq
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.GHC_r[1:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.GHC_r[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_GHC_GHC tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_GHC_GHC
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxCMD_r[31:0]
@1401200
-group_end
@23
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxSSTS_r[11:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pcmd_clear_icc
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pcmd_clear_icc_r
@c00200 @c00200
-ssts -ssts
@c00022 @c00022
...@@ -1490,6 +1532,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen2 ...@@ -1490,6 +1532,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen2
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen3 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen3
@1401200 @1401200
-ssts -ssts
@1000200
-ahci_ctrl_stat -ahci_ctrl_stat
@c00200 @c00200
-axi_ahci_regs -axi_ahci_regs
...@@ -1587,7 +1630,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g ...@@ -1587,7 +1630,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g
-drp -drp
@1401200 @1401200
-axi_ahci_regs -axi_ahci_regs
@800200 @c00200
-ahci_fsm -ahci_fsm
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.hba_arst tb_ahci.dut.sata_top.ahci_top_i.hba_arst
...@@ -1610,7 +1653,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0] ...@@ -1610,7 +1653,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
@1401200 @1401200
-group_end -group_end
@c00023 @c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
@28 @28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
...@@ -1623,7 +1666,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] ...@@ -1623,7 +1666,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] (7)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] (8)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0] (9)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
@1401201 @1401200
-group_end -group_end
@c00022 @c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_data[17:0]
...@@ -1861,7 +1904,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0] ...@@ -1861,7 +1904,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1000200 @1401200
-ahci_fsm -ahci_fsm
@c00200 @c00200
-ahci_fis_receive -ahci_fis_receive
......
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