Commit f5b1c7a6 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

driver debugging

parent 8ce6dc0e

.project

+17 −17
Original line number Diff line number Diff line
@@ -52,87 +52,87 @@ 
		<link>

			<name>vivado_logs/VivadoBitstream.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160223233437781.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160227133528220.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOpt.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160223233437781.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160227133528220.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPhys.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160223233437781.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160227133528220.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoOptPower.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160223233437781.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160227133528220.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoPlace.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160223233437781.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160227133528220.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoRoute.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160223233437781.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160227133528220.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160223232408227.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160227133414136.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160223233437781.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160227133528220.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160223232408227.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160227133414136.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportImplemented.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160223233437781.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160227133528220.log</location>

		</link>

		<link>

			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160223232408227.log</location>

			<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160227133414136.log</location>

		</link>

		<link>

			<name>vivado_state/x393_sata-opt-phys.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160223233437781.dcp</location>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160227133528220.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393_sata-opt-power.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160223233437781.dcp</location>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160227133528220.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393_sata-opt.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160223233437781.dcp</location>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160227133528220.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393_sata-place.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160223233437781.dcp</location>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160227133528220.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393_sata-route.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160223233437781.dcp</location>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160227133528220.dcp</location>

		</link>

		<link>

			<name>vivado_state/x393_sata-synth.dcp</name>

			<type>1</type>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160223232408227.dcp</location>

			<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160227133414136.dcp</location>

		</link>

	</linkedResources>

</projectDescription>

ahci/ahci_ctrl_stat.v

+11 −2
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ module ahci_ctrl_stat #( 
///    input                         st_pending_reset,// reset both st01_pending and st10_pending



// PxCMD

    input                         pcmd_clear_icc, // clear PxCMD.ICC field

//    input                         pcmd_clear_icc, // clear PxCMD.ICC field (generated here)

    input                         pcmd_esp,       // external SATA port (just forward value)

    output                        pcmd_cr,        // command list run - current

    input                         pcmd_cr_set,    // command list run set
@@ -226,6 +226,11 @@ module ahci_ctrl_stat #( 
                                              ({4{ssts_det_dp}} &       4'h3) |

                                              ({4{ssts_det_offline}} &  4'h4);



    reg                   pcmd_clear_icc_r; 

    wire                  pcmd_clear_icc = !pcmd_clear_icc_r &&

                                           ((PxCMD_r & HBA_PORT__PxCMD__ICC__MASK) == 32'h10000000) &&

                                           ((PxSSTS_r & HBA_PORT__PxSSTS__IPM__MASK) == 12'h100) ;

   // PxSSTS_r[11:8]     HBA_PORT__PxSSTS__IPM__MASK                                   ;

    // to update only HBA/async changed bits (not by the software)



    wire  set_ssts_ipm = ssts_ipm_dnp || ssts_ipm_active || ssts_ipm_part || ssts_ipm_slumb || ssts_ipm_devsleep;
@@ -378,6 +383,10 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; 
    assign pcmd_clo = PxCMD_r[3];   // causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit

    assign pcmd_st =  PxCMD_r[0];   // current value

    

    always @(posedge mclk) begin 

        pcmd_clear_icc_r <=pcmd_clear_icc;

    end

                       

    always @(posedge mclk) begin // Here we do not have data written by soft, only the result (cleared). If bit is 0, it is

                                 // either cleared, or was 0. If it was 0, then IS bit was also 0, so clearing will not hurt.

        cirq_PRC <= swr_HBA_PORT__PxSERR && |(~soft_write_data & HBA_PORT__PxSERR__DIAG__N__MASK);

ahci/ahci_top.v

+1 −1
Original line number Diff line number Diff line
@@ -809,7 +809,7 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0] 
        .update_pci              (1'b0), // update_HBA_PORT__PxCI),   // input

        .update_ghc              (1'b0), // update _GHC_GHC,          // input

        

        .pcmd_clear_icc          (1'b0), // pcmd_clear_icc),          // input

//        .pcmd_clear_icc          (1'b0), // pcmd_clear_icc),          // input

        .pcmd_esp                (pcmd_esp),                // input

        .pcmd_cr                 (), //pcmd_cr),                 // output

        .pcmd_cr_set             (pcmd_cr_set),             // input

py393sata/x393sata.py

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ SI5338_PATH_OLD = '/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070' 
MEM_PATH_OLD =      '/sys/devices/elphel393-mem.2/'

#new System

SI5338_PATH_NEW =   '/sys/devices/soc0/amba@0/e0004000.ps7-i2c/i2c-0/0-0070'

MEM_PATH_NEW =      '/sys/devices/soc0/elphel393-mem@0/'

MEM_PATH_NEW =      ''



DEFAULT_BITFILE="/usr/local/verilog/x393_sata.bit"

BUFFER_ADDRESS_NAME = 'buffer_address'

tb/tb_ahci.tf

+7 −0
Original line number Diff line number Diff line
@@ -1179,6 +1179,13 @@ initial begin //Host 
    maxigp1_print        (PXSIG_OFFS32 << 2,"PXSIG_OFFS32");

    maxigp1_print        (PXTFD_OFFS32 << 2,"PXTFD_OFFS32");

    maxigp1_print        (HBA_PORT__PxSERR__DIAG__X__ADDR,"HBA_PORT__PxSERR__DIAG__X__ADDR");

    

// Request ACTIVE, see it will be cleared

    maxigp1_writep       (HBA_PORT__PxCMD__FRE__ADDR << 2, 32'h10000000); //

    repeat (3) begin  

        maxigp1_print        (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__ after ACTIVE request");

    end

    

    maxigp1_print        (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__FRE__ADDR");

    maxigp1_writep       (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, some RO bits already set 

    maxigp1_print        (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__FRE__ADDR");