MAxi clock now sourcing drp and cplllockdetclk (e551876b) · Commits · Elphel / x393_sata

dma/sata_top.v

+6 −0

Original line number	Original line	Diff line number	Diff line
	@@ -32,6 +32,10 @@
	output wire sclk,		output wire sclk,
	output wire sata_rst,		output wire sata_rst,
	input wire extrst,		input wire extrst,

			// reliable clock to source drp and cpll lock det circuits
			input wire reliable_clk,

	/*		/*
	* Commands interface		* Commands interface
	*/		*/
	@@ -605,6 +609,8 @@ sata_host sata_host(
	.rst (sata_rst),		.rst (sata_rst),
	// sata clk		// sata clk
	.clk (sclk),		.clk (sclk),
			// reliable clock to source drp and cpll lock det circuits
			.reliable_clk (reliable_clk),
	// temporary		// temporary
	.al_cmd_in (cmd_out), // == {cmd_type, cmd_port, cmd_val, cmd_done_bad, cmd_done_good; cmd_busy}		.al_cmd_in (cmd_out), // == {cmd_type, cmd_port, cmd_val, cmd_done_bad, cmd_done_good; cmd_busy}
	.al_cmd_val_in (cmd_val_out),		.al_cmd_val_in (cmd_val_out),

+4 −2

Original line number	Original line	Diff line number	Diff line
	@@ -139,8 +139,8 @@ BUFG bufg_axi_aclk0_i (.O(axi_aclk0),.I(fclk[0]));
	BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));		BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
	BUFG bufg_extrst_i (.O(extrst),.I(axi_rst_pre));		BUFG bufg_extrst_i (.O(extrst),.I(axi_rst_pre));
	axi_hp_clk #(		axi_hp_clk #(
	.CLKIN_PERIOD(6.666),		.CLKIN_PERIOD(20.000),
	.CLKFBOUT_MULT_AXIHP(6),		.CLKFBOUT_MULT_AXIHP(18),
	.CLKFBOUT_DIV_AXIHP(6)		.CLKFBOUT_DIV_AXIHP(6)
	) axi_hp_clk_i (		) axi_hp_clk_i (
	.rst (axi_rst), // input		.rst (axi_rst), // input
	@@ -151,6 +151,8 @@ axi_hp_clk #(

	sata_top sata_top(		sata_top sata_top(
	.sclk (sclk),		.sclk (sclk),
			// reliable clock to source drp and cpll lock det circuits
			.reliable_clk (axi_aclk0),
	.sata_rst (sata_rst),		.sata_rst (sata_rst),
	.extrst (extrst),		.extrst (extrst),
	.ACLK (axi_aclk),		.ACLK (axi_aclk),

+7 −0

Original line number	Original line	Diff line number	Diff line
	@@ -29,6 +29,10 @@ module sata_host(
	output wire rst,		output wire rst,
	// sata clk		// sata clk
	output wire clk,		output wire clk,

			// reliable clock to source drp and cpll lock det circuits
			input wire reliable_clk,

	// temporary		// temporary
	input wire [31:0] al_cmd_in, // == {cmd_type, cmd_port, cmd_val, cmd_done_bad, cmd_done_good; cmd_busy}		input wire [31:0] al_cmd_in, // == {cmd_type, cmd_port, cmd_val, cmd_done_bad, cmd_done_good; cmd_busy}
	input wire al_cmd_val_in,		input wire al_cmd_val_in,
	@@ -657,6 +661,9 @@ sata_phy phy(
	// sata clk, generated in pll as usrclk2		// sata clk, generated in pll as usrclk2
	.clk (clk),		.clk (clk),

			// stable clock to source drp and cpll lock det circuits
			.reliable_clk (reliable_clk),

	// state		// state
	.phy_ready (phy_ready),		.phy_ready (phy_ready),

+5 −2

Original line number	Original line	Diff line number	Diff line
	@@ -30,6 +30,9 @@ module sata_phy #(
	output wire clk,		output wire clk,
	output wire rst,		output wire rst,

			// reliable clock to source drp and cpll lock det circuits
			input wire reliable_clk,

	// state		// state
	output wire phy_ready,		output wire phy_ready,

	@@ -370,8 +373,8 @@ gtx_wrap
	/*		/*
	* Interfaces		* Interfaces
	*/		*/
	assign cplllockdetclk = gtrefclk; //TODO		assign cplllockdetclk = reliable_clk; //gtrefclk;
	assign drpclk = gtrefclk;		assign drpclk = reliable_clk; //gtrefclk;

	//assign clk = usrclk2;		//assign clk = usrclk2;
	BUFG bufg_sclk (.O(clk),.I(usrclk2));		BUFG bufg_sclk (.O(clk),.I(usrclk2));

+4 −4

Original line number	Original line	Diff line number	Diff line
	@@ -74,8 +74,8 @@ reg SIMUL_AXI_FULL; // some data available
	wire SIMUL_AXI_EMPTY;		wire SIMUL_AXI_EMPTY;
	reg [31:0] registered_rdata; // here read data from task		reg [31:0] registered_rdata; // here read data from task

	//reg CLK;		reg CLK;
	wire CLK;		//wire CLK;
	reg RST;		reg RST;
	reg AR_SET_CMD_r;		reg AR_SET_CMD_r;
	wire AR_READY;		wire AR_READY;
	@@ -162,12 +162,12 @@ wire #(AXI_TASK_HOLD) AW_SET_CMD = AW_SET_CMD_r;
	wire #(AXI_TASK_HOLD) W_SET_CMD = W_SET_CMD_r;		wire #(AXI_TASK_HOLD) W_SET_CMD = W_SET_CMD_r;

	//always #(CLKIN_PERIOD/2) CLK = ~CLK;		//always #(CLKIN_PERIOD/2) CLK = ~CLK;
	assign CLK = dut.axi_aclk;		//assign CLK = dut.axi_aclk0;

	/*		/*
	* connect axi ports to the dut		* connect axi ports to the dut
	*/		*/
	assign dut.ps7_i.FCLKCLK= {4{EXTCLK_P}};		assign dut.ps7_i.FCLKCLK= {4{CLK}};
	assign dut.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};		assign dut.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};
	// Read address		// Read address
	assign dut.ps7_i.MAXIGP1ARADDR= araddr;		assign dut.ps7_i.MAXIGP1ARADDR= araddr;