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x393_sata
Commit e4816b14 authored by Alexey Grebenkin's avatar Alexey Grebenkin
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Few more changes to make the project synth in vdt enviroment

parent ec00bd28
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Showing with 4317 additions and 26 deletions
ddr3/1024Mb_ddr3_parameters.vh 0 → 120000
View file @ e4816b14
/home/alexey/tmp/sata2/x393/ddr3/1024Mb_ddr3_parameters.vh
\ No newline at end of file
ddr3/2048Mb_ddr3_parameters.vh 0 → 120000
View file @ e4816b14
/home/alexey/tmp/sata2/x393/ddr3/2048Mb_ddr3_parameters.vh
\ No newline at end of file
ddr3/4096Mb_ddr3_parameters.vh 0 → 120000
View file @ e4816b14
/home/alexey/tmp/sata2/x393/ddr3/4096Mb_ddr3_parameters.vh
\ No newline at end of file
dma/sata_top.v
View file @ e4816b14
...@@ -84,7 +84,7 @@ ...@@ -84,7 +84,7 @@
output wire [3:0] afi_awcache, output wire [3:0] afi_awcache,
output wire [2:0] afi_awprot, output wire [2:0] afi_awprot,
output wire [3:0] afi_awlen, output wire [3:0] afi_awlen,
output wire [2:0] afi_awsize, output wire [1:0] afi_awsize,
output wire [1:0] afi_awburst, output wire [1:0] afi_awburst,
output wire [3:0] afi_awqos, output wire [3:0] afi_awqos,
// write data // write data
...@@ -113,7 +113,7 @@ ...@@ -113,7 +113,7 @@
output wire [3:0] afi_arcache, output wire [3:0] afi_arcache,
output wire [2:0] afi_arprot, output wire [2:0] afi_arprot,
output wire [3:0] afi_arlen, output wire [3:0] afi_arlen,
output wire [2:0] afi_arsize, output wire [1:0] afi_arsize,
output wire [1:0] afi_arburst, output wire [1:0] afi_arburst,
output wire [3:0] afi_arqos, output wire [3:0] afi_arqos,
// read data // read data
......
dma/top.v
View file @ e4816b14
...@@ -90,7 +90,7 @@ wire [ 1:0] afi0_awlock; // output[1:0] ...@@ -90,7 +90,7 @@ wire [ 1:0] afi0_awlock; // output[1:0]
wire [ 3:0] afi0_awcache; // output[3:0] wire [ 3:0] afi0_awcache; // output[3:0]
wire [ 2:0] afi0_awprot; // output[2:0] wire [ 2:0] afi0_awprot; // output[2:0]
wire [ 3:0] afi0_awlen; // output[3:0] wire [ 3:0] afi0_awlen; // output[3:0]
wire [ 2:0] afi0_awsize; // output[2:0] wire [ 1:0] afi0_awsize; // output[2:0]
wire [ 1:0] afi0_awburst; // output[1:0] wire [ 1:0] afi0_awburst; // output[1:0]
wire [ 3:0] afi0_awqos; // output[3:0] wire [ 3:0] afi0_awqos; // output[3:0]
wire [63:0] afi0_wdata; // output[63:0] wire [63:0] afi0_wdata; // output[63:0]
...@@ -114,7 +114,7 @@ wire [ 1:0] afi0_arlock; // output[1:0] ...@@ -114,7 +114,7 @@ wire [ 1:0] afi0_arlock; // output[1:0]
wire [ 3:0] afi0_arcache; // output[3:0] wire [ 3:0] afi0_arcache; // output[3:0]
wire [ 2:0] afi0_arprot; // output[2:0] wire [ 2:0] afi0_arprot; // output[2:0]
wire [ 3:0] afi0_arlen; // output[3:0] wire [ 3:0] afi0_arlen; // output[3:0]
wire [ 2:0] afi0_arsize; // output[2:0] wire [ 1:0] afi0_arsize; // output[2:0]
wire [ 1:0] afi0_arburst; // output[1:0] wire [ 1:0] afi0_arburst; // output[1:0]
wire [ 3:0] afi0_arqos; // output[3:0] wire [ 3:0] afi0_arqos; // output[3:0]
wire [63:0] afi0_rdata; // input[63:0] wire [63:0] afi0_rdata; // input[63:0]
......
includes/coring.dat.vh 0 → 100644
View file @ e4816b14
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includes/focus_filt.dat.vh 0 → 100644
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includes/huffman.dat.vh 0 → 100644
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includes/linear1028rgb.dat.vh 0 → 100644
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, .INIT_39 (256'h127C127812741270126C126812641260125C125812541250124C124812441240)
, .INIT_3A (256'h12BC12B812B412B012AC12A812A412A0129C129812941290128C128812841280)
, .INIT_3B (256'h12FC12F812F412F012EC12E812E412E012DC12D812D412D012CC12C812C412C0)
, .INIT_3C (256'h133C133813341330132C132813241320131C131813141310130C130813041300)
, .INIT_3D (256'h137C137813741370136C136813641360135C135813541350134C134813441340)
, .INIT_3E (256'h13BC13B813B413B013AC13A813A413A0139C139813941390138C138813841380)
, .INIT_3F (256'h0FFC13F813F413F013EC13E813E413E013DC13D813D413D013CC13C813C413C0)
, .INIT_40 (256'h103C103810341030102C102810241020101C101810141010100C100810041000)
, .INIT_41 (256'h107C107810741070106C106810641060105C105810541050104C104810441040)
, .INIT_42 (256'h10BC10B810B410B010AC10A810A410A0109C109810941090108C108810841080)
, .INIT_43 (256'h10FC10F810F410F010EC10E810E410E010DC10D810D410D010CC10C810C410C0)
, .INIT_44 (256'h113C113811341130112C112811241120111C111811141110110C110811041100)
, .INIT_45 (256'h117C117811741170116C116811641160115C115811541150114C114811441140)
, .INIT_46 (256'h11BC11B811B411B011AC11A811A411A0119C119811941190118C118811841180)
, .INIT_47 (256'h11FC11F811F411F011EC11E811E411E011DC11D811D411D011CC11C811C411C0)
, .INIT_48 (256'h123C123812341230122C122812241220121C121812141210120C120812041200)
, .INIT_49 (256'h127C127812741270126C126812641260125C125812541250124C124812441240)
, .INIT_4A (256'h12BC12B812B412B012AC12A812A412A0129C129812941290128C128812841280)
, .INIT_4B (256'h12FC12F812F412F012EC12E812E412E012DC12D812D412D012CC12C812C412C0)
, .INIT_4C (256'h133C133813341330132C132813241320131C131813141310130C130813041300)
, .INIT_4D (256'h137C137813741370136C136813641360135C135813541350134C134813441340)
, .INIT_4E (256'h13BC13B813B413B013AC13A813A413A0139C139813941390138C138813841380)
, .INIT_4F (256'h0FFC13F813F413F013EC13E813E413E013DC13D813D413D013CC13C813C413C0)
, .INIT_50 (256'h103C103810341030102C102810241020101C101810141010100C100810041000)
, .INIT_51 (256'h107C107810741070106C106810641060105C105810541050104C104810441040)
, .INIT_52 (256'h10BC10B810B410B010AC10A810A410A0109C109810941090108C108810841080)
, .INIT_53 (256'h10FC10F810F410F010EC10E810E410E010DC10D810D410D010CC10C810C410C0)
, .INIT_54 (256'h113C113811341130112C112811241120111C111811141110110C110811041100)
, .INIT_55 (256'h117C117811741170116C116811641160115C115811541150114C114811441140)
, .INIT_56 (256'h11BC11B811B411B011AC11A811A411A0119C119811941190118C118811841180)
, .INIT_57 (256'h11FC11F811F411F011EC11E811E411E011DC11D811D411D011CC11C811C411C0)
, .INIT_58 (256'h123C123812341230122C122812241220121C121812141210120C120812041200)
, .INIT_59 (256'h127C127812741270126C126812641260125C125812541250124C124812441240)
, .INIT_5A (256'h12BC12B812B412B012AC12A812A412A0129C129812941290128C128812841280)
, .INIT_5B (256'h12FC12F812F412F012EC12E812E412E012DC12D812D412D012CC12C812C412C0)
, .INIT_5C (256'h133C133813341330132C132813241320131C131813141310130C130813041300)
, .INIT_5D (256'h137C137813741370136C136813641360135C135813541350134C134813441340)
, .INIT_5E (256'h13BC13B813B413B013AC13A813A413A0139C139813941390138C138813841380)
, .INIT_5F (256'h0FFC13F813F413F013EC13E813E413E013DC13D813D413D013CC13C813C413C0)
, .INIT_60 (256'h103C103810341030102C102810241020101C101810141010100C100810041000)
, .INIT_61 (256'h107C107810741070106C106810641060105C105810541050104C104810441040)
, .INIT_62 (256'h10BC10B810B410B010AC10A810A410A0109C109810941090108C108810841080)
, .INIT_63 (256'h10FC10F810F410F010EC10E810E410E010DC10D810D410D010CC10C810C410C0)
, .INIT_64 (256'h113C113811341130112C112811241120111C111811141110110C110811041100)
, .INIT_65 (256'h117C117811741170116C116811641160115C115811541150114C114811441140)
, .INIT_66 (256'h11BC11B811B411B011AC11A811A411A0119C119811941190118C118811841180)
, .INIT_67 (256'h11FC11F811F411F011EC11E811E411E011DC11D811D411D011CC11C811C411C0)
, .INIT_68 (256'h123C123812341230122C122812241220121C121812141210120C120812041200)
, .INIT_69 (256'h127C127812741270126C126812641260125C125812541250124C124812441240)
, .INIT_6A (256'h12BC12B812B412B012AC12A812A412A0129C129812941290128C128812841280)
, .INIT_6B (256'h12FC12F812F412F012EC12E812E412E012DC12D812D412D012CC12C812C412C0)
, .INIT_6C (256'h133C133813341330132C132813241320131C131813141310130C130813041300)
, .INIT_6D (256'h137C137813741370136C136813641360135C135813541350134C134813441340)
, .INIT_6E (256'h13BC13B813B413B013AC13A813A413A0139C139813941390138C138813841380)
, .INIT_6F (256'h0FFC13F813F413F013EC13E813E413E013DC13D813D413D013CC13C813C413C0)
, .INIT_70 (256'h103C103810341030102C102810241020101C101810141010100C100810041000)
, .INIT_71 (256'h107C107810741070106C106810641060105C105810541050104C104810441040)
, .INIT_72 (256'h10BC10B810B410B010AC10A810A410A0109C109810941090108C108810841080)
, .INIT_73 (256'h10FC10F810F410F010EC10E810E410E010DC10D810D410D010CC10C810C410C0)
, .INIT_74 (256'h113C113811341130112C112811241120111C111811141110110C110811041100)
, .INIT_75 (256'h117C117811741170116C116811641160115C115811541150114C114811441140)
, .INIT_76 (256'h11BC11B811B411B011AC11A811A411A0119C119811941190118C118811841180)
, .INIT_77 (256'h11FC11F811F411F011EC11E811E411E011DC11D811D411D011CC11C811C411C0)
, .INIT_78 (256'h123C123812341230122C122812241220121C121812141210120C120812041200)
, .INIT_79 (256'h127C127812741270126C126812641260125C125812541250124C124812441240)
, .INIT_7A (256'h12BC12B812B412B012AC12A812A412A0129C129812941290128C128812841280)
, .INIT_7B (256'h12FC12F812F412F012EC12E812E412E012DC12D812D412D012CC12C812C412C0)
, .INIT_7C (256'h133C133813341330132C132813241320131C131813141310130C130813041300)
, .INIT_7D (256'h137C137813741370136C136813641360135C135813541350134C134813441340)
, .INIT_7E (256'h13BC13B813B413B013AC13A813A413A0139C139813941390138C138813841380)
, .INIT_7F (256'h0FFC13F813F413F013EC13E813E413E013DC13D813D413D013CC13C813C413C0)
includes/quantization_100.dat.vh 0 → 100644
View file @ e4816b14
, .INIT_00 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_01 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_02 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_03 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_04 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_05 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_06 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_07 (256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
, .INIT_08 (256'h2000333040005550555040005550555055505550800080005550800080005550)
, .INIT_09 (256'h19A017401550155019A0155020002AB02490249019A033304000400033303330)
, .INIT_0A (256'h0F1010000BA010001740174012500F10125013B010000E40125013B017401740)
, .INIT_0B (256'h0CD00C300CD00E400AB00CD00BA00AB00B20111015500C300C300C300CD00D80)
, .INIT_0C (256'h0CD00CD013B0174013B00CD01C70333033301C70333040003330400040005550)
, .INIT_0D (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
, .INIT_0E (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
, .INIT_0F (256'h0CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD00CD0)
includes/ram18_declare_init.vh 0 → 100644
View file @ e4816b14
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000
includes/ram18_pass_init.vh 0 → 100644
View file @ e4816b14
, .INITP_00 (INITP_00)
, .INITP_01 (INITP_01)
, .INITP_02 (INITP_02)
, .INITP_03 (INITP_03)
, .INITP_04 (INITP_04)
, .INITP_05 (INITP_05)
, .INITP_06 (INITP_06)
, .INITP_07 (INITP_07)
, .INIT_00 (INIT_00)
, .INIT_01 (INIT_01)
, .INIT_02 (INIT_02)
, .INIT_03 (INIT_03)
, .INIT_04 (INIT_04)
, .INIT_05 (INIT_05)
, .INIT_06 (INIT_06)
, .INIT_07 (INIT_07)
, .INIT_08 (INIT_08)
, .INIT_09 (INIT_09)
, .INIT_0A (INIT_0A)
, .INIT_0B (INIT_0B)
, .INIT_0C (INIT_0C)
, .INIT_0D (INIT_0D)
, .INIT_0E (INIT_0E)
, .INIT_0F (INIT_0F)
, .INIT_10 (INIT_10)
, .INIT_11 (INIT_11)
, .INIT_12 (INIT_12)
, .INIT_13 (INIT_13)
, .INIT_14 (INIT_14)
, .INIT_15 (INIT_15)
, .INIT_16 (INIT_16)
, .INIT_17 (INIT_17)
, .INIT_18 (INIT_18)
, .INIT_19 (INIT_19)
, .INIT_1A (INIT_1A)
, .INIT_1B (INIT_1B)
, .INIT_1C (INIT_1C)
, .INIT_1D (INIT_1D)
, .INIT_1E (INIT_1E)
, .INIT_1F (INIT_1F)
, .INIT_20 (INIT_20)
, .INIT_21 (INIT_21)
, .INIT_22 (INIT_22)
, .INIT_23 (INIT_23)
, .INIT_24 (INIT_24)
, .INIT_25 (INIT_25)
, .INIT_26 (INIT_26)
, .INIT_27 (INIT_27)
, .INIT_28 (INIT_28)
, .INIT_29 (INIT_29)
, .INIT_2A (INIT_2A)
, .INIT_2B (INIT_2B)
, .INIT_2C (INIT_2C)
, .INIT_2D (INIT_2D)
, .INIT_2E (INIT_2E)
, .INIT_2F (INIT_2F)
, .INIT_30 (INIT_30)
, .INIT_31 (INIT_31)
, .INIT_32 (INIT_32)
, .INIT_33 (INIT_33)
, .INIT_34 (INIT_34)
, .INIT_35 (INIT_35)
, .INIT_36 (INIT_36)
, .INIT_37 (INIT_37)
, .INIT_38 (INIT_38)
, .INIT_39 (INIT_39)
, .INIT_3A (INIT_3A)
, .INIT_3B (INIT_3B)
, .INIT_3C (INIT_3C)
, .INIT_3D (INIT_3D)
, .INIT_3E (INIT_3E)
, .INIT_3F (INIT_3F)
includes/ram36_declare_init.vh 0 → 100644
View file @ e4816b14
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000
includes/ram36_pass_init.vh 0 → 100644
View file @ e4816b14
, .INITP_00 (INITP_00)
, .INITP_01 (INITP_01)
, .INITP_02 (INITP_02)
, .INITP_03 (INITP_03)
, .INITP_04 (INITP_04)
, .INITP_05 (INITP_05)
, .INITP_06 (INITP_06)
, .INITP_07 (INITP_07)
, .INITP_08 (INITP_08)
, .INITP_09 (INITP_09)
, .INITP_0A (INITP_0A)
, .INITP_0B (INITP_0B)
, .INITP_0C (INITP_0C)
, .INITP_0D (INITP_0D)
, .INITP_0E (INITP_0E)
, .INITP_0F (INITP_0F)
, .INIT_00 (INIT_00)
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, .INIT_08 (INIT_08)
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, .INIT_0C (INIT_0C)
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, .INIT_1B (INIT_1B)
, .INIT_1C (INIT_1C)
, .INIT_1D (INIT_1D)
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, .INIT_1F (INIT_1F)
, .INIT_20 (INIT_20)
, .INIT_21 (INIT_21)
, .INIT_22 (INIT_22)
, .INIT_23 (INIT_23)
, .INIT_24 (INIT_24)
, .INIT_25 (INIT_25)
, .INIT_26 (INIT_26)
, .INIT_27 (INIT_27)
, .INIT_28 (INIT_28)
, .INIT_29 (INIT_29)
, .INIT_2A (INIT_2A)
, .INIT_2B (INIT_2B)
, .INIT_2C (INIT_2C)
, .INIT_2D (INIT_2D)
, .INIT_2E (INIT_2E)
, .INIT_2F (INIT_2F)
, .INIT_30 (INIT_30)
, .INIT_31 (INIT_31)
, .INIT_32 (INIT_32)
, .INIT_33 (INIT_33)
, .INIT_34 (INIT_34)
, .INIT_35 (INIT_35)
, .INIT_36 (INIT_36)
, .INIT_37 (INIT_37)
, .INIT_38 (INIT_38)
, .INIT_39 (INIT_39)
, .INIT_3A (INIT_3A)
, .INIT_3B (INIT_3B)
, .INIT_3C (INIT_3C)
, .INIT_3D (INIT_3D)
, .INIT_3E (INIT_3E)
, .INIT_3F (INIT_3F)
, .INIT_40 (INIT_40)
, .INIT_41 (INIT_41)
, .INIT_42 (INIT_42)
, .INIT_43 (INIT_43)
, .INIT_44 (INIT_44)
, .INIT_45 (INIT_45)
, .INIT_46 (INIT_46)
, .INIT_47 (INIT_47)
, .INIT_48 (INIT_48)
, .INIT_49 (INIT_49)
, .INIT_4A (INIT_4A)
, .INIT_4B (INIT_4B)
, .INIT_4C (INIT_4C)
, .INIT_4D (INIT_4D)
, .INIT_4E (INIT_4E)
, .INIT_4F (INIT_4F)
, .INIT_50 (INIT_50)
, .INIT_51 (INIT_51)
, .INIT_52 (INIT_52)
, .INIT_53 (INIT_53)
, .INIT_54 (INIT_54)
, .INIT_55 (INIT_55)
, .INIT_56 (INIT_56)
, .INIT_57 (INIT_57)
, .INIT_58 (INIT_58)
, .INIT_59 (INIT_59)
, .INIT_5A (INIT_5A)
, .INIT_5B (INIT_5B)
, .INIT_5C (INIT_5C)
, .INIT_5D (INIT_5D)
, .INIT_5E (INIT_5E)
, .INIT_5F (INIT_5F)
, .INIT_60 (INIT_60)
, .INIT_61 (INIT_61)
, .INIT_62 (INIT_62)
, .INIT_63 (INIT_63)
, .INIT_64 (INIT_64)
, .INIT_65 (INIT_65)
, .INIT_66 (INIT_66)
, .INIT_67 (INIT_67)
, .INIT_68 (INIT_68)
, .INIT_69 (INIT_69)
, .INIT_6A (INIT_6A)
, .INIT_6B (INIT_6B)
, .INIT_6C (INIT_6C)
, .INIT_6D (INIT_6D)
, .INIT_6E (INIT_6E)
, .INIT_6F (INIT_6F)
, .INIT_70 (INIT_70)
, .INIT_71 (INIT_71)
, .INIT_72 (INIT_72)
, .INIT_73 (INIT_73)
, .INIT_74 (INIT_74)
, .INIT_75 (INIT_75)
, .INIT_76 (INIT_76)
, .INIT_77 (INIT_77)
, .INIT_78 (INIT_78)
, .INIT_79 (INIT_79)
, .INIT_7A (INIT_7A)
, .INIT_7B (INIT_7B)
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includes/tasks_tests_memory.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* Module: tasks_tests_memory
* Date:2015-08-01
* Author: andrey
* Description: Top-level tasks for testing memory subsystem functionality
*
* Copyright (c) 2015 Elphel, Inc .
* tasks_tests_memory.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* tasks_tests_memory.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
task test_write_levelling; // SuppressThisWarning VEditor - may be unused
begin
// Set special values for DQS idelay for write leveling
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // not no interrupt running cycle - delays are changed immediately
axi_set_dqs_idelay_wlv;
// Set write buffer (from DDR3) WE signal delay for write leveling mode
axi_set_wbuf_delay(WBUF_DLY_WLV);
axi_set_dqs_odelay('h80); // 'h80 - inverted, 'h60 - not - 'h80 will cause warnings during simulation
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
// @ (negedge rstb);
axi_set_dqs_odelay(DLY_DQS_ODELAY);
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done
// task wait_read_queue_empty; - alternative way to check fo empty read queue
// @ (negedge rstb);
axi_set_dqs_idelay_nominal;
axi_set_dqs_odelay_nominal;
// axi_set_dqs_odelay('h78);
axi_set_wbuf_delay(WBUF_DLY_DFLT); //DFLT_WBUF_DELAY
end
endtask
task test_read_pattern; // SuppressThisWarning VEditor - may be unused
begin
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done
end
endtask
task test_write_block; // SuppressThisWarning VEditor - may be unused
begin
// write_block_buf_chn; // fill block memory - already set in set_up task
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
// tempoary - for debugging:
// wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
end
endtask
task test_read_block; // SuppressThisWarning VEditor - may be unused
begin
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
3, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
endtask
// above - move to include
task test_afi_rw; // SuppressThisWarning VEditor - may be unused
input write_ddr3;
input [1:0] extra_pages;
input [21:0] frame_start_addr;
input [15:0] window_full_width; // 13 bit - in 8*16=128 bit bursts
input [15:0] window_width; // 13 bit - in 8*16=128 bit bursts
input [15:0] window_height; // 16 bit (only 14 are used here)
input [15:0] window_left;
input [15:0] window_top;
input [28:0] start64; // relative start address of the transfer (set to 0 when writing lo_addr64)
input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words
input [28:0] size64; // size of the system memory range in 64-bit words
input continue; // 0 start from start64, 1 - continue from where it was
// -----------------------------------------
integer mode;
`ifdef MEMBRIDGE_DEBUG_READ
integer ii;
`endif
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
$display("====== test_afi_rw: write=%d, extra_pages=%d, frame_start= %x, window_full_width=%d, window_width=%d, window_height=%d, window_left=%d, window_top=%d,@%t",
write_ddr3, extra_pages, frame_start_addr, window_full_width, window_width, window_height, window_left, window_top, $time);
$display("len64=%x, width64=%x, start64=%x, lo_addr64=%x, size64=%x,@%t",
((window_width[12:0]==0)? 15'h4000 : {1'b0,window_width[12:0],1'b0})*window_height[13:0],
(window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0},
start64, lo_addr64, size64, $time);
mode= func_encode_mode_scanline(
disable_need,
repetitive,
single,
reset_frame,
extra_pages,
write_ddr3, // write_mem,
1, // enable
0); // chn_reset
write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_STARTADDR, {10'b0,frame_start_addr}); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, {16'h0, window_full_width});
write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY, 0);
write_contol_register(MCNTRL_SCANLINE_CHN1_ADDR + MCNTRL_SCANLINE_MODE, mode);
configure_channel_priority(1,0); // lowest priority channel 3
enable_memcntrl_en_dis(1,1);
// write_contol_register(test_mode_address, TEST01_START_FRAME);
afi_setup(0);
membridge_setup(
((window_width[12:0]==0)? 15'h4000 : {1'b0,window_width[12:0],1'b0})*window_height[13:0], //len64,
(window_width[12:0]==0)? 29'h4000 : {15'b0,window_width[12:0],1'b0}, // width64,
start64,
lo_addr64,
size64);
membridge_start (continue);
`ifdef MEMBRIDGE_DEBUG_READ
// debugging
for (ii=0; ii < 10; ii=ii +1) begin
#200; //#50;
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {27'b0,continue,4'b1101}); // enable both address and data
end
#500;
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {26'b0,continue,5'b10001}); // disable debug (enable remaining xfers)
`endif
// just wait done
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
MEMBRIDGE_STATUS_REG, // MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
MEMBRIDGE_ADDR + MEMBRIDGE_STATUS_CNTRL, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
0, // equal to
1); // do synchronize sequence number
end
endtask
task test_scanline_write; // SuppressThisWarning VEditor - may be unused
input [3:0] channel;
input [1:0] extra_pages;
input wait_done;
input [15:0] window_width; // 13 bit - in 8*16=128 bit bursts
input [15:0] window_height; // 16 bit
input [15:0] window_left;
input [15:0] window_top;
reg [29:0] start_addr;
integer mode;
reg [STATUS_DEPTH-1:0] status_address;
reg [29:0] status_control_address;
reg [29:0] test_mode_address;
integer ii;
integer xfer_size;
integer pages_per_row;
integer startx,starty; // temporary - because of the vdt bug with integer ports
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
$display("====== test_scanline_write: channel=%d, extra_pages=%d, wait_done=%d @%t",
channel, extra_pages, wait_done, $time);
case (channel)
// 1: begin
// start_addr= MCNTRL_SCANLINE_CHN1_ADDR;
// status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
// status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
// test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
// end
3: begin
start_addr= MCNTRL_SCANLINE_CHN3_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN3_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE;
end
default: begin
$display("**** ERROR: Invalid channel, only 3 is valid");
start_addr= MCNTRL_SCANLINE_CHN3_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
end
endcase
mode= func_encode_mode_scanline(
disable_need,
repetitive,
single,
reset_frame,
extra_pages,
1, // write_mem,
1, // enable
0); // chn_reset
write_contol_register(start_addr + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_MODE, mode);
configure_channel_priority(channel,0); // lowest priority channel 3
// enable_memcntrl_channels(16'h000b); // channels 0,1,3 are enabled
enable_memcntrl_en_dis(channel,1);
write_contol_register(test_mode_address, TEST01_START_FRAME);
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
// VDT bugs: 1:does not propagate undefined width through ?:, 2: - does not allow to connect it to task integer input, 3: shows integer input width as 1
xfer_size= ((pages_per_row>1)?
(
(
((ii % pages_per_row) < (pages_per_row-1))?
(1<<NUM_XFER_BITS):
(window_width % (1<<NUM_XFER_BITS))
)
):
({16'b0,window_width}));
$display("########### test_scanline_write block %d: channel=%d, @%t", ii, channel, $time);
startx=window_left + ((ii % pages_per_row)<<NUM_XFER_BITS);
starty=window_top + (ii / pages_per_row);
write_block_scanline_chn(
channel,
(ii & 3),
xfer_size,
startx, //window_left + ((ii % pages_per_row)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
starty); // window_top + (ii / pages_per_row)); // SCANLINE_CUR_Y);\
end
for (ii=0;ii< (window_height * pages_per_row) ;ii = ii+1) begin // here assuming 1 page per line
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
status_address, //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
(ii-TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1, // not equal to
(ii == TEST_INITIAL_BURST)); // synchronize sequence number - only first time, next just wait fro auto update
xfer_size= ((pages_per_row>1)?
(
(
((ii % pages_per_row) < (pages_per_row-1))?
(1<<NUM_XFER_BITS):
(window_width % (1<<NUM_XFER_BITS))
)
):
({16'b0,window_width}));
$display("########### test_scanline_write block %d: channel=%d, @%t", ii, channel, $time);
startx=window_left + ((ii % pages_per_row)<<NUM_XFER_BITS);
starty=window_top + (ii / pages_per_row);
write_block_scanline_chn(
channel,
(ii & 3),
xfer_size,
startx, // window_left + ((ii % pages_per_row)<<NUM_XFER_BITS), // SCANLINE_CUR_X,
starty); // window_top + (ii / pages_per_row)); // SCANLINE_CUR_Y);
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
end
if (wait_done) begin
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
status_address, // MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
0, // equal to
0); // no need to synchronize sequence number
// enable_memcntrl_en_dis(channel,0); // disable channel
end
end
endtask
task test_scanline_read; // SuppressThisWarning VEditor - may be unused
input [3:0] channel;
input [1:0] extra_pages;
input show_data;
input [15:0] window_width;
input [15:0] window_height;
input [15:0] window_left;
input [15:0] window_top;
reg [29:0] start_addr;
integer mode;
reg [STATUS_DEPTH-1:0] status_address;
reg [29:0] status_control_address;
reg [29:0] test_mode_address;
integer ii;
integer xfer_size;
integer pages_per_row;
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
pages_per_row= (window_width>>NUM_XFER_BITS)+((window_width[NUM_XFER_BITS-1:0]==0)?0:1);
$display("====== test_scanline_read: channel=%d, extra_pages=%d, show_data=%d @%t",
channel, extra_pages, show_data, $time);
case (channel)
// 1: begin
// start_addr= MCNTRL_SCANLINE_CHN1_ADDR;
// status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
// status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
// test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
// end
3: begin
start_addr= MCNTRL_SCANLINE_CHN3_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN3_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE;
end
default: begin
$display("**** ERROR: Invalid channel, only 3 is valid");
start_addr= MCNTRL_SCANLINE_CHN3_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN1_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN1_MODE;
end
endcase
mode= func_encode_mode_scanline(
disable_need,
repetitive,
single,
reset_frame,
extra_pages,
0, // write_mem,
1, // enable
0); // chn_reset
// program to the
write_contol_register(start_addr + MCNTRL_SCANLINE_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_WINDOW_STARTXY, SCANLINE_STARTX+(SCANLINE_STARTY<<16));
write_contol_register(start_addr + MCNTRL_SCANLINE_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(channel,0); // lowest priority channel 3
enable_memcntrl_en_dis(channel,1);
write_contol_register(test_mode_address, TEST01_START_FRAME);
for (ii=0;ii<(window_height * pages_per_row);ii = ii+1) begin
xfer_size= ((pages_per_row>1)?
(
(
((ii % pages_per_row) < (pages_per_row-1))?
(1<<NUM_XFER_BITS):
(window_width % (1<<NUM_XFER_BITS))
)
):
({16'b0,window_width}));
wait_status_condition (
status_address, //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
(ii) << 16, // -TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1, // not equal to
(ii == 0)); // synchronize sequence number - only first time, next just wait fro auto update
// read block (if needed), for now just sikip
if (show_data) begin
$display("########### test_scanline_read block %d: channel=%d, @%t", ii, channel, $time);
read_block_buf_chn (
channel,
(ii & 3),
xfer_size <<2,
1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
end
end
endtask
task test_tiled_write; // SuppressThisWarning VEditor - may be unused
input [3:0] channel;
input byte32;
input keep_open;
input [1:0] extra_pages;
input wait_done;
input [15:0] window_width;
input [15:0] window_height;
input [15:0] window_left;
input [15:0] window_top;
input [ 7:0] tile_width;
input [ 7:0] tile_height;
input [ 7:0] tile_vstep;
reg [29:0] start_addr;
integer mode;
reg [STATUS_DEPTH-1:0] status_address;
reg [29:0] status_control_address;
reg [29:0] test_mode_address;
integer ii;
integer tiles_per_row;
integer tile_rows_per_window;
integer tile_size;
integer startx,starty; // temporary - because of the vdt bug with integer ports
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
tiles_per_row= (window_width/tile_width)+ ((window_width % tile_width==0)?0:1);
tile_rows_per_window= ((window_height-1)/tile_vstep) + 1;
tile_size= tile_width*tile_height;
$display("====== test_tiled_write: channel=%d, byte32=%d, keep_open=%d, extra_pages=%d, wait_done=%d @%t",
channel, byte32, keep_open, extra_pages, wait_done, $time);
case (channel)
2: begin
start_addr= MCNTRL_TILED_CHN2_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
end
4: begin
start_addr= MCNTRL_TILED_CHN4_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN4_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_MODE;
end
default: begin
$display("**** ERROR: Invalid channel, only 2 and 4 are valid");
start_addr= MCNTRL_TILED_CHN2_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
end
endcase
mode= func_encode_mode_tiled(
disable_need,
repetitive,
single,
reset_frame,
byte32,
keep_open,
extra_pages,
1, // write_mem,
1, // enable
0); // chn_reset
write_contol_register(start_addr + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
write_contol_register(start_addr + MCNTRL_TILED_TILE_WHS, {8'b0,tile_vstep,tile_height,tile_width});//tile_width+(tile_height<<8)+(tile_vstep<<16));
write_contol_register(start_addr + MCNTRL_TILED_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(channel,0); // lowest priority channel 3
enable_memcntrl_en_dis(channel,1);
write_contol_register(test_mode_address, TEST01_START_FRAME);
for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
$display("########### test_tiled_write block %d: channel=%d, @%t", ii, channel, $time);
startx = window_left + ((ii % tiles_per_row) * tile_width);
starty = window_top + (ii / tile_rows_per_window); // SCANLINE_CUR_Y);\
write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
channel, // channel
(ii & 3),
tile_size,
startx, //window_left + ((ii % tiles_per_row) * tile_width),
starty); //window_top + (ii / tile_rows_per_window)); // SCANLINE_CUR_Y);\
end
for (ii=0;ii<(tiles_per_row * tile_rows_per_window);ii = ii+1) begin
if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
wait_status_condition (
status_address, // MCNTRL_TEST01_STATUS_REG_CHN5_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN5_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
(ii-TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1, // not equal to
(ii == TEST_INITIAL_BURST)); // synchronize sequence number - only first time, next just wait fro auto update
$display("########### test_tiled_write block %d: channel=%d, @%t", ii, channel, $time);
startx = window_left + ((ii % tiles_per_row) * tile_width);
starty = window_top + (ii / tile_rows_per_window);
write_block_scanline_chn( // TODO: Make a different tile buffer data, matching the order
channel, // channel
(ii & 3),
tile_size,
startx, // window_left + ((ii % tiles_per_row) * tile_width),
starty); // window_top + (ii / tile_rows_per_window)); // SCANLINE_CUR_Y);\
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
end
if (wait_done) begin
wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
status_address, // MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
2 << STATUS_2LSB_SHFT, // mask for the 4-bit page number
0, // equal to
0); // no need to synchronize sequence number
// enable_memcntrl_en_dis(channel,0); // disable channel
end
end
endtask
task test_tiled_read; // SuppressThisWarning VEditor - may be unused
input [3:0] channel;
input byte32;
input keep_open;
input [1:0] extra_pages;
input show_data;
input [15:0] window_width;
input [15:0] window_height;
input [15:0] window_left;
input [15:0] window_top;
input [ 7:0] tile_width;
input [ 7:0] tile_height;
input [ 7:0] tile_vstep;
reg [29:0] start_addr;
integer mode;
reg [STATUS_DEPTH-1:0] status_address;
reg [29:0] status_control_address;
reg [29:0] test_mode_address;
integer ii;
integer tiles_per_row;
integer tile_rows_per_window;
integer tile_size;
reg repetitive;
reg single;
reg reset_frame;
reg disable_need;
begin
disable_need = 1'b0;
repetitive = 1'b1;
single = 1'b0;
reset_frame = 1'b0;
tiles_per_row= (window_width/tile_width)+ ((window_width % tile_width==0)?0:1);
tile_rows_per_window= ((window_height-1)/tile_vstep) + 1;
tile_size= tile_width*tile_height;
$display("====== test_tiled_read: channel=%d, byte32=%d, keep_open=%d, extra_pages=%d, show_data=%d @%t",
channel, byte32, keep_open, extra_pages, show_data, $time);
case (channel)
2: begin
start_addr= MCNTRL_TILED_CHN2_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
end
4: begin
start_addr= MCNTRL_TILED_CHN4_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN4_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_MODE;
end
default: begin
$display("**** ERROR: Invalid channel, only 2 and 4 are valid");
start_addr= MCNTRL_TILED_CHN2_ADDR;
status_address= MCNTRL_TEST01_STATUS_REG_CHN2_ADDR;
status_control_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL;
test_mode_address= MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE;
end
endcase
mode= func_encode_mode_tiled(
disable_need,
repetitive,
single,
reset_frame,
byte32,
keep_open,
extra_pages,
0, // write_mem,
1, // enable
0); // chn_reset
write_contol_register(start_addr + MCNTRL_TILED_STARTADDR, FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
write_contol_register(start_addr + MCNTRL_TILED_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_WH, {window_height,window_width}); //WINDOW_WIDTH + (WINDOW_HEIGHT<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_X0Y0, {window_top,window_left}); //WINDOW_X0+ (WINDOW_Y0<<16));
write_contol_register(start_addr + MCNTRL_TILED_WINDOW_STARTXY, TILED_STARTX+(TILED_STARTY<<16));
write_contol_register(start_addr + MCNTRL_TILED_TILE_WHS, {8'b0,tile_vstep,tile_height,tile_width});//(tile_height<<8)+(tile_vstep<<16));
write_contol_register(start_addr + MCNTRL_TILED_MODE, mode);// set mode register: {extra_pages[1:0],enable,!reset}
configure_channel_priority(channel,0); // lowest priority channel 3
enable_memcntrl_en_dis(channel,1);
write_contol_register(test_mode_address, TEST01_START_FRAME);
for (ii=0;ii<(tiles_per_row * tile_rows_per_window);ii = ii+1) begin
wait_status_condition (
status_address, // MCNTRL_TEST01_STATUS_REG_CHN4_ADDR,
status_control_address, // MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN4_STATUS_CNTRL,
DEFAULT_STATUS_MODE,
ii << 16, // -TEST_INITIAL_BURST)<<16, // 4-bit page number
'hf << 16, // mask for the 4-bit page number
1, // not equal to
(ii == 0)); // synchronize sequence number - only first time, next just wait fro auto update
if (show_data) begin
$display("########### test_tiled_read block %d: channel=%d, @%t", ii, channel, $time);
read_block_buf_chn (
channel,
(ii & 3),
tile_size <<2,
1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
write_contol_register(test_mode_address, TEST01_NEXT_PAGE);
end
// enable_memcntrl_en_dis(channel,0); // disable channel
end
endtask
includes/x393_cur_params_target.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_cur_params_target.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Memory controller parameters that need adjustment during training
* Target ,pde
* Copyright (c) 2015 Elphel, Inc.
* x393_cur_params_target.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_cur_params_target.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
localparam DLY_LANE0_ODELAY = 80'hd85c1014141814181218;
localparam DLY_LANE0_IDELAY = 72'h2c7a8380897c807b88;
localparam DLY_LANE1_ODELAY = 80'hd8581812181418181814;
localparam DLY_LANE1_IDELAY = 72'h108078807a887c8280;
localparam DLY_CMDA = 256'hd3d3d3d4dcd1d8cc494949494949494949d4d3ccd3d3dbd4ccd4d2d3d1d2d8cc;
localparam DLY_PHASE = 8'h33;
// localparam DFLT_WBUF_DELAY = 4'h9;
\ No newline at end of file
includes/x393_localparams.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_localparams.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Local parameters for simulation of the x393
*
* Copyright (c) 2015 Elphel, Inc.
* x393_localparams.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_localparams.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// S uppressWarnings VEditor
localparam [1:0] DEFAULT_STATUS_MODE = 3; // auto status on change, increase sequence number
localparam LD_DLY_LANE0_ODELAY = DLY_LD+'h00; // 0x1080
localparam LD_DLY_LANE0_IDELAY = DLY_LD+'h10; // 0x1090
localparam LD_DLY_LANE1_ODELAY = DLY_LD+'h20; // 0x10a0
localparam LD_DLY_LANE1_IDELAY = DLY_LD+'h30; // 0x10b0
localparam LD_DLY_CMDA = DLY_LD+'h40; // 0x10c0
localparam LD_DLY_PHASE = DLY_LD+'h60; // 0x10e0
localparam DLY_SET = MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_DLY_SET; //0x1020
// different sets of settings for the functional simulation and the actual hardware - should not be needed anymore
localparam T_RFC=50; // t_rfc=50 for tCK=2.5ns
localparam T_REFI=48; // t_refi; # 48/97 for normal, 8 - for simulation (7.8us <85C, 3.9us >85C)
// alternative to set same type delays to the same value
localparam DLY_DQ_IDELAY = ( (DLY_LANE0_IDELAY & 8'hff)+
((DLY_LANE0_IDELAY>> 8) & 8'hff)+
((DLY_LANE0_IDELAY>>16) & 8'hff)+
((DLY_LANE0_IDELAY>>24) & 8'hff)+
((DLY_LANE0_IDELAY>>32) & 8'hff)+
((DLY_LANE0_IDELAY>>40) & 8'hff)+
((DLY_LANE0_IDELAY>>48) & 8'hff)+
((DLY_LANE0_IDELAY>>56) & 8'hff)+
(DLY_LANE1_IDELAY & 8'hff)+
((DLY_LANE1_IDELAY>> 8) & 8'hff)+
((DLY_LANE1_IDELAY>>16) & 8'hff)+
((DLY_LANE1_IDELAY>>24) & 8'hff)+
((DLY_LANE1_IDELAY>>32) & 8'hff)+
((DLY_LANE1_IDELAY>>40) & 8'hff)+
((DLY_LANE1_IDELAY>>48) & 8'hff)+
((DLY_LANE1_IDELAY>>56) & 8'hff)+ 8 ) >> 4;
localparam DLY_DQ_ODELAY = (((DLY_LANE0_ODELAY & 8'hff)+
((DLY_LANE0_ODELAY>> 8) & 8'hff)+
((DLY_LANE0_ODELAY>>16) & 8'hff)+
((DLY_LANE0_ODELAY>>24) & 8'hff)+
((DLY_LANE0_ODELAY>>32) & 8'hff)+
((DLY_LANE0_ODELAY>>40) & 8'hff)+
((DLY_LANE0_ODELAY>>48) & 8'hff)+
((DLY_LANE0_ODELAY>>56) & 8'hff)+
(DLY_LANE1_ODELAY & 8'hff)+
((DLY_LANE1_ODELAY>> 8) & 8'hff)+
((DLY_LANE1_ODELAY>>16) & 8'hff)+
((DLY_LANE1_ODELAY>>24) & 8'hff)+
((DLY_LANE1_ODELAY>>32) & 8'hff)+
((DLY_LANE1_ODELAY>>40) & 8'hff)+
((DLY_LANE1_ODELAY>>48) & 8'hff)+
((DLY_LANE1_ODELAY>>56) & 8'hff)+ 8 ) >> 4);
localparam DLY_DQS_IDELAY = (((DLY_LANE0_IDELAY>>64) & 8'hff)+
((DLY_LANE1_IDELAY>>64) & 8'hff)+ 1 ) >> 1;
localparam DLY_DQS_ODELAY = (((DLY_LANE0_ODELAY>>64) & 8'hff)+
((DLY_LANE1_ODELAY>>64) & 8'hff)+ 1 ) >> 1;
localparam DLY_DM_ODELAY = DLY_DQ_ODELAY;
localparam DLY_CMDA_ODELAY =(((DLY_CMDA>> 0) & 8'hff)+
((DLY_CMDA>> 8) & 8'hff)+
((DLY_CMDA>>'h10) & 8'hff)+
((DLY_CMDA>>'h18) & 8'hff)+
((DLY_CMDA>>'h20) & 8'hff)+
((DLY_CMDA>>'h28) & 8'hff)+
((DLY_CMDA>>'h30) & 8'hff)+
((DLY_CMDA>>'h38) & 8'hff)+
((DLY_CMDA>>'h40) & 8'hff)+
((DLY_CMDA>>'h48) & 8'hff)+
((DLY_CMDA>>'h50) & 8'hff)+
((DLY_CMDA>>'h58) & 8'hff)+
((DLY_CMDA>>'h60) & 8'hff)+
((DLY_CMDA>>'h68) & 8'hff)+
((DLY_CMDA>>'h70) & 8'hff)+
((DLY_CMDA>>'hc0) & 8'hff)+
((DLY_CMDA>>'hc8) & 8'hff)+
((DLY_CMDA>>'hd0) & 8'hff)+
((DLY_CMDA>>'hd8) & 8'hff)+
((DLY_CMDA>>'he0) & 8'hff)+
((DLY_CMDA>>'he8) & 8'hff)+
((DLY_CMDA>>'hf0) & 8'hff)+
((DLY_CMDA>>'hf8) & 8'hff)+ 12 ) / 23;
localparam DLY_LANE0_DQS_WLV_IDELAY = DLY_DQS_IDELAY; // b0; // idelay dqs
localparam DLY_LANE1_DQS_WLV_IDELAY = DLY_DQS_IDELAY; // b0; idelay dqs
localparam DQSTRI_FIRST= 4'h1; // 3; // DQS tri-state control word, first when enabling output
localparam DQSTRI_LAST= 4'hc; // DQS tri-state control word, first after disabling output
localparam DQTRI_FIRST= 4'h3; // 7; // DQ tri-state control word, first when enabling output
localparam DQTRI_LAST= 4'he; // DQ tri-state control word, first after disabling output
localparam WBUF_DLY_DFLT= DFLT_WBUF_DELAY; // 4'h8; // 4'h6; // extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
localparam WBUF_DLY_WLV= DFLT_WBUF_DELAY; // 4'h7; // write leveling mode: extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
localparam INITIALIZE_OFFSET= 'h00; // moemory initialization start address (in words) ..`h0c
localparam REFRESH_OFFSET= 'h10; // refresh start address (in words) ..`h13
localparam WRITELEV_OFFSET= 'h20; // write leveling start address (in words) ..`h2a
localparam READ_PATTERN_OFFSET='h40; // read pattern to memory block sequence start address (in words) ..'h053 with 8x2*64 bits (variable)
localparam WRITE_BLOCK_OFFSET= 'h100; // write block sequence start address (in words) ..'h14c
localparam READ_BLOCK_OFFSET= 'h180; // read block sequence start address (in words)
localparam STATUS_SEQ_SHFT= 26; // bits [31:26] is the sequence number
localparam STATUS_2LSB_SHFT= 24; // bits [25:24] get the 2 LSB of the status (transmitted with the sequence number in the second byte)
localparam STATUS_MSB_RSHFT= 2; // status bits [25:2] are read through [23:0]
localparam STATUS_PSHIFTER_RDY_MASK = 1<<STATUS_2LSB_SHFT;
localparam FRAME_START_ADDRESS= 'h1000; // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0)
localparam FRAME_START_ADDRESS_INC= 'h800;
localparam LAST_BUF_FRAME = 1;
localparam CAMSYNC_DELAY = 200;
localparam FRAME_FULL_WIDTH= 'h0c0; // Padded line length (8-row increment), in 8-bursts (16 bytes)
// localparam AFI_LO_ADDR64= 'h4000; // start of the system memory range in 64-bit words
// localparam AFI_SIZE64= 'h4000; // size of system memory range in 64-bit words
// Same as in the actual hardware
localparam AFI_LO_ADDR64= 'h4f20000; // start of the system memory range in 64-bit words
localparam AFI_SIZE64= 'h0c80000; // size of system memory range in 64-bit words
// localparam SCANLINE_WINDOW_WH= `h079000a2; // 2592*1936: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
// localparam SCANLINE_WINDOW_WH= 'h0009000b; // 176*9: low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
localparam WINDOW_WIDTH= 'h000b; //'h005b; //'h000b; // 176: 13-bit window width (0->'h4000)
localparam WINDOW_HEIGHT= 'h000a; // 9: 16-bit window height (0->'h10000)
// localparam SCANLINE_X0Y0= 'h00050003; // X0=3*16=48, Y0=5: // low word - 13-bit window left, high word - 16-bit window top
localparam WINDOW_X0= 'h5c; //'h7f; // 'h005c; // 'h7c; // 'h0003; // X0=3*16=48 - 13-bit window left
localparam WINDOW_Y0= 'h0005; // Y0=5: 16-bit window top
// localparam SCANLINE_STARTXY= 'h0; // low word - 13-bit start X (relative to window), high word - 16-bit start y (normally 0)
localparam SCANLINE_STARTX= 'h0; // 13-bit start X (relative to window), high word (normally 0)
localparam SCANLINE_STARTY= 'h0; // 16-bit start y (normally 0)
localparam [1:0] SCANLINE_EXTRA_PAGES= 0; // 0..2 - number of pages in the buffer to keep/not write // SuppressThisWarning VEditor - not used
localparam TILED_STARTX= 'h0; // 13-bit start X (relative to window), high word (normally 0)
localparam TILED_STARTY= 'h0; // 16-bit start y (normally 0)
localparam [1:0] TILED_EXTRA_PAGES= 0; // 0..2 - number of pages in the buffer to keep/not write
localparam TILED_KEEP_OPEN= 1'b1; //1'b1; // 1'b0; // Do not close banks between reads (valid only for tiles <=8 rows, needed if less than 3? rows)
localparam TILE_WIDTH= 'h04; // 6-bit tile width (1..'h40)
localparam TILE_HEIGHT= 'h08; //'h05; // 'h04; //'h06; // 6-bit tile height (1..'h40) // 4 - violation
localparam TILE_VSTEP= 'h04; // 6-bit tile vertical step, with no overlap it is equal to TILE_HEIGHT (1..'h40)
localparam TEST01_START_FRAME= 1;
localparam TEST01_NEXT_PAGE= 2;
localparam TEST01_SUSPEND= 4; // SuppressThisWarning VEditor - not used
localparam TEST_INITIAL_BURST= 4; // 3;
\ No newline at end of file
includes/x393_mcontr_encode_cmd.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_mcontr_encode_cmd.vh
* Date:2015-02-09
* Author: Andrey Filippov
* Description: Functions used to encode memory controller sequences
*
* Copyright (c) 2015 Elphel, Inc.
* x393_mcontr_encode_cmd.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_mcontr_encode_cmd.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
function [31:0] func_encode_skip;
input [CMD_PAUSE_BITS-1:0] skip; // number of extra cycles to skip (and keep all the other outputs)
input done; // end of sequence
input [2:0] bank; // bank (here OK to be any)
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_skip= func_encode_cmd (
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column address
bank[2:0], // bank (here OK to be any)
3'b0, // RAS/CAS/WE, positive logic
odt_en, // enable ODT
cke, // disable CKE
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // connect to external buffer (but only if not paused)
1'b0, // nop
buf_rst);
end
endfunction
function [31:0] func_encode_cmd;
input [14:0] addr; // 15-bit row/column address
input [2:0] bank; // bank (here OK to be any)
input [2:0] rcw; // RAS/CAS/WE, positive logic
input odt_en; // enable ODT
input cke; // disable CKE
input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
input dqs_toggle; // enable toggle DQS according to the pattern
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input nop; // add NOP after the current command, keep other data
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_cmd={
addr[14:0], // 15-bit row/column address
bank [2:0], // bank
rcw[2:0], // RAS/CAS/WE
odt_en, // enable ODT
cke, // may be optimized (removed from here)?
sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
dqs_toggle, // enable toggle DQS according to the pattern
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
nop, // add NOP after the current command, keep other data
buf_rst // Reserved for future use
};
end
endfunction
includes/x393_parameters.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_parameters.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Parameters for the x393 (simulation and implementation)
*
* Copyright (c) 2015 Elphel, Inc.
* x393_parameters.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_parameters.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
parameter MCONTR_RD_MASK = 'h3c00, // AXI read address mask to generate busy
parameter CONTROL_ADDR = 'h0000, // AXI write address of control write registers
parameter CONTROL_ADDR_MASK = 'h3800, // AXI write mask of control registers
parameter CONTROL_RBACK_ADDR = 'h0000, // AXI read address of control registers readback
parameter CONTROL_RBACK_ADDR_MASK = 'h3800, // AXI mask of control registers readback addresses
parameter CONTROL_RBACK_DEPTH= 11, // 10 - 1xbram, 11 - 2xbram
parameter STATUS_ADDR = 'h0800, // AXI read address of status read registers
parameter STATUS_ADDR_MASK = 'h3c00, // AXI write address of status registers
parameter MCONTR_CMD_WR_ADDR = 'h0c00, // AXI write to command sequence memory
parameter MCONTR_BUF0_RD_ADDR = 'h1000, // AXI read address from buffer 0 (PS sequence, memory read) (was 'h400)
parameter MCONTR_BUF0_WR_ADDR = 'h1000, // AXI write address to buffer 0 (PS sequence, memory write) (was 'h400)
// MCONTR_BUF[2-4]_* - temporary, will be removed in the futire
parameter MCONTR_BUF2_RD_ADDR = 'h1400, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
parameter MCONTR_BUF2_WR_ADDR = 'h1400, // AXI write address to buffer 2 (PL sequence, tiles, memory write)
parameter MCONTR_BUF3_RD_ADDR = 'h1800, // AXI read address from buffer 3 (PL sequence, scanline, memory read)
parameter MCONTR_BUF3_WR_ADDR = 'h1800, // AXI write address to buffer 3 (PL sequence, scanline, memory write)
parameter MCONTR_BUF4_RD_ADDR = 'h1c00, // AXI read address from buffer 4 (PL sequence, tiles, memory read)
parameter MCONTR_BUF4_WR_ADDR = 'h1c00, // AXI write address to buffer 4 (PL sequence, tiles, memory write)
parameter AXI_WR_ADDR_BITS = 14,
parameter AXI_RD_ADDR_BITS = 14,
parameter STATUS_DEPTH= 8, // 256 cells, maybe just 16..64 are enough?
//command interface parameters
parameter DLY_LD = 'h080, // address to generate delay load
parameter DLY_LD_MASK = 'h780, // address mask to generate delay load
//0x1000..103f - 0- bit data (set/reset)
parameter MCONTR_PHY_0BIT_ADDR = 'h020, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_0BIT_ADDR_MASK = 'h7f0, // address mask to generate sequencer channel/run
// 0x1020 - DLY_SET // 0 bits -set pre-programmed delays
// 0x1024..1025 - CMDA_EN // 0 bits - enable/disable command/address outputs
// 0x1026..1027 - SDRST_ACT // 0 bits - enable/disable active-low reset signal to DDR3 memory
// 0x1028..1029 - CKE_EN // 0 bits - enable/disable CKE signal to memory
// 0x102a..102b - DCI_RST // 0 bits - enable/disable CKE signal to memory
// 0x102c..102d - DLY_RST // 0 bits - enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_SET = 'h0, // set pre-programmed delays
parameter MCONTR_PHY_0BIT_CMDA_EN = 'h4, // enable/disable command/address outputs
parameter MCONTR_PHY_0BIT_SDRST_ACT = 'h6, // enable/disable active-low reset signal to DDR3 memory
parameter MCONTR_PHY_0BIT_CKE_EN = 'h8, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DCI_RST = 'ha, // enable/disable CKE signal to memory
parameter MCONTR_PHY_0BIT_DLY_RST = 'hc, // enable/disable CKE signal to memory
//0x1030..1037 - 0-bit memory cotroller (set/reset)
parameter MCONTR_TOP_0BIT_ADDR = 'h030, // address to turn on/off memory controller features
parameter MCONTR_TOP_0BIT_ADDR_MASK = 'h7f8, // address mask to generate sequencer channel/run
// 0x1030..1031 - MCONTR_EN // 0 bits, disable/enable memory controller
// 0x1032..1033 - REFRESH_EN // 0 bits, disable/enable memory refresh
// 0x1034..1037 - reserved
parameter MCONTR_TOP_0BIT_MCONTR_EN = 'h0, // set pre-programmed delays
parameter MCONTR_TOP_0BIT_REFRESH_EN = 'h2, // disable/enable command/address outputs
//0x1040..107f - 16-bit data
// 0x1040..104f - RUN_CHN // address to set sequncer channel and run (4 LSB-s - channel) - bits?
// parameter RUN_CHN_REL = 'h040, // address to set sequnecer channel and run (4 LSB-s - channel)
// parameter RUN_CHN_REL_MASK = 'h7f0, // address mask to generate sequencer channel/run
// 0x1050..1057: MCONTR_PHY16
parameter MCONTR_PHY_16BIT_ADDR = 'h050, // address to set sequnecer channel and run (4 LSB-s - channel)
parameter MCONTR_PHY_16BIT_ADDR_MASK = 'h7f8, // address mask to generate sequencer channel/run
// 0x1050 - PATTERNS // 16 bits
// 0x1051 - PATTERNS_TRI // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
// 0x1052 - WBUF_DELAY // 4 bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
// 0x1053 - EXTRA_REL // 1 bit - set extra parameters (currently just inv_clk_div)
// 0x1054 - STATUS_CNTRL // 8 bits - write to status control
parameter MCONTR_PHY_16BIT_PATTERNS = 'h0, // set DQM and DQS patterns (16'h0055)
parameter MCONTR_PHY_16BIT_PATTERNS_TRI = 'h1, // 16-bit address to set DQM and DQS tristate on/off patterns {dqs_off,dqs_on, dq_off,dq_on} - 4 bits each
parameter MCONTR_PHY_16BIT_WBUF_DELAY = 'h2, // 4? bits - extra delay (in mclk cycles) to add to write buffer enable (DDR3 read data)
parameter MCONTR_PHY_16BIT_EXTRA = 'h3, // ? bits - set extra parameters (currently just inv_clk_div)
parameter MCONTR_PHY_STATUS_CNTRL = 'h4, // write to status control (8-bit)
//0x1060..106f: arbiter priority data
parameter MCONTR_ARBIT_ADDR = 'h060, // Address to set channel priorities
parameter MCONTR_ARBIT_ADDR_MASK = 'h7f0, // Address mask to set channel priorities
//0x1070..1077 - 16-bit top memory controller:
parameter MCONTR_TOP_16BIT_ADDR = 'h070, // address to set mcontr top control registers
parameter MCONTR_TOP_16BIT_ADDR_MASK = 'h7f8, // address mask to set mcontr top control registers
// 0x1070 - MCONTR_CHN_EN // 16 bits per-channel enable (want/need requests)
// 0x1071 - REFRESH_PERIOD // 8-bit refresh period
// 0x1072 - REFRESH_ADDRESS // 10 bits
// 0x1073 - STATUS_CNTRL // 8 bits - write to status control (and debug?)
parameter MCONTR_TOP_16BIT_CHN_EN = 'h0, // 16 bits per-channel enable (want/need requests)
parameter MCONTR_TOP_16BIT_REFRESH_PERIOD = 'h1, // 8-bit refresh period
parameter MCONTR_TOP_16BIT_REFRESH_ADDRESS= 'h2, // 10 bits refresh address in the sequencer (PL) memory
parameter MCONTR_TOP_16BIT_STATUS_CNTRL= 'h3, // 8 bits - write to status control (and debug?)
// Status read address
parameter MCONTR_PHY_STATUS_REG_ADDR= 'h0, // 8 or less bits: status register address to use for memory controller phy
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 2, //1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'haa, // TODO: make work for the simulator too 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
parameter DFLT_DQ_TRI_ON_PATTERN= 4'h7, // DQ tri-state control word, first when enabling output
parameter DFLT_DQ_TRI_OFF_PATTERN= 4'he, // DQ tri-state control word, first after disabling output
parameter DFLT_DQS_TRI_ON_PATTERN= 4'h3, // DQS tri-state control word, first when enabling output
parameter DFLT_DQS_TRI_OFF_PATTERN=4'hc, // DQS tri-state control word, first after disabling output
parameter DFLT_WBUF_DELAY= 4'h9, // TODO: Find the reason - simulation needs 8, target - 9
parameter DFLT_INV_CLK_DIV= 1'b0,
parameter DFLT_CHN_EN= 16'h0, // channel mask to be enabled at reset
parameter DFLT_REFRESH_ADDR= 10'h0, // refresh sequence address in command memory
parameter DFLT_REFRESH_PERIOD= 8'h0, // default 8-bit refresh period (scale?)
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter PHASE_WIDTH = 8,
parameter SLEW_DQ = "SLOW",
parameter SLEW_DQS = "SLOW",
parameter SLEW_CMDA = "SLOW",
parameter SLEW_CLK = "SLOW",
parameter IBUF_LOW_PWR = "TRUE",
`ifdef use200Mhz
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
parameter CLK_DIV_PHASE = 0.000,
parameter MCLK_PHASE = 90.000,
parameter REF_JITTER1 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter SS_MOD_PERIOD = 10000,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10,
parameter NUM_CYCLES_LOW_BIT= 'h6, // decode addresses [NUM_CYCLES_LOW_BIT+:4] into command a/d length
// TODO: put actual data
parameter NUM_CYCLES_00 = 2, // 2-cycle 000.003f
parameter NUM_CYCLES_01 = 4, // 4-cycle 040.007f
parameter NUM_CYCLES_02 = 3, // 3-cycle 080.00bf
parameter NUM_CYCLES_03 = 3, // 3-cycle 0c0.00ff
parameter NUM_CYCLES_04 = 6, // 6-cycle 100.013f
parameter NUM_CYCLES_05 = 6, // 6-cycle 140.017f
parameter NUM_CYCLES_06 = 4, // 4-cycle 180.01bf
parameter NUM_CYCLES_07 = 4, // 4-cycle 1c0.01ff
parameter NUM_CYCLES_08 = 6, // 6-cycle 200.023f
parameter NUM_CYCLES_09 = 6, //
parameter NUM_CYCLES_10 = 6, //
parameter NUM_CYCLES_11 = 6, //
parameter NUM_CYCLES_12 = 6, //
parameter NUM_CYCLES_13 = 5, // 5-cycle - not yet used
parameter NUM_CYCLES_14 = 6, // 6-cycle - not yet used
parameter NUM_CYCLES_15 = 9, // single-cycle
parameter NUM_CYCLES_16 = 6, //
parameter NUM_CYCLES_17 = 6, //
parameter NUM_CYCLES_18 = 6, //
parameter NUM_CYCLES_19 = 6, //
parameter NUM_CYCLES_20 = 6, //
parameter NUM_CYCLES_21 = 6, //
parameter NUM_CYCLES_22 = 6, //
parameter NUM_CYCLES_23 = 6, //
parameter NUM_CYCLES_24 = 6, //
parameter NUM_CYCLES_25 = 6, //
parameter NUM_CYCLES_26 = 6, //
parameter NUM_CYCLES_27 = 6, //
parameter NUM_CYCLES_28 = 6, //
parameter NUM_CYCLES_29 = 6, //
parameter NUM_CYCLES_30 = 6, //
parameter NUM_CYCLES_31 = 6, //
// parameter CMD0_ADDR = 'h0800, // AXI write to command sequence memory
// parameter CMD0_ADDR_MASK = 'h1800, // AXI read address mask for the command sequence memory
parameter MCNTRL_PS_ADDR= 'h100,
parameter MCNTRL_PS_MASK= 'h7e0, // both channels 0 and 1
parameter MCNTRL_PS_STATUS_REG_ADDR= 'h2,
parameter MCNTRL_PS_EN_RST= 'h0,
parameter MCNTRL_PS_CMD= 'h1,
parameter MCNTRL_PS_STATUS_CNTRL= 'h2,
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over)
parameter MCNTRL_SCANLINE_CHN1_ADDR= 'h120,
parameter MCNTRL_SCANLINE_CHN3_ADDR= 'h130,
parameter MCNTRL_SCANLINE_MASK= 'h7f0, // both channels 0 and 1
parameter MCNTRL_SCANLINE_MODE= 'h0, // set mode register: {extra_pages[1:0],enable,!reset}
parameter MCNTRL_SCANLINE_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_SCANLINE_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_SCANLINE_FRAME_SIZE= 'h3, // 22-bit frame start address increment (3 CA LSBs==0. BA==0)
parameter MCNTRL_SCANLINE_FRAME_LAST= 'h4, // 16-bit last frame number in the buffer
parameter MCNTRL_SCANLINE_FRAME_FULL_WIDTH= 'h5, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_SCANLINE_WINDOW_WH= 'h6, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_SCANLINE_WINDOW_X0Y0= 'h7, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_SCANLINE_WINDOW_STARTXY= 'h8, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR= 'h4,
parameter MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR= 'h6,
parameter MCNTRL_SCANLINE_PENDING_CNTR_BITS= 2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_SCANLINE_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_CHN2_ADDR= 'h140,
parameter MCNTRL_TILED_CHN4_ADDR= 'h150,
parameter MCNTRL_TILED_MASK= 'h7f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_SIZE= 'h3, // 22-bit frame start address increment (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_LAST= 'h4, // 16-bit last frame number in the buffer
parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h5, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_TILED_WINDOW_WH= 'h6, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_X0Y0= 'h7, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h8, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WHS= 'h9, // low byte - 6-bit tile width in 8-bursts, second byte - tile height (0 - > 64),
// 3-rd byte - vertical step (to control tile vertical overlap)
parameter MCNTRL_TILED_STATUS_REG_CHN2_ADDR= 'h5,
parameter MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h7,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
parameter BUFFER_DEPTH32= 10, // Block rum buffer depth on a 32-bit port
// bits in mode control word
parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
parameter MCONTR_LINTILE_EN = 1, // enable requests
parameter MCONTR_LINTILE_WRITE = 2, // write to memory mode
parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
parameter MCNTRL_TEST01_MASK= 'h7f0,
parameter MCNTRL_TEST01_CHN1_MODE= 'h2, // set mode register for channel 5
parameter MCNTRL_TEST01_CHN1_STATUS_CNTRL= 'h3, // control status reporting for channel 5
parameter MCNTRL_TEST01_CHN2_MODE= 'h4, // set mode register for channel 2
parameter MCNTRL_TEST01_CHN2_STATUS_CNTRL= 'h5, // control status reporting for channel 2
parameter MCNTRL_TEST01_CHN3_MODE= 'h6, // set mode register for channel 3
parameter MCNTRL_TEST01_CHN3_STATUS_CNTRL= 'h7, // control status reporting for channel 3
parameter MCNTRL_TEST01_CHN4_MODE= 'h8, // set mode register for channel 4
parameter MCNTRL_TEST01_CHN4_STATUS_CNTRL= 'h9, // control status reporting for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN1_ADDR= 'h3c, // status/readback register for channel 2
parameter MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3d, // status/readback register for channel 3
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f, // status/readback register for channel 4
parameter MCONTR_SENS_BASE = 'h680, // .. 'h6bf
parameter MCONTR_SENS_INC = 'h10,
parameter MCONTR_CMPRS_BASE = 'h6c0, // .. 'h6ff
parameter MCONTR_CMPRS_INC = 'h10,
parameter MCONTR_SENS_STATUS_BASE = 'h28, // .. 'h2b
parameter MCONTR_SENS_STATUS_INC = 'h1,
parameter MCONTR_CMPRS_STATUS_BASE = 'h2c, // .. 'h2f
parameter MCONTR_CMPRS_STATUS_INC = 'h1,
// membridge module parameters
parameter MEMBRIDGE_ADDR= 'h200,
parameter MEMBRIDGE_MASK= 'h7f0,
parameter MEMBRIDGE_CTRL= 'h0, // bit 0 - enable, bits[2:1]: 01 - start, 11 - start and reset address
parameter MEMBRIDGE_STATUS_CNTRL= 'h1,
parameter MEMBRIDGE_LO_ADDR64= 'h2, // low address of the system memory, in 64-bit words (<<3 to get byte address)
parameter MEMBRIDGE_SIZE64= 'h3, // size of the system memory range (access will roll over to lo_addr
parameter MEMBRIDGE_START64= 'h4, // start address relative to lo_addr
parameter MEMBRIDGE_LEN64= 'h5, // full length of transfer in 64-bit words
parameter MEMBRIDGE_WIDTH64= 'h6, // frame width in 64-bit words (partial last page in each line)
parameter MEMBRIDGE_MODE= 'h7, // frame width in 64-bit words (partial last page in each line)
parameter MEMBRIDGE_STATUS_REG= 'h3b,
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0, // late/early WRITE commands (to adjust timing by 1 SDCLK period)
parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR
parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x20, x22, x24, x26
parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor
parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h20, 'h22, 'h24, 'h26
parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h21, 'h23, 'h25, 'h27
parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels
parameter HISTOGRAM_RAM_MODE = "BUF32", // "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter SENS_NUM_SUBCHN = 3, // number of subchannels for his sensor ports (1..4)
parameter SENS_GAMMA_BUFFER = 0, // 1 - use "shadow" table for clean switching, 0 - single table per channel
// parameters defining address map
parameter SENSOR_CTRL_RADDR = 0, // relative to SENSOR_GROUP_ADDR
parameter SENSOR_CTRL_ADDR_MASK = 'h7ff, //
// bits of the SENSOR mode register
parameter SENSOR_MODE_WIDTH = 10,
parameter SENSOR_HIST_EN_BITS = 0, // 0..3 1 - enable histogram modules, disable after processing the started frame
parameter SENSOR_HIST_NRST_BITS = 4, // 0 - immediately reset all histogram modules
parameter SENSOR_CHN_EN_BIT = 8, // 1 - this enable channel
parameter SENSOR_16BIT_BIT = 9, // 0 - 8 bpp mode, 1 - 16 bpp (bypass gamma). Gamma-processed data is still used for histograms
parameter SENSI2C_CTRL_RADDR = 2, // 302..'h303
parameter SENSI2C_CTRL_MASK = 'h7fe,
// sensor_i2c_io relative control register addresses
parameter SENSI2C_CTRL = 'h0,
// Control register bits
parameter SENSI2C_CMD_RESET = 14, // [14] reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
parameter SENSI2C_CMD_RUN = 13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
parameter SENSI2C_CMD_RUN_PBITS = 1,
parameter SENSI2C_CMD_BYTES = 11, // if 1, use [10:9] to set command bytes to send after slave address (0..3)
parameter SENSI2C_CMD_BYTES_PBITS = 2,
parameter SENSI2C_CMD_DLY = 8, // [7:0] - duration of quater i2c cycle (if 0, [3:0] control SCL+SDA)
parameter SENSI2C_CMD_DLY_PBITS = 8,
// direct control of SDA/SCL mutually exclusive with DLY control, disabled by running i2c
parameter SENSI2C_CMD_SCL = 16, // [17:16] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL
parameter SENSI2C_CMD_SCL_WIDTH = 2,
parameter SENSI2C_CMD_SDA = 18, // [19:18] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA,
parameter SENSI2C_CMD_SDA_WIDTH = 2,
parameter SENSI2C_STATUS = 'h1,
parameter SENS_SYNC_RADDR = 'h4,
parameter SENS_SYNC_MASK = 'h7fc,
// 2 locations reserved for control/status (if they will be needed)
parameter SENS_SYNC_MULT = 'h2, // relative register address to write number of frames to combine in one (minus 1, '0' - each farme)
parameter SENS_SYNC_LATE = 'h3, // number of lines to delay late frame sync
parameter SENS_GAMMA_RADDR = 'h38, // 'h38..'h3b was 4,
parameter SENS_GAMMA_ADDR_MASK = 'h7fc,
// sens_gamma registers
parameter SENS_GAMMA_CTRL = 'h0,
parameter SENS_GAMMA_ADDR_DATA = 'h1, // bit 20 ==1 - table address, bit 20==0 - table data (18 bits)
parameter SENS_GAMMA_HEIGHT01 = 'h2, // bits [15:0] - height minus 1 of image 0, [31:16] - height-1 of image1
parameter SENS_GAMMA_HEIGHT2 = 'h3, // bits [15:0] - height minus 1 of image 2 ( no need for image 3)
// bits of the SENS_GAMMA_CTRL mode register
parameter SENS_GAMMA_MODE_WIDTH = 5, // does not include trig
parameter SENS_GAMMA_MODE_BAYER = 0,
parameter SENS_GAMMA_MODE_PAGE = 2,
parameter SENS_GAMMA_MODE_EN = 3,
parameter SENS_GAMMA_MODE_REPET = 4,
parameter SENS_GAMMA_MODE_TRIG = 5,
// Vignetting correction / pixel value scaling - controlled via single data word (same as in 252), some of bits [23:16]
// are used to select register, bits 25:24 - select sub-frame
parameter SENS_LENS_RADDR = 'h3c,
parameter SENS_LENS_ADDR_MASK = 'h7fc,
parameter SENS_LENS_COEFF = 'h3, // set vignetting/scale coefficients (
parameter SENS_LENS_AX = 'h00, // 00000...
parameter SENS_LENS_AX_MASK = 'hf8,
parameter SENS_LENS_AY = 'h08, // 00001...
parameter SENS_LENS_AY_MASK = 'hf8,
parameter SENS_LENS_C = 'h10, // 00010...
parameter SENS_LENS_C_MASK = 'hf8,
parameter SENS_LENS_BX = 'h20, // 001.....
parameter SENS_LENS_BX_MASK = 'he0,
parameter SENS_LENS_BY = 'h40, // 010.....
parameter SENS_LENS_BY_MASK = 'he0,
parameter SENS_LENS_SCALES = 'h60, // 01100...
parameter SENS_LENS_SCALES_MASK = 'hf8,
parameter SENS_LENS_FAT0_IN = 'h68, // 01101000
parameter SENS_LENS_FAT0_IN_MASK = 'hff,
parameter SENS_LENS_FAT0_OUT = 'h69, // 01101001
parameter SENS_LENS_FAT0_OUT_MASK = 'hff,
parameter SENS_LENS_POST_SCALE = 'h6a, // 01101010
parameter SENS_LENS_POST_SCALE_MASK = 'hff,
parameter SENSIO_RADDR = 8, //'h408 .. 'h40f
parameter SENSIO_ADDR_MASK = 'h7f8,
// sens_parallel12 registers
parameter SENSIO_CTRL = 'h0,
// SENSIO_CTRL register bits
parameter SENS_CTRL_MRST = 0, // 1: 0
parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
parameter SENS_CTRL_LD_DLY = 10, // 10
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
// SENSIO_JTAG register bits
parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
parameter SENSI2C_ABS_RADDR = 'h10, // 'h410..'h41f
parameter SENSI2C_REL_RADDR = 'h20, // 'h420..'h42f
parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
// sens_hist registers (relative to SENSOR_GROUP_ADDR)
parameter HISTOGRAM_RADDR0 = 'h30, //
parameter HISTOGRAM_RADDR1 = 'h32, //
parameter HISTOGRAM_RADDR2 = 'h34, //
parameter HISTOGRAM_RADDR3 = 'h36, //
parameter HISTOGRAM_ADDR_MASK = 'h7fe, // for each channel
// sens_hist registers
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
//sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12,
parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_SLEW = "SLOW",
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 4'd5, // 7,
// other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0,
parameter HIST_SAXI_MODE_WIDTH = 8,
parameter HIST_SAXI_EN = 0,
parameter HIST_SAXI_NRESET = 1,
parameter HIST_CONFIRM_WRITE = 2, // wait write confirmation for each block
// bit 3 is not used
parameter HIST_SAXI_AWCACHE = 4, // ..7 Write 4'h3 there, cache mode (4 bits, default 4'h3)
parameter HIST_SAXI_MODE_ADDR_MASK = 'h7ff,
parameter NUM_FRAME_BITS = 4, // number of bits use for frame number
// Other parameters
parameter SENS_SYNC_FBITS = 16, // number of bits in a frame counter for linescan mode
parameter SENS_SYNC_LBITS = 16, // number of bits in a line counter for sof_late output (limited by eof)
parameter SENS_SYNC_LATE_DFLT = 15, // number of lines to delay late frame sync
parameter SENS_SYNC_MINBITS = 8, // number of bits to enforce minimal frame period
parameter SENS_SYNC_MINPER = 130, // minimal frame period (in pclk/mclk?)
// sens_parallel12 other parameters
// parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter PXD_SLEW = "SLOW",
`ifdef use200Mhz
parameter real SENS_REFCLK_FREQUENCY = 300.0, // same as REFCLK_FREQUENCY
`else
parameter real SENS_REFCLK_FREQUENCY = 200.0,
`endif
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_IPCLK_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS2 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
parameter CMPRS_BASE_INC = 'h10,
parameter CMPRS_AFIMUX_RADDR0= 'h40, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
parameter CMPRS_AFIMUX_RADDR1= 'h50, // relative to CMPRS_NUM_AFI_CHN ( 16 addr)
parameter CMPRS_AFIMUX_MASK= 'h7f0,
parameter CMPRS_STATUS_REG_BASE= 'h10,
parameter CMPRS_HIFREQ_REG_BASE= 'h14,
parameter CMPRS_AFIMUX_REG_ADDR0= 'h18, // Uses 4 locations
parameter CMPRS_AFIMUX_REG_ADDR1= 'h1c, // Uses 4 locations
parameter CMPRS_STATUS_REG_INC= 1,
parameter CMPRS_HIFREQ_REG_INC= 1,
parameter CMPRS_MASK= 'h7f8,
parameter CMPRS_CONTROL_REG= 0,
parameter CMPRS_STATUS_CNTRL= 1,
parameter CMPRS_FORMAT= 2,
parameter CMPRS_COLOR_SATURATION= 3,
parameter CMPRS_CORING_MODE= 4,
parameter CMPRS_TABLES= 6, // 6..7
// Bit-fields in compressor control word
parameter CMPRS_CBIT_RUN = 2, // bit # to control compressor run modes
parameter CMPRS_CBIT_RUN_BITS = 2, // number of bits to control compressor run modes
parameter CMPRS_CBIT_QBANK = 6, // bit # to control quantization table page
parameter CMPRS_CBIT_QBANK_BITS = 3, // number of bits to control quantization table page
parameter CMPRS_CBIT_DCSUB = 8, // bit # to control extracting DC components bypassing DCT
parameter CMPRS_CBIT_DCSUB_BITS = 1, // bit # to control extracting DC components bypassing DCT
parameter CMPRS_CBIT_CMODE = 13, // bit # to control compressor color modes
parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
parameter CMPRS_CBIT_FOCUS_BITS = 2, // number of bits to control compressor focus display mode
// compressor bit-fields decode
parameter CMPRS_CBIT_RUN_RST = 2'h0, // reset compressor, stop immediately
// parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
parameter CMPRS_CBIT_RUN_STANDALONE = 2'h2, // enable compressor, compress single frame from memory (async)
parameter CMPRS_CBIT_RUN_ENABLE = 2'h3, // enable compressor, enable synchronous compression mode
parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original
parameter CMPRS_CBIT_CMODE_JP46DC = 4'h3, // jp4, 6 blocks, dc -improved
parameter CMPRS_CBIT_CMODE_JPEG20 = 4'h4, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
parameter CMPRS_CBIT_CMODE_JP4 = 4'h5, // jp4, 4 blocks, dc-improved
parameter CMPRS_CBIT_CMODE_JP4DC = 4'h6, // jp4, 4 blocks, dc-improved
parameter CMPRS_CBIT_CMODE_JP4DIFF = 4'h7, // jp4, 4 blocks, differential
parameter CMPRS_CBIT_CMODE_JP4DIFFHDR = 4'h8, // jp4, 4 blocks, differential, hdr
parameter CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 4'h9, // jp4, 4 blocks, differential, divide by 2
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer
parameter CMPRS_COLOR20 = 1, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer (not implemented)
parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBRM1 = 13, // bit # of number of macroblock rows minus 1 field in format word
parameter CMPRS_FRMT_MBRM1_BITS = 13, // number of bits in number of macroblock rows minus 1 field in format word
parameter CMPRS_FRMT_LMARG = 26, // bit # of left margin field in format word
parameter CMPRS_FRMT_LMARG_BITS = 5, // number of bits in left margin field in format word
parameter CMPRS_CSAT_CB = 0, // bit # of number of blue scale field in color saturation word
parameter CMPRS_CSAT_CB_BITS = 10, // number of bits in blue scale field in color saturation word
parameter CMPRS_CSAT_CR = 12, // bit # of number of red scale field in color saturation word
parameter CMPRS_CSAT_CR_BITS = 10, // number of bits in red scale field in color saturation word
parameter CMPRS_CORING_BITS = 3, // number of bits in coring mode
parameter CMPRS_TIMEOUT_BITS= 12,
parameter CMPRS_TIMEOUT= 1000, // mclk cycles
parameter CMPRS_AFIMUX_EN= 'h0, // enables (gl;obal and per-channel)
parameter CMPRS_AFIMUX_RST= 'h1, // per-channel resets
parameter CMPRS_AFIMUX_MODE= 'h2, // per-channel select - which register to return as status
parameter CMPRS_AFIMUX_STATUS_CNTRL= 'h4, // .. 'h7
parameter CMPRS_AFIMUX_SA_LEN= 'h8, // .. 'hf
parameter CMPRS_AFIMUX_WIDTH = 26, // maximal for status: currently only works with 26)
parameter CMPRS_AFIMUX_CYCBITS = 3,
parameter AFI_MUX_BUF_LATENCY = 4'd2, // buffers read latency from fifo_ren* to fifo_rdata* valid : 2 if no register layers are used
// GPIO control : 'h700..'h701, status: 'h30
parameter integer GPIO_DRIVE = 12,
parameter GPIO_ADDR = 'h700, // .701
parameter GPIO_MASK = 'h7fe,
parameter GPIO_STATUS_REG_ADDR = 'h30, // address where status can be read out (10 GPIO inputs)
parameter GPIO_IBUF_LOW_PWR = "TRUE",
parameter GPIO_IOSTANDARD = "LVCMOS15", // power is 1.5V
parameter GPIO_SLEW = "SLOW",
parameter GPIO_SET_PINS = 0, // Set GPIO output state, give control for some bits to other modules
parameter GPIO_SET_STATUS = 1, // set status mode
parameter GPIO_N = 10, // number of GPIO bits to control
parameter GPIO_PORTEN = 24, // bit number to control port enables (up from this)
// Timing (rtc+camsync) parameters
parameter RTC_ADDR= 'h704, // 'h707
parameter CAMSYNC_ADDR = 'h708, // 'h70f
parameter RTC_STATUS_REG_ADDR = 'h31, // (1 loc) address where status can be read out (currently just sequence # and alternating bit)
parameter RTC_SEC_USEC_ADDR = 'h32, // ..'h33 address where seconds of the snapshot can be read (microseconds - next address)
parameter RTC_MASK = 'h7fc,
parameter CAMSYNC_MASK = 'h7f8,
parameter CAMSYNC_MODE = 'h0,
parameter CAMSYNC_TRIG_SRC = 'h1, // setup trigger source
parameter CAMSYNC_TRIG_DST = 'h2, // setup trigger destination line(s)
parameter CAMSYNC_TRIG_PERIOD = 'h3, // setup output trigger period
parameter CAMSYNC_TRIG_DELAY0 = 'h4, // setup input trigger delay
parameter CAMSYNC_TRIG_DELAY1 = 'h5, // setup input trigger delay
parameter CAMSYNC_TRIG_DELAY2 = 'h6, // setup input trigger delay
parameter CAMSYNC_TRIG_DELAY3 = 'h7, // setup input trigger delay
parameter CAMSYNC_EN_BIT = 'h0, // enable module (0 - reset)
parameter CAMSYNC_SNDEN_BIT = 'h2, // enable writing ts_snd_en
parameter CAMSYNC_EXTERNAL_BIT = 'h4, // enable writing ts_external (0 - local timestamp in the frame header)
parameter CAMSYNC_TRIGGERED_BIT = 'h6, // triggered mode ( 0- async)
parameter CAMSYNC_MASTER_BIT = 'h9, // select a 2-bit master channel (master delay may be used as a flash delay)
parameter CAMSYNC_CHN_EN_BIT = 'he, // per-channel enable timestamp generation
parameter CAMSYNC_PRE_MAGIC = 6'b110100,
parameter CAMSYNC_POST_MAGIC = 6'b001101,
parameter RTC_MHZ= 25, // RTC input clock in MHz (should be interger number)
parameter RTC_BITC_PREDIV = 5, // number of bits to generate 2 MHz pulses counting refclk
parameter RTC_SET_USEC= 0, // 20-bit number of microseconds
parameter RTC_SET_SEC= 1, // 32-bit full number of seconds (und actually update timer)
parameter RTC_SET_CORR= 2, // write correction 16-bit signed
parameter RTC_SET_STATUS= 3, // generate an output pulse to take a snapshot
// Command sequencers parameters
parameter CMDFRAMESEQ_ADDR_BASE= 'h780,
parameter CMDFRAMESEQ_ADDR_INC= 'h20,
parameter CMDFRAMESEQ_MASK= 'h7e0,
parameter CMDFRAMESEQ_DEPTH = 64, // 32/64/128
parameter CMDFRAMESEQ_ABS = 0,
parameter CMDFRAMESEQ_REL = 16,
parameter CMDFRAMESEQ_CTRL = 31,
parameter CMDFRAMESEQ_RST_BIT = 14,
parameter CMDFRAMESEQ_RUN_BIT = 13,
parameter CMDSEQMUX_ADDR = 'h702, // only status control
parameter CMDSEQMUX_MASK = 'h7ff,
parameter CMDSEQMUX_STATUS = 'h38,
// Logger parameters
parameter LOGGER_ADDR = 'h720, //..'h721
parameter LOGGER_STATUS = 'h722, // .. 'h722
parameter LOGGER_STATUS_REG_ADDR = 'h39, // just 1 location)
parameter LOGGER_MASK = 'h7fe,
parameter LOGGER_STATUS_MASK = 'h7ff,
parameter LOGGER_PAGE_IMU = 0, // 'h00..'h1f - overlaps with period/duration/halfperiod/config?
parameter LOGGER_PAGE_GPS = 1, // 'h20..'h3f
parameter LOGGER_PAGE_MSG = 2, // 'h40..'h5f
parameter LOGGER_PERIOD = 0,
parameter LOGGER_BIT_DURATION = 1,
parameter LOGGER_BIT_HALF_PERIOD = 2, //rs232 half bit period
parameter LOGGER_CONFIG = 3,
parameter LOGGER_CONF_IMU = 2,
parameter LOGGER_CONF_IMU_BITS = 2,
parameter LOGGER_CONF_GPS = 7,
parameter LOGGER_CONF_GPS_BITS = 4,
parameter LOGGER_CONF_MSG = 13,
parameter LOGGER_CONF_MSG_BITS = 5,
parameter LOGGER_CONF_SYN = 18, // 15,
parameter LOGGER_CONF_SYN_BITS = 4, // 1,
parameter LOGGER_CONF_EN = 20, // 17,
parameter LOGGER_CONF_EN_BITS = 1,
parameter LOGGER_CONF_DBG = 25, // 22,
parameter LOGGER_CONF_DBG_BITS = 4,
parameter MULT_SAXI_HALF_BRAM_IN = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
parameter MULT_SAXI_WLOG = 4, // number of bits for the input data ( 3 - 8 bit, 4 - 16-bit, 5 - 32-bit
parameter MULT_SAXI_ADDR = 'h730, // ..'h737
parameter MULT_SAXI_CNTRL_ADDR = 'h738, // ..'h739
parameter MULT_SAXI_STATUS_REG = 'h34, //..'h37 uses 4 consecutive locations
parameter MULT_SAXI_HALF_BRAM = 1, // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
parameter MULT_SAXI_BSLOG0 = 4, // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1)
parameter MULT_SAXI_BSLOG1 = 4,
parameter MULT_SAXI_BSLOG2 = 4,
parameter MULT_SAXI_BSLOG3 = 4,
parameter MULT_SAXI_MASK = 'h7f8, // 4 address/length pairs. In bytes, but lower bits are set to 0?
parameter MULT_SAXI_CNTRL_MASK = 'h7fe, // mode and status - 2 locations
parameter MULT_SAXI_AWCACHE = 4'h3, //..7 cache mode (4 bits, default 4'h3)
parameter MULT_SAXI_ADV_WR = 4, // number of clock cycles before end of write to genearte adv_wr_done
parameter MULT_SAXI_ADV_RD = 3, // number of clock cycles before end of write to genearte adv_wr_done
// Clock management (input, generation, buffering)
parameter CLK_ADDR = 'h728, // ..'h729
parameter CLK_MASK = 'h7fe, //
parameter CLK_STATUS_REG_ADDR = 'h3a, //
parameter CLK_CNTRL = 0,
parameter CLK_STATUS = 1,
parameter CLKIN_PERIOD_AXIHP = 20, //ns >1.25, 600<Fvco<1200
parameter DIVCLK_DIVIDE_AXIHP = 1,
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKOUT_DIV_AXIHP = 6, // To get 150MHz for the reference clock
parameter BUF_CLK1X_AXIHP = "BUFG", // "BUFG", "BUFH", "BUFR", "NONE"
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG",
parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
parameter PHASE_CLK2X_XCLK = 0.000,
parameter BUF_CLK1X_XCLK = "BUFG",
parameter BUF_CLK1X_XCLK2X = "BUFG",
parameter CLKIN_PERIOD_SYNC = 20, // 50MHz
parameter DIVCLK_DIVIDE_SYNC = 1,
parameter CLKFBOUT_MULT_SYNC = 20, // 50*20=1000 MHz
parameter CLKOUT_DIV_SYNC = 10, // 100 MHz
parameter BUF_CLK1X_SYNC = "BUFG",
parameter MEMCLK_CAPACITANCE = "DONT_CARE",
parameter MEMCLK_IBUF_DELAY_VALUE = "0",
parameter MEMCLK_IBUF_LOW_PWR = "TRUE",
parameter MEMCLK_IFD_DELAY_VALUE = "AUTO",
parameter MEMCLK_IOSTANDARD = "SSTL15",
parameter FFCLK0_CAPACITANCE = "DONT_CARE",
parameter FFCLK0_DIFF_TERM = "FALSE",
parameter FFCLK0_DQS_BIAS = "FALSE",
parameter FFCLK0_IBUF_DELAY_VALUE = "0",
parameter FFCLK0_IBUF_LOW_PWR = "TRUE",
parameter FFCLK0_IFD_DELAY_VALUE = "AUTO",
parameter FFCLK0_IOSTANDARD = "RSDS_25",
parameter FFCLK1_CAPACITANCE = "DONT_CARE",
parameter FFCLK1_DIFF_TERM = "FALSE",
parameter FFCLK1_DQS_BIAS = "FALSE",
parameter FFCLK1_IBUF_DELAY_VALUE = "0",
parameter FFCLK1_IBUF_LOW_PWR = "TRUE",
parameter FFCLK1_IFD_DELAY_VALUE = "AUTO",
parameter FFCLK1_IOSTANDARD = "RSDS_25"
\ No newline at end of file
includes/x393_simulation_parameters.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_simulation_parameters.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Simulation-specific parameters for the x393
*
* Copyright (c) 2015 Elphel, Inc.
* x393_simulation_parameters.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_simulation_parameters.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
, // to continue previous parameter list
parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,
parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,
parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1
parameter integer AXI_TASK_HOLD=1.0,
// parameter [1:0] DEFAULT_STATUS_MODE=3,
parameter SIMUL_AXI_READ_WIDTH=16,
parameter MEMCLK_PERIOD = 5.0,
parameter FCLK0_PERIOD = 41.667, // 10.417, 24MHz
parameter FCLK1_PERIOD = 0.0,
// parameter SENSOR12BITS_LLINE = 192, // 1664;// line duration in clocks
// parameter SENSOR12BITS_NCOLS = 66, //58; //56; // 129; //128; //1288;
// parameter SENSOR12BITS_NROWS = 18, // 16; // 1032;
// parameter SENSOR12BITS_NROWB = 1, // number of "blank rows" from vact to 1-st hact
// parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
// parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
parameter SENSOR12BITS_NGPL = 8, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
//parameter tDDO = 10; // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TMD = 4, //
parameter SENSOR12BITS_TDDO = 2, // some confusion here - let's assume that it is from DCLK to Data out
parameter SENSOR12BITS_TDDO1 = 5, //
// parameter SENSOR12BITS_TRIGDLY = 8, // delay between trigger input and start of output (VACT) in lines
// parameter SENSOR12BITS_RAMP = 1, // 1 - ramp, 0 - random (now - sensor.dat)
// parameter SENSOR12BITS_NEW_BAYER = 0, // 0 - "old" tiles (16x16, 1 - new - (18x18)
parameter HISTOGRAM_LEFT = 0, // 2; // left
parameter HISTOGRAM_TOP = 8, // 2, // top
parameter HISTOGRAM_WIDTH = 6, // width
parameter HISTOGRAM_HEIGHT = 6, // height
parameter HISTOGRAM_STRAT_PAGE = 20'h12345,
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
parameter WOI_WIDTH= 64,
parameter QUADRANTS_PXD_HACT_VACT = 6'h01 // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
\ No newline at end of file
includes/x393_tasks01.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_tasks01.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Simulation tasks for the x393 (low level)
*
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks01.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks01.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// Low-level tasks
// alternative way to check for empty read queue (without a separate counter)
task write_contol_register;
input [29:0] reg_addr;
// input integer reg_addr;
input [31:0] data;
begin
axi_write_single_w(CONTROL_ADDR+reg_addr, data);
end
endtask
task read_contol_register;
input [29:0] reg_addr;
begin
read_and_wait_w(CONTROL_RBACK_ADDR+reg_addr);
end
endtask
task wait_read_queue_empty;
begin
wait (~rvalid && rready && (rid==LAST_ARID)); // nothing left in read queue?
SIMUL_AXI_FULL<=1'b0;
end
endtask
task axi_set_rd_lag;
input [3:0] lag;
begin
@(posedge CLK);
RD_LAG <= lag;
end
endtask
task axi_set_b_lag;
input [3:0] lag;
begin
@(posedge CLK);
B_LAG <= lag;
end
endtask
task read_and_wait_w;
input [29:0] address;
begin
read_and_wait ({address,2'b0});
end
endtask
task read_and_wait;
input [31:0] address;
begin
axi_read_addr(
GLOBAL_READ_ID, // id
address & 32'hfffffffc, // addr
4'h0, // len - single
1 // burst type - increment
);
GLOBAL_READ_ID <= GLOBAL_READ_ID+1;
wait (!CLK && rvalid && rready);
wait (CLK);
registered_rdata <= rdata;
wait (!CLK); // registered_rdata should be valid on exit
end
endtask
task axi_write_single_w; // address in bytes, not words
input [29:0] address;
input [31:0] data;
begin
`ifdef DEBUG_WR_SINGLE
$display("axi_write_single_w %h:%h @ %t",address,data,$time);
`endif
axi_write_single ({address,2'b0},data);
end
endtask
task axi_write_single; // address in bytes, not words
input [31:0] address;
input [31:0] data;
begin
axi_write_addr_data(
GLOBAL_WRITE_ID, // id
// address << 2, // addr
address & 32'hfffffffc, // addr
data,
4'h0, // len - single
1, // burst type - increment
1'b1, // data_en
4'hf, // wstrb
1'b1 // last
);
GLOBAL_WRITE_ID <= GLOBAL_WRITE_ID+1;
#0.1; // without this delay axi_write_addr_data() used old value of GLOBAL_WRITE_ID
end
endtask
task axi_write_addr_data;
input [11:0] id;
input [31:0] addr;
input [31:0] data;
input [ 3:0] len;
input [ 1:0] burst;
input data_en; // if 0 - do not send data, only address
input [ 3:0] wstrb;
input last;
reg data_sent;
// wire data_sent_d;
// assign #(.1) data_sent_d= data_sent;
begin
wait (!CLK && AW_READY);
AWID_IN_r <= id;
AWADDR_IN_r <= addr;
AWLEN_IN_r <= len;
AWSIZE_IN_r <= 3'b010;
AWBURST_IN_r <= burst;
AW_SET_CMD_r <= 1'b1;
if (data_en && W_READY) begin
WID_IN_r <= id;
WDATA_IN_r <= data;
WSTRB_IN_r <= wstrb;
WLAST_IN_r <= last;
W_SET_CMD_r <= 1'b1;
data_sent <= 1'b1;
end else begin
data_sent <= 1'b0;
end
DEBUG1 <=1'b1;
wait (CLK);
DEBUG1 <=1'b0;
AWID_IN_r <= 'hz;
AWADDR_IN_r <= 'hz;
AWLEN_IN_r <= 'hz;
AWSIZE_IN_r <= 'hz;
AWBURST_IN_r <= 'hz;
AW_SET_CMD_r <= 1'b0;
DEBUG2 <=1'b1;
if (data_sent) begin
WID_IN_r <= 'hz;
WDATA_IN_r <= 'hz;
WSTRB_IN_r <= 'hz;
WLAST_IN_r <= 'hz;
W_SET_CMD_r <= 1'b0;
end
// Now sent data if it was not sent simultaneously with the address
if (data_en && !data_sent) begin
DEBUG3 <=1'b1;
wait (!CLK && W_READY);
DEBUG3 <=1'b0;
WID_IN_r <= id;
WDATA_IN_r <= data;
WSTRB_IN_r <= wstrb;
WLAST_IN_r <= last;
W_SET_CMD_r <= 1'b1;
wait (CLK);
DEBUG3 <=1'bx;
WID_IN_r <= 'hz;
WDATA_IN_r <= 'hz;
WSTRB_IN_r <= 'hz;
WLAST_IN_r <= 'hz;
W_SET_CMD_r <= 1'b0;
end
DEBUG2 <=1'b0;
#0.1;
data_sent <= 1'b0;
#0.1;
end
endtask
task axi_write_data;
input [11:0] id;
input [31:0] data;
input [ 3:0] wstrb;
input last;
begin
wait (!CLK && W_READY);
WID_IN_r <= id;
WDATA_IN_r <= data;
WSTRB_IN_r <= wstrb;
WLAST_IN_r <= last;
W_SET_CMD_r <= 1'b1;
wait (CLK);
WID_IN_r <= 12'hz;
WDATA_IN_r <= 'hz;
WSTRB_IN_r <= 4'hz;
WLAST_IN_r <= 1'bz;
W_SET_CMD_r <= 1'b0;
#0.1;
end
endtask
task axi_read_addr;
input [11:0] id;
input [31:0] addr;
input [ 3:0] len;
input [ 1:0] burst;
begin
wait (!CLK && AR_READY);
ARID_IN_r <= id;
ARADDR_IN_r <= addr;
ARLEN_IN_r <= len;
ARSIZE_IN_r <= 3'b010;
ARBURST_IN_r <= burst;
AR_SET_CMD_r <= 1'b1;
wait (CLK);
ARID_IN_r <= 12'hz;
ARADDR_IN_r <= 'hz;
ARLEN_IN_r <= 4'hz;
ARSIZE_IN_r <= 3'hz;
ARBURST_IN_r <= 2'hz;
AR_SET_CMD_r <= 1'b0;
LAST_ARID <= id;
NUM_WORDS_EXPECTED <= NUM_WORDS_EXPECTED+len+1;
end
endtask
includes/x393_tasks_afi.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_tasks_afi.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Simulation tasks for the AXI_HP (AFI)
*
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_afi.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks_afi.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
task membridge_setup;
input [28:0] len64; // number of 64-bit words to transfer
input [28:0] width64; // frame width in 64-bit words
input [28:0] start64; // relative start address of the transfer (set to 0 when writing lo_addr64)
input [28:0] lo_addr64; // low address of the system memory range, in 64-bit words
input [28:0] size64; // size of the system memory range in 64-bit words
begin
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_LO_ADDR64, {3'b0,lo_addr64});
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_SIZE64, {3'b0,size64});
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_START64, {3'b0,start64});
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_LEN64, {3'b0,len64});
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_WIDTH64, {3'b0,width64});
end
endtask
task membridge_start;
input continue; // 0 start from start64, 1 - continue from where it was
begin
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {29'b0,continue,2'b11});
end
endtask
task membridge_en; // SuppressThisWarning VEditor - may be unused
input en; // not needed to start, pauses axi if set to 0 whil running, resets "done" status bit
begin
write_contol_register(MEMBRIDGE_ADDR + MEMBRIDGE_CTRL, {31'b0,en});
end
endtask
task afi_setup;
input [1:0] port_num;
begin
afi_write_reg(port_num, 'h0, 0); // AFI_RDCHAN_CTRL
afi_write_reg(port_num, 'h4, 7); // AFI_RDCHAN_ISSUINGCAP
afi_write_reg(port_num, 'h8, 0); // AFI_RDQOS
//afi_write_reg(port_num, 'hc, 0); // AFI_RDDATAFIFO_LEVEL
//afi_write_reg(port_num, 'h10, 0); // AFI_RDDEBUG
afi_write_reg(port_num, 'h14, 'hf00); // AFI_WRCHAN_CTRL
afi_write_reg(port_num, 'h18, 7); // AFI_WRCHAN_ISSUINGCAP
afi_write_reg(port_num, 'h1c, 0); // AFI_WRQOS
//afi_write_reg(port_num, 'h20, 0); // AFI_WRDATAFIFO_LEVEL
//afi_write_reg(port_num, 'h24, 0); // AFI_WRDEBUG
end
endtask
task afi_write_reg;
input [1:0] port_num;
input integer rel_baddr; // relative byte address
input [31:0] data;
begin
ps_write_reg(32'hf8008000+ (port_num << 12) + (rel_baddr & 'hfffffffc), data);
end
endtask
task afi_read_reg; // SuppressThisWarning VEditor - may be unused
input [1:0] port_num;
input integer rel_baddr; // relative byte address
input verbose;
begin
ps_read_reg(32'hf8008000+ (port_num << 12) + (rel_baddr & 'hfffffffc), verbose);
end
endtask
task ps_write_reg;
input [31:0] ps_reg_addr;
input [31:0] ps_reg_data;
begin
@(posedge HCLK);
PS_REG_ADDR <= ps_reg_addr;
PS_REG_DIN <= ps_reg_data;
PS_REG_WR <= 1'b1;
@(posedge HCLK);
PS_REG_ADDR <= 'bx;
PS_REG_DIN <= 'bx;
PS_REG_WR <= 1'b0;
end
endtask
task ps_read_reg;
input [31:0] ps_reg_addr;
input verbose;
begin
@(posedge HCLK);
PS_REG_ADDR <= ps_reg_addr;
PS_REG_RD <= 1'b1;
@(posedge HCLK);
PS_REG_ADDR <= 'bx;
PS_REG_DIN <= 'bx;
PS_REG_WR <= 1'b0;
@(negedge HCLK);
if (verbose) begin
$display("ps_read_reg(%x) -> %x @%t",ps_reg_addr,PS_RDATA,$time);
end
end
endtask
\ No newline at end of file
includes/x393_tasks_mcntrl_buffers.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_tasks_mcntrl_buffers.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Simulation tasks for software reading/writing (with test patterns)
* of the block buffers.
*
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_mcntrl_buffers.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks_mcntrl_buffers.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
/*
task write_block_scanline_chn; // S uppressThisWarning VEditor : may be unused
input integer chn; // buffer channel
input [1:0] page;
// input integer num_words; // number of words to write (will be rounded up to multiple of 16)
input [NUM_XFER_BITS:0] num_bursts; // number of 8-bursts to write (will be rounded up to multiple of 16)
input integer startX;
input integer startY;
reg [29:0] start_addr;
begin
$display("====== write_block_scanline_chn:%d page: %x X=0x%x Y=0x%x num=%d @%t", chn, page, startX, startY,num_words, $time);
case (chn)
1: start_addr=MCONTR_BUF0_WR_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel for write_block_scanline_chn = %d @%t", chn, $time);
start_addr = MCONTR_BUF0_WR_ADDR+ (page << 8);
end
endcase
// write_block_incremtal (start_addr, num_words, (startX<<2) + (startY<<16)); // 1 of startX is 8x16 bit, 16 bytes or 4 32-bit words
write_block_incremtal (start_addr, num_bursts << 2, (startX<<2) + (startY<<16)); // 1 of startX is 8x16 bit, 16 bytes or 4 32-bit words
end
endtask
*/
task write_block_incremtal;
input [29:0] start_word_address;
input integer num_words; // number of words to write (will be rounded up to multiple of 16)
input integer start_value;
integer i, j;
begin
$display("**** write_block_buf @%t", $time);
for (i = 0; i < num_words; i = i + 16) begin
axi_write_addr_data(
i, // id
{start_word_address,2'b0}+( i << 2),
start_value+i,
4'hf, // len
1, // burst type - increment
1'b1, // data_en
4'hf, // wstrb
1'b0 // last
);
// $display("+Write block data (addr:data): 0x%x:0x%08x @%t", i, i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24), $time);
$display("+Write block incremental (addr:data): 0x%x:0x%08x @%t", i, start_value+i, $time);
for (j = 1; j < 16; j = j + 1) begin
axi_write_data(
i, // id
start_value+i+j,
4'hf, // wstrb
(j == 15) ? 1'b1 : 1'b0 // last
);
$display(" Write block incremental (addr:data): 0x%08x:0x%x @%t", (i + j), start_value+i+j, $time);
end
end
end
endtask
task write_block_buf_chn; // S uppressThisWarning VEditor : may be unused
input integer chn; // buffer channel
input [1:0] page;
input integer num_words; // number of words to write (will be rounded up to multiple of 16)
reg [29:0] start_addr;
begin
case (chn)
0: start_addr=MCONTR_BUF0_WR_ADDR + (page << 8);
// 1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
2: start_addr=MCONTR_BUF2_WR_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
4: start_addr=MCONTR_BUF4_WR_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel (not 0,2,3,4) for write buffer = %d @%t", chn, $time);
start_addr = MCONTR_BUF0_WR_ADDR+ (page << 8);
end
endcase
write_block_buf (start_addr, num_words);
end
endtask
task write_block_buf;
input [29:0] start_word_address;
input integer num_words; // number of words to write (will be rounded up to multiple of 16)
integer i, j;
begin
$display("**** write_block_buf @%t", $time);
for (i = 0; i < num_words; i = i + 16) begin
axi_write_addr_data(
i, // id
{start_word_address,2'b0}+( i << 2),
// (MCONTR_BUF0_WR_ADDR + (page <<8)+ i) << 2, // addr
i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24),
4'hf, // len
1, // burst type - increment
1'b1, // data_en
4'hf, // wstrb
1'b0 // last
);
$display("+Write block data (addr:data): 0x%x:0x%08x @%t", i, i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24), $time);
for (j = 1; j < 16; j = j + 1) begin
axi_write_data(
i, // id
(i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24),
4'hf, // wstrb
(j == 15) ? 1'b1 : 1'b0 // last
);
$display(" Write block data (addr:data): 0x%08x:0x%x @%t", (i + j),
(i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24), $time);
end
end
end
endtask
// read memory
task read_block_buf_chn; // S uppressThisWarning VEditor : may be unused
// input integer chn; // buffer channel
input [3:0] chn; // buffer channel
input [1:0] page;
input integer num_read; // number of words to read (will be rounded up to multiple of 16)
input wait_done;
reg [29:0] start_addr;
begin
case (chn)
0: start_addr=MCONTR_BUF0_RD_ADDR + (page << 8);
2: start_addr=MCONTR_BUF2_RD_ADDR + (page << 8);
3: start_addr=MCONTR_BUF3_RD_ADDR + (page << 8);
4: start_addr=MCONTR_BUF4_RD_ADDR + (page << 8);
default: begin
$display("**** ERROR: Invalid channel (not 0,2,3,4) for read buffer = %d @%t", chn, $time);
start_addr = 30'b0+ (page << 8);
end
endcase
read_block_buf (start_addr, num_read, wait_done);
end
endtask
task read_block_buf;
input [29:0] start_word_address;
input integer num_read; // number of words to read (will be rounded up to multiple of 16)
input wait_done;
integer i; //,j;
begin
wait (~rstb);
SIMUL_AXI_FULL<=1'b0;
$display("**** read_block_buf @%t", $time);
axi_set_rd_lag(0);
for (i = 0; i < num_read; i = i + 16) begin
wait(arready);
// $display ("read_block_buf (0x%x) @%t",i,$time);
axi_read_addr(
i, // id
{start_word_address,2'b0}+( i << 2), // addr
4'hf, // len
1 // burst type - increment
);
end
if (wait_done) begin
// wait (AXI_RD_EMPTY);
wait_read_queue_empty;
end
end
endtask
includes/x393_tasks_mcntrl_en_dis_priority.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_tasks_mcntrl_en_dis_priority.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Simulation tasks for software reading/writing (with test patterns)
* of the block buffers.
*
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_mcntrl_en_dis_priority.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks_mcntrl_en_dis_priority.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
task enable_cmda;
input en;
begin
write_contol_register(MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_CMDA_EN + en, 0);
end
endtask
task enable_cke;
input en;
begin
write_contol_register(MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_CKE_EN + en, 0);
end
endtask
task activate_sdrst;
input en;
begin
write_contol_register(MCONTR_PHY_0BIT_ADDR + MCONTR_PHY_0BIT_SDRST_ACT + en, 0);
end
endtask
task enable_refresh;
input en;
begin
write_contol_register(MCONTR_TOP_0BIT_ADDR + MCONTR_TOP_0BIT_REFRESH_EN + en, 0);
end
endtask
task enable_memcntrl;
input en;
begin
write_contol_register(MCONTR_TOP_0BIT_ADDR + MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
end
endtask
task enable_memcntrl_channels;
input [15:0] chnen; // bit-per-channel, 1 - enable;
begin
ENABLED_CHANNELS = chnen; // currently enabled memory channels
write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,chnen});
end
endtask
task enable_memcntrl_en_dis;
input [3:0] chn;
input en;
begin
if (en) begin
ENABLED_CHANNELS = ENABLED_CHANNELS | (1<<chn);
end else begin
ENABLED_CHANNELS = ENABLED_CHANNELS & ~(1<<chn);
end
write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,ENABLED_CHANNELS});
end
endtask
task configure_channel_priority;
input [ 3:0] chn;
input [15:0] priority; // (higher is more important)
begin
write_contol_register(MCONTR_ARBIT_ADDR + chn, {16'b0,priority});
end
endtask
includes/x393_tasks_mcntrl_timing.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_tasks_mcntrl_timing.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Simulation tasks for programming I/O delays and other timing
* parameters in the memory controller
*
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_mcntrl_timing.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks_mcntrl_timing.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
task axi_set_same_delays; //SuppressThisWarning VEditor : may be unused
input [7:0] dq_idelay;
input [7:0] dq_odelay;
input [7:0] dqs_idelay;
input [7:0] dqs_odelay;
input [7:0] dm_odelay;
input [7:0] cmda_odelay;
begin
$display("SET DELAYS(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x) @ %t",
dq_idelay,dq_odelay,dqs_idelay,dqs_odelay,dm_odelay,cmda_odelay,$time);
axi_set_dq_idelay(dq_idelay);
axi_set_dq_odelay(dq_odelay);
axi_set_dqs_idelay(dqs_idelay);
axi_set_dqs_odelay(dqs_odelay);
axi_set_dm_odelay(dm_odelay);
axi_set_cmda_odelay(cmda_odelay);
end
endtask
task axi_set_dqs_odelay_nominal; //SuppressThisWarning VEditor : may be unused
begin
$display("axi_set_dqs_odelay_nominal(0x%x,0x%x) @ %t",
(DLY_LANE0_ODELAY >> (8<<3)) & 32'hff,
(DLY_LANE1_ODELAY >> (8<<3)) & 32'hff,
$time);
// axi_set_dqs_idelay(
write_contol_register(LD_DLY_LANE0_ODELAY + 8, (DLY_LANE0_ODELAY >> (8<<3)) & 32'hff);
write_contol_register(LD_DLY_LANE1_ODELAY + 8, (DLY_LANE1_ODELAY >> (8<<3)) & 32'hff);
write_contol_register(DLY_SET,0);
end
endtask
task axi_set_dqs_idelay_nominal; //SuppressThisWarning VEditor : may be unused
begin
// axi_set_dqs_idelay(
write_contol_register(LD_DLY_LANE0_IDELAY + 8, (DLY_LANE0_IDELAY >> (8<<3)) & 32'hff);
write_contol_register(LD_DLY_LANE1_IDELAY + 8, (DLY_LANE1_IDELAY >> (8<<3)) & 32'hff);
write_contol_register(DLY_SET,0);
end
endtask
task axi_set_dqs_idelay_wlv; //SuppressThisWarning VEditor : may be unused
begin
write_contol_register(LD_DLY_LANE0_IDELAY + 8, DLY_LANE0_DQS_WLV_IDELAY);
write_contol_register(LD_DLY_LANE1_IDELAY + 8, DLY_LANE1_DQS_WLV_IDELAY);
write_contol_register(DLY_SET,0);
end
endtask
task axi_set_delays; // set all individual delays
integer i;
begin
$display("axi_set_delays @ %t",$time);
for (i=0;i<10;i=i+1) begin
write_contol_register(LD_DLY_LANE0_ODELAY + i, (DLY_LANE0_ODELAY >> (i<<3)) & 32'hff);
end
for (i=0;i<9;i=i+1) begin
write_contol_register(LD_DLY_LANE0_IDELAY + i, (DLY_LANE0_IDELAY >> (i<<3)) & 32'hff);
end
for (i=0;i<10;i=i+1) begin
write_contol_register(LD_DLY_LANE1_ODELAY + i, (DLY_LANE1_ODELAY >> (i<<3)) & 32'hff);
end
for (i=0;i<9;i=i+1) begin
write_contol_register(LD_DLY_LANE1_IDELAY + i, (DLY_LANE1_IDELAY >> (i<<3)) & 32'hff);
end
for (i=0;i<32;i=i+1) begin
write_contol_register(LD_DLY_CMDA + i, (DLY_CMDA >> (i<<3)) & 32'hff);
end
// write_contol_register(DLY_SET,0);
axi_set_phase(DLY_PHASE); // also sets all delays
end
endtask
task axi_get_delays; // set all individual delays
integer i;
begin
$display("axi_get_delays @ %t",$time);
for (i=0;i<10;i=i+1) begin
read_contol_register(LD_DLY_LANE0_ODELAY + i);
end
for (i=0;i<9;i=i+1) begin
read_contol_register(LD_DLY_LANE0_IDELAY + i);
end
for (i=0;i<10;i=i+1) begin
read_contol_register(LD_DLY_LANE1_ODELAY + i);
end
for (i=0;i<9;i=i+1) begin
read_contol_register(LD_DLY_LANE1_IDELAY + i);
end
for (i=0;i<32;i=i+1) begin
read_contol_register(LD_DLY_CMDA + i);
end
read_contol_register(LD_DLY_PHASE);
end
endtask
task axi_set_dq_idelay; // sets same delay to all dq idelay
input [7:0] delay;
begin
$display("SET DQ IDELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_LANE0_IDELAY, 8, delay);
axi_set_multiple_delays(LD_DLY_LANE1_IDELAY, 8, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_dq_odelay;
input [7:0] delay;
begin
$display("SET DQ ODELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_LANE0_ODELAY, 8, delay);
axi_set_multiple_delays(LD_DLY_LANE1_ODELAY, 8, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_dqs_idelay;
input [7:0] delay;
begin
$display("SET DQS IDELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_LANE0_IDELAY + 8, 1, delay);
axi_set_multiple_delays(LD_DLY_LANE1_IDELAY + 8, 1, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_dqs_odelay;
input [7:0] delay;
begin
$display("SET DQS ODELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_LANE0_ODELAY + 8, 1, delay);
axi_set_multiple_delays(LD_DLY_LANE1_ODELAY + 8, 1, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_dm_odelay;
input [7:0] delay;
begin
$display("SET DQM IDELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_LANE0_ODELAY + 9, 1, delay);
axi_set_multiple_delays(LD_DLY_LANE1_ODELAY + 9, 1, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_cmda_odelay;
input [7:0] delay;
begin
$display("SET COMMAND and ADDRESS ODELAY=0x%x @ %t",delay,$time);
axi_set_multiple_delays(LD_DLY_CMDA, 32, delay);
write_contol_register(DLY_SET,0); // set all delays
end
endtask
task axi_set_multiple_delays;
input [29:0] reg_addr;
input integer number;
input [7:0] delay;
integer i;
begin
for (i=0;i<number;i=i+1) begin
write_contol_register(reg_addr + i, {24'b0,delay}); // control regiter address
end
end
endtask
task axi_set_phase;
input [PHASE_WIDTH-1:0] phase;
begin
$display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
write_contol_register(DLY_SET,0);
target_phase <= phase;
end
endtask
task axi_set_wbuf_delay;
input [3:0] delay;
begin
$display("SET WBUF DELAY to 0x%x @ %t",delay,$time);
write_contol_register(MCONTR_PHY_16BIT_ADDR+MCONTR_PHY_16BIT_WBUF_DELAY, {28'h0, delay});
end
endtask
// set dq /dqs tristate on/off patterns
task axi_set_tristate_patterns;
begin
$display("SET TRISTATE PATTERNS @ %t",$time);
write_contol_register(MCONTR_PHY_16BIT_ADDR +MCONTR_PHY_16BIT_PATTERNS_TRI,
{16'h0, DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
end
endtask
task axi_set_dqs_dqm_patterns;
begin
$display("SET DQS+DQM PATTERNS @ %t",$time);
// set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
write_contol_register(MCONTR_PHY_16BIT_ADDR + MCONTR_PHY_16BIT_PATTERNS,
32'h0055);
end
endtask
includes/x393_tasks_pio_sequences.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_tasks_pio_sequences.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Simulation tasks for programming memory transaction
* sequences (controlles by PS)
*
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_pio_sequences.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks_pio_sequences.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
task enable_reset_ps_pio; // control reset and enable of the PS PIO channel;
input en;
input rst;
begin
write_contol_register(MCNTRL_PS_ADDR + MCNTRL_PS_EN_RST, {30'b0,en,~rst});
end
endtask
task set_read_block;
input [ 2:0] ba;
input [14:0] ra;
input [ 9:0] ca;
input sel;
reg [29:0] cmd_addr;
reg [31:0] data;
integer i;
begin
cmd_addr <= MCONTR_CMD_WR_ADDR + READ_BLOCK_OFFSET;
// activate
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( ra[14:0], ba[2:0], 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// see if pause is needed . See when buffer read should be started - maybe before WR command
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// first read
// read
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 2, 0, 0, sel, 0, 0, 0, 1, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 1, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
//repeat remaining reads
for (i=1;i<64;i=i+1) begin
// read
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd({5'b0,ca[9:0]}+(i<<3),ba[2:0],2, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
end
// nop - all 3 below are the same? - just repeat?
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 0, 0, sel, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// tRTP = 4*tCK is already satisfied, no skip here
// precharge, end of a page (B_RST)
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( ra[14:0], ba[2:0], 5, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 2, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// Turn off DCI, set DONE
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
end
endtask
task set_write_block;
input[2:0]ba;
input[14:0]ra;
input[9:0]ca;
input sel;
reg[29:0] cmd_addr;
reg[31:0] data;
integer i;
begin
cmd_addr <= MCONTR_CMD_WR_ADDR + WRITE_BLOCK_OFFSET;
// activate
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( ra[14:0], ba[2:0], 4, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// see if pause is needed . See when buffer read should be started - maybe before WR command
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0); // tRCD - 2 read bufs
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// first write, 3 rd_buf
// write
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}, ba[2:0], 3, 1, 0, sel, 0, 0, 0, 0, 0, 1, 0, 0); // B_RD moved 1 cycle earlier
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop 4-th rd_buf
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
// data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 1, 1, 1, 0, 1, 0, 1, 0);
// data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 0, 0, 0, 1, 0);
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 0, 0, 0, 0, 0, 1, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
//repeat remaining writes
for (i = 1; i < 62; i = i + 1) begin
// write
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(i<<3),ba[2:0],3, 1, 0, sel, 1, 1, 1, 0, 0, 1, 1, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
end
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(62<<3),ba[2:0], 3, 1, 0, sel, 1, 1, 1, 0, 0, 1, 0, 0); // write w/o nop
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, sel, 1, 1, 1, 0, 0, 0, 0); // nop with buffer read off
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// One last write pair w/o buffer
// add bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( {5'b0,ca[9:0]}+(63<<3),ba[2:0], 3, 1, 0, sel, 1, 1, 1, 0, 0, 0, 1, 0); // write with nop
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 1, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 1, 0, 0, 0, 1); // removed B_RD 1 cycle earlier
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, ba[2:0], 1, 0, 0, 1, 1, 1, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// ODT off, it has latency
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 2, 0, ba[2:0], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// precharge, ODT off
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( ra[14:0], ba[2:0], 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 2, 0, ba[2:0], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// Finalize, set DONE
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
end
endtask
// Set MR3, read nrep*8 words, save to buffer (port0). No ACTIVATE/PRECHARGE are needed/allowed
task set_read_pattern;
input integer nrep;
// input [ 2:0] ba;
// input [14:0] ra;
// input [ 9:0] ca;
reg[29:0] cmd_addr;
reg[31:0] data;
reg[17:0] mr3_norm;
reg[17:0] mr3_patt;
integer i;
begin
cmd_addr <= MCONTR_CMD_WR_ADDR + READ_PATTERN_OFFSET;
mr3_norm <= ddr3_mr3(
1'h0, // mpr; // MPR mode: 0 - normal, 1 - dataflow from MPR
2'h0); // [1:0] mpr_rf; // MPR read function: 2'b00: predefined pattern 0101...
mr3_patt <= ddr3_mr3(
1'h1, // mpr; // MPR mode: 0 - normal, 1 - dataflow from MPR
2'h0); // [1:0] mpr_rf; // MPR read function: 2'b00: predefined pattern 0101...
@(posedge CLK);
// Set pattern mode
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd(mr3_patt[14:0], mr3_patt[17:15], 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); // tMOD
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// first read
// read
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( 0, 0, 2, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop (combine with previous?)
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
//repeat remaining reads
for (i = 1; i < nrep; i = i + 1) begin
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( 0, 0, 2, 0, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
end
// nop - all 3 below are the same? - just repeat?
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0); // was BUF WR
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// nop, no write buffer - next page
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 1, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// Turn off read pattern mode
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd(mr3_norm[14:0], mr3_norm[17:15], 7, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// tMOD (keep DCI enabled)
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 5, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// Turn off DCI
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// Finalize (set DONE)
data <= func_encode_skip( 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
end
endtask
task set_write_lev;
input[CMD_PAUSE_BITS-1:0]nrep;
reg[17:0] mr1_norm;
reg[17:0] mr1_wlev;
reg[29:0] cmd_addr;
reg[31:0] data;
reg[CMD_PAUSE_BITS-1:0] dqs_low_rpt;
reg[CMD_PAUSE_BITS-1:0] nrep_minus_1;
begin
dqs_low_rpt <= 8;
nrep_minus_1 <= nrep - 1;
mr1_norm <= ddr3_mr1(
1'h0, // qoff; // output enable: 0 - DQ, DQS operate in normal mode, 1 - DQ, DQS are disabled
1'h0, // tdqs; // termination data strobe (for x8 devices) 0 - disabled, 1 - enabled
3'h2, // [2:0] rtt; // on-die termination resistance: // 3'b010 - RZQ/2 (120 Ohm)
1'h0, // wlev; // write leveling
2'h0, // ods; // output drive strength: // 2'b00 - RZQ/6 - 40 Ohm
2'h0, // [1:0] al; // additive latency: 2'b00 - disabled (AL=0)
1'b0); // dll; // 0 - DLL enabled (normal), 1 - DLL disabled
mr1_wlev <= ddr3_mr1(
1'h0, // qoff; // output enable: 0 - DQ, DQS operate in normal mode, 1 - DQ, DQS are disabled
1'h0, // tdqs; // termination data strobe (for x8 devices) 0 - disabled, 1 - enabled
3'h2, // [2:0] rtt; // on-die termination resistance: // 3'b010 - RZQ/2 (120 Ohm)
1'h1, // wlev; // write leveling
2'h0, // ods; // output drive strength: // 2'b00 - RZQ/6 - 40 Ohm
2'h0, // [1:0] al; // additive latency: 2'b00 - disabled (AL=0)
1'b0); // dll; // 0 - DLL enabled (normal), 1 - DLL disabled
cmd_addr <= MCONTR_CMD_WR_ADDR + WRITELEV_OFFSET;
// Enter write leveling mode
@(posedge CLK)
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd(mr1_wlev[14:0], mr1_wlev[17:15], 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); // tWLDQSEN=25tCK
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// enable DQS output, keep it low (15 more tCK for the total of 40 tCK
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip(dqs_low_rpt, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// Toggle DQS as needed for write leveling, write to buffer
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip(nrep_minus_1,0, 0, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// continue toggling (5 times), but disable writing to buffer (used same wbuf latency as for read)
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 4, 0, 0, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// Keep DCI (but not ODT) active ODT should be off befor MRS
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 2, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// exit write leveling mode, ODT off, DCI off
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd(mr1_norm[14:0], mr1_norm[17:15], 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); // tMOD
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// Finalize. See if DONE can be combined with B_RST, if not - insert earlier
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1); // can DONE be combined with B_RST?
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
end
endtask
task set_refresh;
input[9:0]t_rfc; // =50 for tCK=2.5ns
input[7:0]t_refi; // 48/97 for normal, 8 - for simulation
reg[29:0] cmd_addr;
reg[31:0] data;
begin
cmd_addr <= MCONTR_CMD_WR_ADDR + REFRESH_OFFSET;
@(posedge CLK)
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd( 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// =50 tREFI=260 ns before next ACTIVATE or REFRESH, @2.5ns clock, @5ns cycle
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( t_rfc, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// Ready for normal operation
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// write_contol_register(DLY_SET,0);
write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_REFRESH_ADDRESS, REFRESH_OFFSET);
write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_REFRESH_PERIOD, {24'h0,t_refi});
// enable refresh - should it be done here?
// write_contol_register(MCONTR_PHY_0BIT_ADDR + MCONTR_TOP_0BIT_REFRESH_EN + 1, 0);
end
endtask
task set_mrs; // will also calibrate ZQ
input reset_dll;
reg[17:0] mr0;
reg[17:0] mr1;
reg[17:0] mr2;
reg[17:0] mr3;
reg[29:0] cmd_addr;
reg[31:0] data;
begin
mr0 <= ddr3_mr0(
1'h0, // pd; // precharge power down 0 - dll off (slow exit), 1 - dll on (fast exit)
3'h2, // [2:0] wr; // write recovery (encode ceil(tWR/tCK)) // 3'b010: 6
reset_dll, // dll_rst; // 1 - dll reset (self clearing bit)
4'h4, // [3:0] cl; // CAS latency: // 0100: 6 (time 15ns)
1'h0, // bt; // read burst type: 0 sequential (nibble), 1 - interleave
2'h0); // [1:0] bl; // burst length: // 2'b00 - fixed BL8
mr1 <= ddr3_mr1(
1'h0, // qoff; // output enable: 0 - DQ, DQS operate in normal mode, 1 - DQ, DQS are disabled
1'h0, // tdqs; // termination data strobe (for x8 devices) 0 - disabled, 1 - enabled
3'h2, // [2:0] rtt; // on-die termination resistance: // 3'b010 - RZQ/2 (120 Ohm)
1'h0, // wlev; // write leveling
2'h0, // ods; // output drive strength: // 2'b00 - RZQ/6 - 40 Ohm
2'h0, // [1:0] al; // additive latency: 2'b00 - disabled (AL=0)
1'b0); // dll; // 0 - DLL enabled (normal), 1 - DLL disabled
mr2 <= ddr3_mr2(
2'h0, // [1:0] rtt_wr; // Dynamic ODT : // 2'b00 - disabled, 2'b01 - RZQ/4 = 60 Ohm, 2'b10 - RZQ/2 = 120 Ohm
1'h0, // srt; // Self-refresh temperature 0 - normal (0-85C), 1 - extended (<=95C)
1'h0, // asr; // Auto self-refresh 0 - disabled (manual), 1 - enabled (auto)
3'h0); // [2:0] cwl; // CAS write latency:3'b000 5CK (tCK >= 2.5ns), 3'b001 6CK (1.875ns <= tCK < 2.5ns)
mr3 <= ddr3_mr3(
1'h0, // mpr; // MPR mode: 0 - normal, 1 - dataflow from MPR
2'h0); // [1:0] mpr_rf; // MPR read function: 2'b00: predefined pattern 0101...
cmd_addr <= MCONTR_CMD_WR_ADDR + INITIALIZE_OFFSET;
@(posedge CLK)
$display("mr0=0x%x", mr0);
$display("mr1=0x%x", mr1);
$display("mr2=0x%x", mr2);
$display("mr3=0x%x", mr3);
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd(mr2[14:0], mr2[17:15], 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd(mr3[14:0], mr3[17:15], 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd(mr1[14:0], mr1[17:15], 7, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0); // SEL==1 - just testing?
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd(mr0[14:0], mr0[17:15], 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// encode ZQCL:
// addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data <= func_encode_cmd(15'h400, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// 512 clock cycles after ZQCL
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 256, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
// sequence done bit, skip length is ignored
// skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data <= func_encode_skip( 10, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
@(posedge CLK) axi_write_single_w(cmd_addr, data); cmd_addr <= cmd_addr + 1;
end
endtask
function [ADDRESS_NUMBER+2:0] ddr3_mr0;
input pd; // precharge power down 0 - dll off (slow exit), 1 - dll on (fast exit)
input [2:0] wr; // write recovery:
// 3'b000: 16
// 3'b001: 5
// 3'b010: 6
// 3'b011: 7
// 3'b100: 8
// 3'b101: 10
// 3'b110: 12
// 3'b111: 14
input dll_rst; // 1 - dll reset (self clearing bit)
input [3:0] cl; // CAS latency (>=15ns):
// 0000: reserved
// 0010: 5
// 0100: 6
// 0110: 7
// 1000: 8
// 1010: 9
// 1100: 10
// 1110: 11
// 0001: 12
// 0011: 13
// 0101: 14
input bt; // read burst type: 0 sequential (nibble), 1 - interleaved
input [1:0] bl; // burst length:
// 2'b00 - fixed BL8
// 2'b01 - 4 or 8 on-the-fly by A12
// 2'b10 - fixed BL4 (chop)
// 2'b11 - reserved
begin
ddr3_mr0 = {
3'b0,
{ADDRESS_NUMBER-13{1'b0}},
pd, // MR0.12
wr, // MR0.11_9
dll_rst, // MR0.8
1'b0, // MR0.7
cl[3:1], // MR0.6_4
bt, // MR0.3
cl[0], // MR0.2
bl[1:0]}; // MR0.1_0
end
endfunction
function [ADDRESS_NUMBER+2:0] ddr3_mr1;
input qoff; // output enable: 0 - DQ, DQS operate in normal mode, 1 - DQ, DQS are disabled
input tdqs; // termination data strobe (for x8 devices) 0 - disabled, 1 - enabled
input [2:0] rtt; // on-die termination resistance:
// 3'b000 - disabled
// 3'b001 - RZQ/4 (60 Ohm)
// 3'b010 - RZQ/2 (120 Ohm)
// 3'b011 - RZQ/6 (40 Ohm)
// 3'b100 - RZQ/12(20 Ohm)
// 3'b101 - RZQ/8 (30 Ohm)
// 3'b11x - reserved
input wlev; // write leveling
input [1:0] ods; // output drive strength:
// 2'b00 - RZQ/6 - 40 Ohm
// 2'b01 - RZQ/7 - 34 Ohm
// 2'b1x - reserved
input [1:0] al; // additive latency:
// 2'b00 - disabled (AL=0)
// 2'b01 - AL=CL-1;
// 2'b10 - AL=CL-2
// 2'b11 - reserved
input dll; // 0 - DLL enabled (normal), 1 - DLL disabled
begin
ddr3_mr1 = {
3'h1,
{ADDRESS_NUMBER-13{1'b0}},
qoff, // MR1.12
tdqs, // MR1.11
1'b0, // MR1.10
rtt[2], // MR1.9
1'b0, // MR1.8
wlev, // MR1.7
rtt[1], // MR1.6
ods[1], // MR1.5
al[1:0], // MR1.4_3
rtt[0], // MR1.2
ods[0], // MR1.1
dll}; // MR1.0
end
endfunction
function [ADDRESS_NUMBER+2:0] ddr3_mr2;
input [1:0] rtt_wr; // Dynamic ODT :
// 2'b00 - disabled
// 2'b01 - RZQ/4 = 60 Ohm
// 2'b10 - RZQ/2 = 120 Ohm
// 2'b11 - reserved
input srt; // Self-refresh temperature 0 - normal (0-85C), 1 - extended (<=95C)
input asr; // Auto self-refresh 0 - disabled (manual), 1 - enabled (auto)
input [2:0] cwl; // CAS write latency:
// 3'b000 5CK ( tCK >= 2.5ns)
// 3'b001 6CK (1.875ns <= tCK < 2.5ns)
// 3'b010 7CK (1.5ns <= tCK < 1.875ns)
// 3'b011 8CK (1.25ns <= tCK < 1.5ns)
// 3'b100 9CK (1.071ns <= tCK < 1.25ns)
// 3'b101 10CK (0.938ns <= tCK < 1.071ns)
// 3'b11x reserved
begin
ddr3_mr2 = {
3'h2,
{ADDRESS_NUMBER-11{1'b0}},
rtt_wr[1:0], // MR2.10_9
1'b0, // MR2.8
srt, // MR2.7
asr, // MR2.6
cwl[2:0], // MR2.5_3
3'b0}; // MR2.2_0
end
endfunction
function [ADDRESS_NUMBER+2:0] ddr3_mr3;
input mpr; // MPR mode: 0 - normal, 1 - dataflow from MPR
input [1:0] mpr_rf; // MPR read function:
// 2'b00: predefined pattern 0101...
// 2'b1x, 2'bx1 - reserved
begin
ddr3_mr3 = {
3'h3,
{ADDRESS_NUMBER-3{1'b0}},
mpr, // MR3.2
mpr_rf[1:0]}; // MR3.1_0
end
endfunction
includes/x393_tasks_ps_pio.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_tasks_ps_pio.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Simulation tasks for mcntrl_ps_pio module (launching software
* - programmed memory transaction sequences)
*
* Copyright (c) 2015 Elphel, Inc.
* x393_tasks_ps_pio.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_tasks_ps_pio.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
task schedule_ps_pio; // schedule software-control memory operation (may need to check FIFO status first)
input [9:0] seq_addr; // sequence start address
input [1:0] page; // buffer page number
input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
input chn; // channel buffer to use: 0 - memory read, 1 - memory write
input wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
begin
// wait_ps_pio_ready(DEFAULT_STATUS_MODE); // wait FIFO not half full
write_contol_register(MCNTRL_PS_ADDR + MCNTRL_PS_CMD, {17'b0,wait_complete,chn,urgent,page,seq_addr});
end
endtask
task wait_ps_pio_ready; // wait PS PIO module can accept comamnds (fifo half empty)
input [1:0] mode;
input sync_seq; // synchronize sequences
begin
wait_status_condition (
MCNTRL_PS_STATUS_REG_ADDR,
MCNTRL_PS_ADDR+MCNTRL_PS_STATUS_CNTRL,
mode,
0,
2 << STATUS_2LSB_SHFT,
0,
sync_seq);
end
endtask
task wait_ps_pio_done; // wait PS PIO module has no pending/running memory transaction
input [1:0] mode;
input sync_seq; // synchronize sequences
begin
wait_status_condition (
MCNTRL_PS_STATUS_REG_ADDR,
MCNTRL_PS_ADDR+MCNTRL_PS_STATUS_CNTRL,
mode,
0,
3 << STATUS_2LSB_SHFT,
0,
sync_seq);
end
endtask
includes/x393_tasks_status.vh 0 → 100644
View file @ e4816b14
/*******************************************************************************
* File: x393_status.vh
* Date:2015-02-07
* Author: Andrey Filippov
* Description: Simulation tasks for the x393 related to status
*
* Copyright (c) 2015 Elphel, Inc.
* x393_status.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* x393_status.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
// CVC bug that is supposed to be already fixed
`ifdef CVC
task wait_status_condition;
input [STATUS_DEPTH-1:0] status_address;
input [29:0] status_control_address;
input [1:0] status_mode;
input [25:0] pattern; // bits as in read registers
input [25:0] mask; // which bits to compare
input invert_match; // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
input wait_seq;
reg match;
reg [5:0] seq_num;
reg [31:0] pattern1;
reg [31:0] mask1;
begin
WAITING_STATUS = 1;
pattern1 = {6'h0,pattern};
mask1 = {6'h0,mask};
for (match=0; !match; match = invert_match ^ (((registered_rdata ^ pattern1) & mask1)==0)) begin
read_status(status_address);
if (wait_seq) begin
seq_num = (registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20)&'h30;
write_contol_register(status_control_address, {24'b0,status_mode,seq_num});
read_status(status_address);
while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ seq_num) & 6'h30)!=0) begin // match just 2 MSBs
read_status(status_address);
end
end
pattern1 = {6'h0,pattern};
mask1 = {6'h0,mask};
end
WAITING_STATUS = 0;
end
endtask
`else
task wait_status_condition;
input [STATUS_DEPTH-1:0] status_address;
input [29:0] status_control_address;
input [1:0] status_mode;
input [25:0] pattern; // bits as in read registers
input [25:0] mask; // which bits to compare
input invert_match; // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
input wait_seq;
reg match;
reg [5:0] seq_num;
begin
WAITING_STATUS = 1;
for (match=0; !match; match = invert_match ^ (((registered_rdata ^ {6'h0,pattern}) & {6'h0,mask})==0)) begin
read_status(status_address);
if (wait_seq) begin
seq_num = (registered_rdata[STATUS_SEQ_SHFT+:6] ^ 6'h20)&'h30;
write_contol_register(status_control_address, {24'b0,status_mode,seq_num});
read_status(status_address);
while (((registered_rdata[STATUS_SEQ_SHFT+:6] ^ seq_num) & 6'h30)!=0) begin // match just 2 MSBs
read_status(status_address);
end
end
end
WAITING_STATUS = 0;
end
endtask
`endif
/*
task wait_status_condition_auto; // assumes status is already updating
input [STATUS_DEPTH-1:0] status_address;
input [29:0] status_control_address;
input [1:0] status_mode;
input [25:0] pattern; // bits as in read registers
input [25:0] mask; // which bits to compare
input invert_match; // 0 - wait until match to pattern (all bits), 1 - wait until no match (any of bits differ)
reg match;
begin
WAITING_STATUS = 1;
for (match=0; !match; match = invert_match ^ (((registered_rdata ^ {6'h0,pattern}) & {6'h0,mask})==0)) begin
read_status(status_address);
end
WAITING_STATUS = 0;
end
endtask
*/
task wait_phase_shifter_ready;
begin
WAITING_STATUS = 1;
read_status(MCONTR_PHY_STATUS_REG_ADDR);
while (((registered_rdata & STATUS_PSHIFTER_RDY_MASK) == 0) || (((registered_rdata ^ {24'h0,target_phase}) & 'hff) != 0)) begin
read_status(MCONTR_PHY_STATUS_REG_ADDR); // exits after negedge CLK
end
WAITING_STATUS = 0;
end
endtask
task read_all_status;
begin
$display (" read_all_status @%t",$time);
read_status (MCONTR_PHY_STATUS_REG_ADDR);
read_status (MCONTR_TOP_STATUS_REG_ADDR);
read_status (MCNTRL_PS_STATUS_REG_ADDR);
read_status (MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR);
read_status (MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR);
read_status (MCNTRL_TILED_STATUS_REG_CHN2_ADDR);
read_status (MCNTRL_TILED_STATUS_REG_CHN4_ADDR);
// read_status (MCNTRL_TEST01_STATUS_REG_CHN1_ADDR);
read_status (MCNTRL_TEST01_STATUS_REG_CHN2_ADDR);
read_status (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR);
read_status (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR);
read_status (MEMBRIDGE_STATUS_REG);
end
endtask
task read_status;
input [STATUS_DEPTH-1:0] address;
begin
read_and_wait_w(STATUS_ADDR + address ); // Will set: registered_rdata <= rdata;
end
endtask
task program_status_all;
input [1:0] mode;
input [5:0] seq_num;
begin
program_status (MCONTR_PHY_16BIT_ADDR, MCONTR_PHY_STATUS_CNTRL, mode,seq_num); //MCONTR_PHY_STATUS_REG_ADDR= 'h0,
program_status (MCONTR_TOP_16BIT_ADDR, MCONTR_TOP_16BIT_STATUS_CNTRL, mode,seq_num); //MCONTR_TOP_STATUS_REG_ADDR= 'h1,
program_status (MCNTRL_PS_ADDR, MCNTRL_PS_STATUS_CNTRL, mode,seq_num); //MCNTRL_PS_STATUS_REG_ADDR= 'h2,
program_status (MCNTRL_SCANLINE_CHN1_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN2_ADDR='h4,
program_status (MCNTRL_SCANLINE_CHN3_ADDR, MCNTRL_SCANLINE_STATUS_CNTRL, mode,seq_num); //MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR='h5,
program_status (MCNTRL_TILED_CHN2_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
program_status (MCNTRL_TILED_CHN4_ADDR, MCNTRL_TILED_STATUS_CNTRL, mode,seq_num); //MCNTRL_TILED_STATUS_REG_CHN4_ADDR= 'h6,
// program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN1_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR= 'h3c,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3d,
program_status (MCNTRL_TEST01_ADDR, MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
program_status (MEMBRIDGE_ADDR , MEMBRIDGE_STATUS_CNTRL, mode,seq_num); //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3e,
end
endtask
task program_status;
input [29:0] base_addr;
input [7:0] reg_addr;
input [1:0] mode;
// mode bits:
// 0 disable status generation,
// 1 single status request,
// 2 - auto status, keep specified seq number,
// 3 - auto, inc sequence number
input [5:0] seq_number;
begin
// axi_write_single_w(CONTROL_ADDR+base_addr+reg_addr, {24'b0,mode,seq_number});
write_contol_register(base_addr + reg_addr, {24'b0,mode,seq_number});
end
endtask
system_defines.vh 0 → 100644
View file @ e4816b14
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
`define PRELOAD_BRAMS
// Enviroment-dependent options
`ifdef IVERILOG
`define SIMULATION
`define OPEN_SOURCE_ONLY
`else
`ifdef CVC
`define SIMULATION
`define OPEN_SOURCE_ONLY
`endif // CVC
`endif // IVERILOG
// will not use simultaneous reset in shift registers, just and input data with ~rst
`define SHREG_SEQUENTIAL_RESET 1
// synthesis does to recognize global clock as G input of the primitive latch
`undef INFER_LATCHES
// define when using CDC - it does not support them
`undef IGNORE_ATTR
//`define MEMBRIDGE_DEBUG_READ 1
`define use200Mhz 1
`define USE_CMD_ENCOD_TILED_32_RD 1
// It can be used to check different `ifdef branches
//`define XIL_TIMING //Simprim
`define den4096Mb 1
// `define IVERILOG
// defines for memory channels
// chn 0 is read from memory and write to memory
`define def_enable_mem_chn0
`define def_read_mem_chn0
`define def_write_mem_chn0
`undef def_scanline_chn0
`undef def_tiled_chn0
// chn 1 is scanline r+w
`define def_enable_mem_chn1
`define def_read_mem_chn1
`define def_write_mem_chn1
`define def_scanline_chn1
`undef def_tiled_chn1
// chn 2 is tiled r+w
`define def_enable_mem_chn2
`define def_read_mem_chn2
`define def_write_mem_chn2
`undef def_scanline_chn2
`define def_tiled_chn2
// chn 3 is scanline r+w (reuse later)
`define def_enable_mem_chn3
`define def_read_mem_chn3
`define def_write_mem_chn3
`define def_scanline_chn3
`undef def_tiled_chn3
// chn 4 is tiled r+w (reuse later)
`define def_enable_mem_chn4
`define def_read_mem_chn4
`define def_write_mem_chn4
`undef def_scanline_chn4
`define def_tiled_chn4
// chn 5 is disabled
`undef def_enable_mem_chn5
// chn 6 is disabled
`undef def_enable_mem_chn6
// chn 7 is disabled
`undef def_enable_mem_chn7
// chn 8 is scanline w (sensor channel 0)
`define def_enable_mem_chn8
`undef def_read_mem_chn8
`define def_write_mem_chn8
`define def_scanline_chn8
`undef def_tiled_chn8
// chn 9 is scanline w (sensor channel 1)
`define def_enable_mem_chn9
`undef def_read_mem_chn9
`define def_write_mem_chn9
`define def_scanline_chn9
`undef def_tiled_chn9
// chn 10 is scanline w (sensor channel 2)
`define def_enable_mem_chn10
`undef def_read_mem_chn10
`define def_write_mem_chn10
`define def_scanline_chn10
`undef def_tiled_chn10
// chn 11 is scanline w (sensor channel 3)
`define def_enable_mem_chn11
`undef def_read_mem_chn11
`define def_write_mem_chn11
`define def_scanline_chn11
`undef def_tiled_chn11
// chn 12 is tiled read (compressor channel 0)
`define def_enable_mem_chn12
`define def_read_mem_chn12
`undef def_write_mem_chn12
`undef def_scanline_chn12
`define def_tiled_chn12
// chn 12 is tiled read (compressor channel 1)
`define def_enable_mem_chn13
`define def_read_mem_chn13
`undef def_write_mem_chn13
`undef def_scanline_chn13
`define def_tiled_chn13
// chn 12 is tiled read (compressor channel 2)
`define def_enable_mem_chn14
`define def_read_mem_chn14
`undef def_write_mem_chn14
`undef def_scanline_chn14
`define def_tiled_chn14
// chn 12 is tiled read (compressor channel 3)
`define def_enable_mem_chn15
`define def_read_mem_chn15
`undef def_write_mem_chn15
`undef def_scanline_chn15
`define def_tiled_chn15
`endif
\ No newline at end of file
wrapper/GTXE2_GPL.v
View file @ e4816b14
...@@ -88,7 +88,7 @@ module gtxe2_chnl_cpll( ...@@ -88,7 +88,7 @@ module gtxe2_chnl_cpll(
input wire [4:0] PMARSVDIN, input wire [4:0] PMARSVDIN,
input wire [4:0] PMARSVDIN2, input wire [4:0] PMARSVDIN2,
input wire [19:0] TSTIN, input wire [19:0] TSTIN,
output wire TSTOUT, output wire [9:0] TSTOUT,
// internal // internal
input wire ref_clk, input wire ref_clk,
...@@ -287,7 +287,7 @@ module gtxe2_chnl_clocking( ...@@ -287,7 +287,7 @@ module gtxe2_chnl_clocking(
output wire rx_sipo_clk, output wire rx_sipo_clk,
// additional ports to cpll // additional ports to cpll
output TSTOUT, output [9:0] TSTOUT,
input [15:0] GTRSVD, input [15:0] GTRSVD,
input [15:0] PCSRSVDIN, input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2, input [4:0] PCSRSVDIN2,
...@@ -2208,7 +2208,7 @@ module gtxe2_chnl( ...@@ -2208,7 +2208,7 @@ module gtxe2_chnl(
output wire rx_serial_clk, output wire rx_serial_clk,
// additional ports to pll // additional ports to pll
output TSTOUT, output [9:0] TSTOUT,
input [15:0] GTRSVD, input [15:0] GTRSVD,
input [15:0] PCSRSVDIN, input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2, input [4:0] PCSRSVDIN2,
...@@ -2428,7 +2428,7 @@ module GTXE2_GPL( ...@@ -2428,7 +2428,7 @@ module GTXE2_GPL(
output CPLLFBCLKLOST, output CPLLFBCLKLOST,
output CPLLLOCK, output CPLLLOCK,
output CPLLREFCLKLOST, output CPLLREFCLKLOST,
output TSTOUT, output [9:0] TSTOUT,
input [15:0] GTRSVD, input [15:0] GTRSVD,
input [15:0] PCSRSVDIN, input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2, input [4:0] PCSRSVDIN2,
...@@ -2445,7 +2445,7 @@ module GTXE2_GPL( ...@@ -2445,7 +2445,7 @@ module GTXE2_GPL(
input TXPMARESET, input TXPMARESET,
output TXRESETDONE, output TXRESETDONE,
input TXUSERRDY, input TXUSERRDY,
output PCSRSVDOUT, output [15:0] PCSRSVDOUT,
// RX Reset ports, UG476 p.73 // RX Reset ports, UG476 p.73
input GTRXRESET, input GTRXRESET,
input RXPMARESET, input RXPMARESET,
...@@ -2651,8 +2651,8 @@ module GTXE2_GPL( ...@@ -2651,8 +2651,8 @@ module GTXE2_GPL(
input RXDLYOVRDEN, input RXDLYOVRDEN,
input RXDDIEN, input RXDDIEN,
output RXPHALIGNDONE, output RXPHALIGNDONE,
output RXPHMONITOR, output [4:0] RXPHMONITOR,
output RXPHSLIPMONITOR, output [4:0] RXPHSLIPMONITOR,
output RXDLYSRESETDONE, output RXDLYSRESETDONE,
// RX Buffer Ports, ug476 p.259 // RX Buffer Ports, ug476 p.259
output [2:0] RXBUFSTATUS, output [2:0] RXBUFSTATUS,
......
wrapper/gtxe2_channel_wrapper.v
View file @ e4816b14
...@@ -18,7 +18,6 @@ ...@@ -18,7 +18,6 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
`define OPEN_SOURCE_ONLY
module gtxe2_channel_wrapper( module gtxe2_channel_wrapper(
// clocking ports, UG476 p.37 // clocking ports, UG476 p.37
input [2:0] CPLLREFCLKSEL, input [2:0] CPLLREFCLKSEL,
...@@ -40,7 +39,7 @@ module gtxe2_channel_wrapper( ...@@ -40,7 +39,7 @@ module gtxe2_channel_wrapper(
output CPLLFBCLKLOST, output CPLLFBCLKLOST,
output CPLLLOCK, output CPLLLOCK,
output CPLLREFCLKLOST, output CPLLREFCLKLOST,
output TSTOUT, output [9:0] TSTOUT,
input [15:0] GTRSVD, input [15:0] GTRSVD,
input [15:0] PCSRSVDIN, input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2, input [4:0] PCSRSVDIN2,
...@@ -57,7 +56,7 @@ module gtxe2_channel_wrapper( ...@@ -57,7 +56,7 @@ module gtxe2_channel_wrapper(
input TXPMARESET, input TXPMARESET,
output TXRESETDONE, output TXRESETDONE,
input TXUSERRDY, input TXUSERRDY,
output PCSRSVDOUT, output [15:0] PCSRSVDOUT,
// RX Reset ports, UG476 p.73 // RX Reset ports, UG476 p.73
input GTRXRESET, input GTRXRESET,
input RXPMARESET, input RXPMARESET,
...@@ -263,8 +262,8 @@ module gtxe2_channel_wrapper( ...@@ -263,8 +262,8 @@ module gtxe2_channel_wrapper(
input RXDLYOVRDEN, input RXDLYOVRDEN,
input RXDDIEN, input RXDDIEN,
output RXPHALIGNDONE, output RXPHALIGNDONE,
output RXPHMONITOR, output [4:0] RXPHMONITOR,
output RXPHSLIPMONITOR, output [4:0] RXPHSLIPMONITOR,
output RXDLYSRESETDONE, output RXDLYSRESETDONE,
// RX Buffer Ports, ug476 p.259 // RX Buffer Ports, ug476 p.259
output [2:0] RXBUFSTATUS, output [2:0] RXBUFSTATUS,
...@@ -358,10 +357,10 @@ parameter TXPHDLY_CFG = 24'h0; ...@@ -358,10 +357,10 @@ parameter TXPHDLY_CFG = 24'h0;
parameter TXDLY_CFG = 16'h0; parameter TXDLY_CFG = 16'h0;
parameter TXDLY_LCFG = 9'h0; parameter TXDLY_LCFG = 9'h0;
parameter TXDLY_TAP_CFG = 16'h0; parameter TXDLY_TAP_CFG = 16'h0;
parameter TXSYNC_MULTILANE = 1'b0; //parameter TXSYNC_MULTILANE = 1'b0;
parameter TXSYNC_SKIP_DA = 1'b0; //parameter TXSYNC_SKIP_DA = 1'b0;
parameter TXSYNC_OVRD = 1'b1; //parameter TXSYNC_OVRD = 1'b1;
parameter LOOPBACK_CFG = 1'b0; //parameter LOOPBACK_CFG = 1'b0;
// TX Pattern Generator, ug476 p.147 // TX Pattern Generator, ug476 p.147
parameter RXPRBS_ERR_LOOPBACK = 1'b0; parameter RXPRBS_ERR_LOOPBACK = 1'b0;
// TX Fabric Clock Output Control Attributes, ug476 p. 153 // TX Fabric Clock Output Control Attributes, ug476 p. 153
...@@ -459,7 +458,7 @@ parameter RX_DATA_WIDTH = 20; ...@@ -459,7 +458,7 @@ parameter RX_DATA_WIDTH = 20;
parameter RX_INT_DATAWIDTH = 0; parameter RX_INT_DATAWIDTH = 0;
parameter ES_PMA_CFG = 10'h0; parameter ES_PMA_CFG = 10'h0;
// Pattern Checker Attributes, ug476 p.226 // Pattern Checker Attributes, ug476 p.226
parameter RX_PRBS_ERR_CNT = 16'h15c; //parameter RX_PRBS_ERR_CNT = 16'h15c;
// RX Byte and Word Alignment Attributes, ug476 p.235 // RX Byte and Word Alignment Attributes, ug476 p.235
parameter ALIGN_COMMA_WORD = 1; parameter ALIGN_COMMA_WORD = 1;
parameter ALIGN_COMMA_ENABLE = 10'b1111111111; parameter ALIGN_COMMA_ENABLE = 10'b1111111111;
...@@ -472,7 +471,7 @@ parameter SHOW_REALIGN_COMMA = "TRUE"; ...@@ -472,7 +471,7 @@ parameter SHOW_REALIGN_COMMA = "TRUE";
parameter RXSLIDE_MODE = "OFF"; parameter RXSLIDE_MODE = "OFF";
parameter RXSLIDE_AUTO_WAIT = 7; parameter RXSLIDE_AUTO_WAIT = 7;
parameter RX_SIG_VALID_DLY = 10; parameter RX_SIG_VALID_DLY = 10;
parameter COMMA_ALIGN_LATENCY = 9'h14e; //parameter COMMA_ALIGN_LATENCY = 9'h14e;
// RX 8B/10B Decoder Attributes, ug476 p.242 // RX 8B/10B Decoder Attributes, ug476 p.242
parameter RX_DISPERR_SEQ_MATCH = "TRUE"; parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE"; parameter DEC_MCOMMA_DETECT = "TRUE";
...@@ -608,10 +607,10 @@ GTXE2_CHANNEL #( ...@@ -608,10 +607,10 @@ GTXE2_CHANNEL #(
.TXDLY_CFG (TXDLY_CFG), .TXDLY_CFG (TXDLY_CFG),
.TXDLY_LCFG (TXDLY_LCFG), .TXDLY_LCFG (TXDLY_LCFG),
.TXDLY_TAP_CFG (TXDLY_TAP_CFG), .TXDLY_TAP_CFG (TXDLY_TAP_CFG),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), /* .TXSYNC_MULTILANE (TXSYNC_MULTILANE),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA), .TXSYNC_SKIP_DA (TXSYNC_SKIP_DA),
.TXSYNC_OVRD (TXSYNC_OVRD), .TXSYNC_OVRD (TXSYNC_OVRD),
.LOOPBACK_CFG (LOOPBACK_CFG), .LOOPBACK_CFG (LOOPBACK_CFG),*/
// TX Pattern Generator, ug476 p.147 // TX Pattern Generator, ug476 p.147
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK), .RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK),
// TX Fabric Clock Output Control Attributes, ug476 p. 153 // TX Fabric Clock Output Control Attributes, ug476 p. 153
...@@ -714,7 +713,7 @@ GTXE2_CHANNEL #( ...@@ -714,7 +713,7 @@ GTXE2_CHANNEL #(
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH), .RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.ES_PMA_CFG (ES_PMA_CFG), .ES_PMA_CFG (ES_PMA_CFG),
// Pattern Checker Attributes, ug476 p.226 // Pattern Checker Attributes, ug476 p.226
.RX_PRBS_ERR_CNT (RX_PRBS_ERR_CNT), //.RX_PRBS_ERR_CNT (RX_PRBS_ERR_CNT),
// RX Byte and Word Alignment Attributes, ug476 p.235 // RX Byte and Word Alignment Attributes, ug476 p.235
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD), .ALIGN_COMMA_WORD (ALIGN_COMMA_WORD),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE), .ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
...@@ -727,7 +726,7 @@ GTXE2_CHANNEL #( ...@@ -727,7 +726,7 @@ GTXE2_CHANNEL #(
.RXSLIDE_MODE (RXSLIDE_MODE), .RXSLIDE_MODE (RXSLIDE_MODE),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT), .RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY), .RX_SIG_VALID_DLY (RX_SIG_VALID_DLY),
.COMMA_ALIGN_LATENCY (COMMA_ALIGN_LATENCY), //.COMMA_ALIGN_LATENCY (COMMA_ALIGN_LATENCY),
// RX 8B/10B Decoder Attributes, ug476 p.242 // RX 8B/10B Decoder Attributes, ug476 p.242
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH), .RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT), .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
......
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