Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393_sata
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393_sata
Commits
d7d90f4c
Commit
d7d90f4c
authored
Dec 08, 2016
by
Andrey Filippov
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Updated headers for doxygen, matching those in x393 project
parent
abfd2b0d
Changes
40
Hide whitespace changes
Inline
Side-by-side
Showing
40 changed files
with
475 additions
and
262 deletions
+475
-262
ahci_ctrl_stat.v
ahci/ahci_ctrl_stat.v
+12
-7
ahci_dma.v
ahci/ahci_dma.v
+12
-7
ahci_dma_rd_fifo.v
ahci/ahci_dma_rd_fifo.v
+12
-7
ahci_dma_rd_stuff.v
ahci/ahci_dma_rd_stuff.v
+12
-7
ahci_dma_wr_fifo.v
ahci/ahci_dma_wr_fifo.v
+12
-7
ahci_fis_receive.v
ahci/ahci_fis_receive.v
+12
-7
ahci_fis_transmit.v
ahci/ahci_fis_transmit.v
+12
-7
ahci_fsm.v
ahci/ahci_fsm.v
+12
-8
ahci_sata_layers.v
ahci/ahci_sata_layers.v
+12
-7
ahci_top.v
ahci/ahci_top.v
+12
-7
axi_ahci_regs.v
ahci/axi_ahci_regs.v
+12
-7
axi_hp_abort.v
ahci/axi_hp_abort.v
+12
-7
freq_meter.v
ahci/freq_meter.v
+12
-7
sata_ahci_top.v
ahci/sata_ahci_top.v
+12
-7
oob_dev.v
device/oob_dev.v
+14
-9
sata_phy_dev.v
device/sata_phy_dev.v
+14
-9
action_decoder.v
generated/action_decoder.v
+7
-6
condition_mux.v
generated/condition_mux.v
+7
-6
crc.v
host/crc.v
+12
-7
drp_other_registers.v
host/drp_other_registers.v
+12
-7
elastic1632.v
host/elastic1632.v
+12
-7
gtx_10x8dec.v
host/gtx_10x8dec.v
+12
-7
gtx_8x10enc.v
host/gtx_8x10enc.v
+12
-7
gtx_comma_align.v
host/gtx_comma_align.v
+12
-7
gtx_elastic.v
host/gtx_elastic.v
+12
-7
gtx_wrap.v
host/gtx_wrap.v
+12
-7
link.v
host/link.v
+12
-7
oob.v
host/oob.v
+12
-7
oob_ctrl.v
host/oob_ctrl.v
+12
-7
sata_phy.v
host/sata_phy.v
+12
-7
scrambler.v
host/scrambler.v
+12
-7
ahci_defaults.vh
includes/ahci_defaults.vh
+1
-1
ahci_localparams.vh
includes/ahci_localparams.vh
+1
-1
ahci_fsm_sequence.py
py393sata/ahci_fsm_sequence.py
+28
-18
create_ahci_registers.py
py393sata/create_ahci_registers.py
+4
-1
system_defines.vh
system_defines.vh
+39
-0
GTXE2_GPL.v
wrapper/GTXE2_GPL.v
+12
-7
clock_inverter.v
wrapper/clock_inverter.v
+12
-7
gtxe2_channel_wrapper.v
wrapper/gtxe2_channel_wrapper.v
+12
-7
x393_sata.bit
x393_sata.bit
+0
-0
No files found.
ahci/ahci_ctrl_stat.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: ahci_ctrl_stat
* <b>Module:</b>ahci_ctrl_stat
* Date:2016-01-12
* @file ahci_ctrl_stat.v
* Author: Andrey Filippov
* @date 2016-01-12
* Description: Copy of significant register fields, updating them in
* @author Andrey Filippov
*
* @brief Copy of significant register fields, updating them in
* axi_ahci_regs registers (software accessible)
* axi_ahci_regs registers (software accessible)
*
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_ctrl_stat.v is free software; you can redistribute it and/or modify
* ahci_ctrl_stat.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -18,7 +23,7 @@
...
@@ -18,7 +23,7 @@
*
*
* You should have received a copy of the GNU General Public License
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
ahci_ctrl_stat
#(
module
ahci_ctrl_stat
#(
...
...
ahci/ahci_dma.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: ahci_dma
* <b>Module:</b>ahci_dma
* Date:2016-01-01
* @file ahci_dma.v
* Author: Andrey Filippov
* @date 2016-01-01
* Description: DMA R/W over 64-AXI channel for AHCI implementation
* @author Andrey Filippov
*
* @brief DMA R/W over 64-AXI channel for AHCI implementation
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_dma.v is free software; you can redistribute it and/or modify
* ahci_dma.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
ahci_dma
(
module
ahci_dma
(
...
...
ahci/ahci_dma_rd_fifo.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: ahci_dma_rd_fifo
* <b>Module:</b>ahci_dma_rd_fifo
* Date:2016-01-01
* @file ahci_dma_rd_fifo.v
* Author: Andrey Filippov
* @date 2016-01-01
* Description: cross clocks, word-realign, 64->32
* @author Andrey Filippov
*
* @brief cross clocks, word-realign, 64->32
* Convertion from x64 QWORD-aligned AXI data @hclk to
* Convertion from x64 QWORD-aligned AXI data @hclk to
* 32-bit word-aligned data at mclk
* 32-bit word-aligned data at mclk
*
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_dma_rd_fifo.v is free software; you can redistribute it and/or modify
* ahci_dma_rd_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -32,7 +37,7 @@
...
@@ -32,7 +37,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
ahci_dma_rd_fifo
#(
module
ahci_dma_rd_fifo
#(
...
...
ahci/ahci_dma_rd_stuff.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: ahci_dma_rd_stuff
* <b>Module:</b>ahci_dma_rd_stuff
* Date:2016-01-01
* @file ahci_dma_rd_stuff.v
* Author: Andrey Filippov
* @date 2016-01-01
* Description: Stuff DWORD data with missing words into continuous 32-bit data
* @author Andrey Filippov
*
* @brief Stuff DWORD data with missing words into continuous 32-bit data
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_dma_rd_stuff.v is free software; you can redistribute it and/or modify
* ahci_dma_rd_stuff.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
ahci_dma_rd_stuff
(
module
ahci_dma_rd_stuff
(
...
...
ahci/ahci_dma_wr_fifo.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: ahci_dma_wr_fifo
* <b>Module:</b>ahci_dma_wr_fifo
* Date:2016-01-02
* @file ahci_dma_wr_fifo.v
* Author: Andrey Filippov
* @date 2016-01-02
* Description: cross clocks, word-realign, 32 -> 64 with byte write mask
* @author Andrey Filippov
*
* @brief cross clocks, word-realign, 32 -> 64 with byte write mask
* Convertion from x32 DWORD data received from FIS-es @ mclk to QWORD-aligned
* Convertion from x32 DWORD data received from FIS-es @ mclk to QWORD-aligned
* AXI data @hclk
* AXI data @hclk
*
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_dma_wr_fifo.v is free software; you can redistribute it and/or modify
* ahci_dma_wr_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -32,7 +37,7 @@
...
@@ -32,7 +37,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
ahci_dma_wr_fifo
#(
module
ahci_dma_wr_fifo
#(
...
...
ahci/ahci_fis_receive.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: ahci_fis_receive
* <b>Module:</b>ahci_fis_receive
* Date:2016-01-06
* @file ahci_fis_receive.v
* Author: Andrey Filippov
* @date 2016-01-06
* Description: Receives incoming FIS-es, forwards DMA ones to DMA engine
* @author Andrey Filippov
*
* @brief Receives incoming FIS-es, forwards DMA ones to DMA engine
* Stores received FIS-es if requested
* Stores received FIS-es if requested
*
*
* 'fis_first_vld' is asserted when the FIFO output contains first DWORD
* 'fis_first_vld' is asserted when the FIFO output contains first DWORD
...
@@ -13,7 +15,10 @@
...
@@ -13,7 +15,10 @@
* one of the 3 states (fis_ok, fis_err and fis_ferr) are raised
* one of the 3 states (fis_ok, fis_err and fis_ferr) are raised
* This module also receives/updates device signature and PxTFD ERR and STS.
* This module also receives/updates device signature and PxTFD ERR and STS.
*
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_fis_receive.v is free software; you can redistribute it and/or modify
* ahci_fis_receive.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -26,7 +31,7 @@
...
@@ -26,7 +31,7 @@
*
*
* You should have received a copy of the GNU General Public License
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
ahci_fis_receive
#(
module
ahci_fis_receive
#(
...
...
ahci/ahci_fis_transmit.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: ahci_fis_transmit
* <b>Module:</b>ahci_fis_transmit
* Date:2016-01-07
* @file ahci_fis_transmit.v
* Author: Andrey Filippov
* @date 2016-01-07
* Description: Fetches commands, command tables, creates/sends FIS
* @author Andrey Filippov
*
* @brief Fetches commands, command tables, creates/sends FIS
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_fis_transmit.v is free software; you can redistribute it and/or modify
* ahci_fis_transmit.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -17,7 +22,7 @@
...
@@ -17,7 +22,7 @@
*
*
* You should have received a copy of the GNU General Public License
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
ahci_fis_transmit
#(
module
ahci_fis_transmit
#(
...
...
ahci/ahci_fsm.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: ahci_fsm
* <b>Module:</b>ahci_fsm
* Date:2016-01-10
* @file ahci_fsm.v
* Author: Andrey Filippov
* @date 2016-01-10
* Description: AHCI host+port0 state machine
* @author Andrey Filippov
*
* @brief AHCI host+port0 state machine
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_fsm.v is free software; you can redistribute it and/or modify
* ahci_fsm.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -17,7 +22,7 @@
...
@@ -17,7 +22,7 @@
*
*
* You should have received a copy of the GNU General Public License
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
ahci_fsm
module
ahci_fsm
...
@@ -318,7 +323,6 @@ module ahci_fsm
...
@@ -318,7 +323,6 @@ module ahci_fsm
wire
clear_pisn32
;
// additional clear when in P:NotRunning state
wire
clear_pisn32
;
// additional clear when in P:NotRunning state
assign
fsm_next
=
(
fsm_preload
||
(
fsm_actions
&&
!
update_busy
&&
!
fsm_act_busy
)
||
fsm_transitions
[
0
])
&&
!
async_pend_r
[
0
]
;
// quiet if received cominit is pending
assign
fsm_next
=
(
fsm_preload
||
(
fsm_actions
&&
!
update_busy
&&
!
fsm_act_busy
)
||
fsm_transitions
[
0
])
&&
!
async_pend_r
[
0
]
;
// quiet if received cominit is pending
assign
update_all
=
fsm_jump
[
0
]
;
assign
update_all
=
fsm_jump
[
0
]
;
assign
ssts_ipm_dnp
=
phy_ready_chng_r
&&
(
phy_ready_prev
==
0
)
;
// device not present or communication not established
assign
ssts_ipm_dnp
=
phy_ready_chng_r
&&
(
phy_ready_prev
==
0
)
;
// device not present or communication not established
...
...
ahci/ahci_sata_layers.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: ahci_sata_layers
* <b>Module:</b>ahci_sata_layers
* Date:2016-01-19
* @file ahci_sata_layers.v
* Author: Andrey Filippov
* @date 2016-01-19
* Description: Link and PHY SATA layers
* @author Andrey Filippov
*
* @brief Link and PHY SATA layers
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_sata_layers.v is free software; you can redistribute it and/or modify
* ahci_sata_layers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -17,7 +22,7 @@
...
@@ -17,7 +22,7 @@
*
*
* You should have received a copy of the GNU General Public License
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
ahci_sata_layers
#(
module
ahci_sata_layers
#(
...
...
ahci/ahci_top.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: ahci_top
* <b>Module:</b>ahci_top
* Date:2016-01-09
* @file ahci_top.v
* Author: Andrey Filippov
* @date 2016-01-09
* Description: Top module of the AHCI implementation
* @author Andrey Filippov
*
* @brief Top module of the AHCI implementation
*
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_top.v is free software; you can redistribute it and/or modify
* ahci_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -17,7 +22,7 @@
...
@@ -17,7 +22,7 @@
*
*
* You should have received a copy of the GNU General Public License
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
ahci_top
#(
module
ahci_top
#(
...
...
ahci/axi_ahci_regs.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: axi_ahci_regs
* <b>Module:</b>axi_ahci_regs
* Date:2015-12-29
* @file axi_ahci_regs.v
* Author: Andrey Filippov
* @date 2015-12-29
* Description: Registers for single-port AHCI over AXI implementation
* @author Andrey Filippov
*
* @brief Registers for single-port AHCI over AXI implementation
* Combination of PCI Headers, PCI power management, and HBA memory
* Combination of PCI Headers, PCI power management, and HBA memory
* 128 DWORD registers
* 128 DWORD registers
* Registers, with bits being RO, RW, RWC, RW1
* Registers, with bits being RO, RW, RWC, RW1
*
*
* Copyright (c) 2015 Elphel, Inc .
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* axi_ahci_regs.v is free software; you can redistribute it and/or modify
* axi_ahci_regs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -33,7 +38,7 @@
...
@@ -33,7 +38,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
...
...
ahci/axi_hp_abort.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: axi_hp_abort
* <b>Module:</b>axi_hp_abort
* Date:2016-02-07
* @file axi_hp_abort.v
* Author: Andrey Filippov
* @date 2016-02-07
* Description: Trying to gracefully reset AXI HP after aborted transmission
* @author Andrey Filippov
*
* @brief Trying to gracefully reset AXI HP after aborted transmission
* For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0)
* For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0)
* For write - keep track aof all what was sent so far, assuming aw is always ahead of w
* For write - keep track aof all what was sent so far, assuming aw is always ahead of w
* Reset only by global reset (system POR) - probably it is not possible to just
* Reset only by global reset (system POR) - probably it is not possible to just
* reset PL or relaod bitfile,
* reset PL or relaod bitfile,
*
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* axi_hp_abort.v is free software; you can redistribute it and/or modify
* axi_hp_abort.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -21,7 +26,7 @@
...
@@ -21,7 +26,7 @@
*
*
* You should have received a copy of the GNU General Public License
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
axi_hp_abort
(
module
axi_hp_abort
(
...
...
ahci/freq_meter.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: freq_meter
* <b>Module:</b>freq_meter
* Date:2016-02-13
* @file freq_meter.v
* Author: Andrey Filippov
* @date 2016-02-13
* Description: Measure device clock frequency to set the local clock
* @author Andrey Filippov
*
* @brief Measure device clock frequency to set the local clock
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
*
* Copyright (c) 2016 Elphel, Inc .
* freq_meter.v is free software; you can redistribute it and/or modify
* freq_meter.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -17,7 +22,7 @@
...
@@ -17,7 +22,7 @@
*
*
* You should have received a copy of the GNU General Public License
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
freq_meter
#(
module
freq_meter
#(
...
...
ahci/sata_ahci_top.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: sata_ahci_top
* <b>Module:</b>sata_ahci_top
* Date: 2015-07-11
* @file sata_ahci_top.v
* Author: Alexey
* @date 2015-07-11
* Description: sata for z7nq top-level module
* @author Alexey
*
* @brief Top of the AHCI implementation of the host adapter
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* sata_ahci_top.v is free software; you can redistribute it and/or modify
* sata_ahci_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
/*
/*
* Takes commands from axi iface as a slave, transfers data with another axi iface as a master
* Takes commands from axi iface as a slave, transfers data with another axi iface as a master
...
...
device/oob_dev.v
View file @
d7d90f4c
/*
******************************************************************************
/*
!
*
Module: oob
*
<b>Module:</b>oob_dev
*
Date: 2015-07-11
*
@file oob_dev.v
*
Author: Alexey
*
@date 2015-07-11
*
Description: sata oob unit implementation
*
@author Alexey
*
*
* Copyright (c) 2015 Elphel, Inc.
* @brief sata oob unit implementation
* oob.v is free software; you can redistribute it and/or modify
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* oob_dev.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* (at your option) any later version.
*
*
* oob.v file is distributed in the hope that it will be useful,
* oob
_dev
.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* GNU General Public License for more details.
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
/*
/*
* For now both device and host shall be set up to SATA2 speeds.
* For now both device and host shall be set up to SATA2 speeds.
* Need to think how to change speed grades on fly (either to broaden
* Need to think how to change speed grades on fly (either to broaden
...
...
device/sata_phy_dev.v
View file @
d7d90f4c
/*
******************************************************************************
/*
!
*
Module: sata_phy
*
<b>Module:</b>sata_phy_dev
*
Date: 2015-07-11
*
@file sata_phy_dev.v
*
Author: Alexey
*
@date 2015-07-11
*
Description: phy-level, including oob, clock generation and GTXE2
*
@author Alexey
*
*
* Copyright (c) 2015 Elphel, Inc.
* @brief phy-level, including oob, clock generation and GTXE2
* sata_phy.v is free software; you can redistribute it and/or modify
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* sata_phy_dev.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* (at your option) any later version.
*
*
* sata_phy.v file is distributed in the hope that it will be useful,
* sata_phy
_dev
.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* GNU General Public License for more details.
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
//`include "oob_dev.v"
//`include "oob_dev.v"
module
sata_phy_dev
#(
module
sata_phy_dev
#(
parameter
DATA_BYTE_WIDTH
=
4
parameter
DATA_BYTE_WIDTH
=
4
...
...
generated/action_decoder.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: action_decoder
* <b>Module:</b>action_decoder
* Date:2016-12-07
* @file action_decoder.v
* Author: auto-generated file, see ahci_fsm_sequence.py
* @date 2016-12-08
* Description: Decode sequencer code to 1-hot actions
* @author auto-generated file, see ahci_fsm_sequence.py
*******************************************************************************/
* @brief Decode sequencer code to 1-hot actions
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
...
...
generated/condition_mux.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: condition_mux
* <b>Module:</b>condition_mux
* Date:2016-12-07
* @file condition_mux.v
* Author: auto-generated file, see ahci_fsm_sequence.py
* @date 2016-12-08
* Description: Select condition
* @author auto-generated file, see ahci_fsm_sequence.py
*******************************************************************************/
* @brief Select condition
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
...
...
host/crc.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: crc
* <b>Module:</b>crc
* Date: 2015-07-11
* @file crc.v
* Author: Alexey
* @date 2015-07-11
* Description: crc calculations for the link layer
* @author Alexey
*
* @brief crc calculations for the link layer
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* crc.v is free software; you can redistribute it and/or modify
* crc.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
/* same as for a scrambler, @ doc p.561 */
/* same as for a scrambler, @ doc p.561 */
// TODO make it parallel, make another widths support
// TODO make it parallel, make another widths support
module
crc
#(
module
crc
#(
...
...
host/drp_other_registers.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: drp_other_registers
* <b>Module:</b>drp_other_registers
* Date:2016-03-13
* @file drp_other_registers.v
* Author: andrey
* @date 2016-03-13
* Description: Additional registers controlled/read back over DRP
* @author Andrey Filippov
*
* @brief Additional registers controlled/read back over DRP
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
*
* Copyright (c) 2016 Elphel, Inc .
* drp_other_registers.v is free software; you can redistribute it and/or modify
* drp_other_registers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -17,7 +22,7 @@
...
@@ -17,7 +22,7 @@
*
*
* You should have received a copy of the GNU General Public License
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
drp_other_registers
#(
module
drp_other_registers
#(
...
...
host/elastic1632.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: elastic1632
* <b>Module:</b>elastic1632
* Date:2016-02-03
* @file elastic1632.v
* Author: andrey
* @date 2016-02-03
* Description: Elastic buffer with 16-bit data input and 32-bit output
* @author Andrey Filippov
*
* @brief Elastic buffer with 16-bit data input and 32-bit output
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
*
* Copyright (c) 2016 Elphel, Inc .
* elastic1632.v is free software; you can redistribute it and/or modify
* elastic1632.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -17,7 +22,7 @@
...
@@ -17,7 +22,7 @@
*
*
* You should have received a copy of the GNU General Public License
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
elastic1632
#(
module
elastic1632
#(
...
...
host/gtx_10x8dec.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: gtx_10x8dec
* <b>Module:</b>gtx_10x8dec
* Date: 2015-07-11
* @file gtx_10x8dec.v
* Author: Alexey
* @date 2015-07-11
* Description: 8x10 encoder implementation
* @author Alexey
*
* @brief 8x10 encoder implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_10x8dec.v is free software; you can redistribute it and/or modify
* gtx_10x8dec.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
module
gtx_10x8dec
(
module
gtx_10x8dec
(
input
wire
rst
,
input
wire
rst
,
input
wire
clk
,
input
wire
clk
,
...
...
host/gtx_8x10enc.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: gtx_8x10enc
* <b>Module:</b>gtx_8x10enc
* Date: 2015-07-11
* @file gtx_8x10enc.v
* Author: Alexey
* @date 2015-07-11
* Description: 8x10 encoder implementation
* @author Alexey
*
* @brief 8x10 encoder implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_8x10enc.v is free software; you can redistribute it and/or modify
* gtx_8x10enc.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
module
gtx_8x10enc
(
module
gtx_8x10enc
(
input
wire
rst
,
input
wire
rst
,
input
wire
clk
,
input
wire
clk
,
...
...
host/gtx_comma_align.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: gtx_comma_align
* <b>Module:</b>gtx_comma_align
* Date: 2015-07-11
* @file gtx_comma_align.v
* Author: Alexey
* @date 2015-07-11
* Description: comma aligner implementation
* @author Alexey
*
* @brief comma aligner implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_comma_align.v is free software; you can redistribute it and/or modify
* gtx_comma_align.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
module
gtx_comma_align
(
module
gtx_comma_align
(
input
wire
rst
,
input
wire
rst
,
input
wire
clk
,
input
wire
clk
,
...
...
host/gtx_elastic.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: gtx_elastic
* <b>Module:</b>gtx_elastic
* Date: 2015-07-11
* @file gtx_elastic.v
* Author: Alexey
* @date 2015-07-11
* Description: elastic buffer implementation
* @author Alexey
*
* @brief elastic buffer implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_elastic.v is free software; you can redistribute it and/or modify
* gtx_elastic.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
module
gtx_elastic
#(
module
gtx_elastic
#(
parameter
DEPTH_LOG2
=
4
,
// 3, // => 8 total rows
parameter
DEPTH_LOG2
=
4
,
// 3, // => 8 total rows
parameter
OFFSET
=
8
// 4 // distance between read and write pointers, = wr_ptr - rd_ptr
parameter
OFFSET
=
8
// 4 // distance between read and write pointers, = wr_ptr - rd_ptr
...
...
host/gtx_wrap.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: gtx_wrap
* <b>Module:</b>gtx_wrap
* Date: 2015-08-24
* @file gtx_wrap.v
* Author: Alexey
* @date 2015-08-24
* Description: shall replace gtx's PCS part functions, bypassing PCS itself in gtx
* @author Alexey
*
* @brief shall replace gtx's PCS part functions, bypassing PCS itself in gtx
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_wrap.v is free software; you can redistribute it and/or modify
* gtx_wrap.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
//`include "gtx_8x10enc.v"
//`include "gtx_8x10enc.v"
//`include "gtx_10x8dec.v"
//`include "gtx_10x8dec.v"
//`include "gtx_comma_align.v"
//`include "gtx_comma_align.v"
...
...
host/link.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: link
* <b>Module:</b>link
* Date: 2015-07-11
* @file link.v
* Author: Alexey
* @date 2015-07-11
* Description: sata link layer implementation
* @author Alexey
*
* @brief sata link layer implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* link.v is free software; you can redistribute it and/or modify
* link.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
//`include "scrambler.v"
//`include "scrambler.v"
//`include "crc.v"
//`include "crc.v"
module
link
#(
module
link
#(
...
...
host/oob.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: oob
* <b>Module:</b>oob
* Date: 2015-07-11
* @file oob.v
* Author: Alexey
* @date 2015-07-11
* Description: sata oob unit implementation
* @author Alexey
*
* @brief sata oob unit implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* oob.v is free software; you can redistribute it and/or modify
* oob.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
/*
/*
* For now both device and host shall be set up to SATA2 speeds.
* For now both device and host shall be set up to SATA2 speeds.
* Need to think how to change speed grades on fly (either to broaden
* Need to think how to change speed grades on fly (either to broaden
...
...
host/oob_ctrl.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: oob_ctrl
* <b>Module:</b>oob_ctrl
* Date: 2015-07-11
* @file oob_ctrl.v
* Author: Alexey
* @date 2015-07-11
* Description: module to start oob sequences and to handle errors
* @author Alexey
*
* @brief module to start oob sequences and to handle errors
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* oob_ctrl.v is free software; you can redistribute it and/or modify
* oob_ctrl.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
//`include "oob.v"
//`include "oob.v"
module
oob_ctrl
#(
module
oob_ctrl
#(
parameter
DATA_BYTE_WIDTH
=
4
,
parameter
DATA_BYTE_WIDTH
=
4
,
...
...
host/sata_phy.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: sata_phy
* <b>Module:</b>sata_phy
* Date: 2015-07-11
* @file sata_phy.v
* Author: Alexey
* @date 2015-07-11
* Description: phy-level, including oob, clock generation and GTXE2
* @author Alexey
*
* @brief phy-level, including oob, clock generation and GTXE2
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* sata_phy.v is free software; you can redistribute it and/or modify
* sata_phy.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
//`include "oob_ctrl.v"
//`include "oob_ctrl.v"
//`include "gtx_wrap.v"
//`include "gtx_wrap.v"
module
sata_phy
#(
module
sata_phy
#(
...
...
host/scrambler.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: scrambler
* <b>Module:</b>scrambler
* Date: 2015-07-11
* @file scrambler.v
* Author: Alexey
* @date 2015-07-11
* Description: a scrambler for the link layer
* @author Alexey
*
* @brief a scrambler for the link layer
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* scrambler.v is free software; you can redistribute it and/or modify
* scrambler.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
/*
/*
* Algorithm is taken from the doc, p.565. TODO make it parallel
* Algorithm is taken from the doc, p.565. TODO make it parallel
*/
*/
...
...
includes/ahci_defaults.vh
View file @
d7d90f4c
...
@@ -2,6 +2,6 @@
...
@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h00000000000000000000000000000000000000000101000
A
001000000001FFFE)
, .INIT_0C (256'h00000000000000000000000000000000000000000101000
B
001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
includes/ahci_localparams.vh
View file @
d7d90f4c
...
@@ -97,7 +97,7 @@
...
@@ -97,7 +97,7 @@
// RO: HBA Revision ID
// RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'h
a
;
localparam PCI_Header__RID__RID__DFLT = 'h
b
;
// RO: Base Class Code: 1 - Mass Storage Device
// RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
...
...
py393sata/ahci_fsm_sequence.py
View file @
d7d90f4c
...
@@ -490,13 +490,14 @@ def bin_cnk (n,k):
...
@@ -490,13 +490,14 @@ def bin_cnk (n,k):
result
.
append
(
d
)
result
.
append
(
d
)
return
result
return
result
def
condition_mux_verilog
(
conditions
,
condition_vals
,
module_name
,
fanout
,
file
=
None
):
def
condition_mux_verilog
(
conditions
,
condition_vals
,
module_name
,
fanout
,
header_file
=
""
,
file
=
None
):
header_template
=
"""/*******************************************************************************
header_template
=
"""/*!
* Module:
%
s
* <b>Module:</b>
%
s
* Date:
%
s
* @file
%
s
* Author: auto-generated file, see
%
s
* @date
%
s
* Description: Select condition
* @author auto-generated file, see
%
s
*******************************************************************************/
* @brief Select condition
*/
`timescale 1ns/1ps
`timescale 1ns/1ps
...
@@ -505,6 +506,10 @@ module %s (
...
@@ -505,6 +506,10 @@ module %s (
input ce, // enable recording all conditions
input ce, // enable recording all conditions
input [
%2
d:0] sel,
input [
%2
d:0] sel,
output condition,"""
output condition,"""
if
header_file
:
header_file
=
os
.
path
.
basename
(
header_file
)
else
:
header_file
=
""
v
=
max
(
condition_vals
.
values
())
v
=
max
(
condition_vals
.
values
())
num_inputs
=
0
;
num_inputs
=
0
;
while
v
:
while
v
:
...
@@ -512,7 +517,7 @@ module %s (
...
@@ -512,7 +517,7 @@ module %s (
v
>>=
1
v
>>=
1
maximal_length
=
max
([
len
(
n
)
for
n
in
conditions
])
maximal_length
=
max
([
len
(
n
)
for
n
in
conditions
])
numregs
=
(
len
(
conditions
)
+
fanout
)
//
fanout
# one more bit for 'always' (sel == 0)
numregs
=
(
len
(
conditions
)
+
fanout
)
//
fanout
# one more bit for 'always' (sel == 0)
header
=
header_template
%
(
module_name
,
datetime
.
date
.
today
()
.
isoformat
(),
os
.
path
.
basename
(
__file__
),
module_name
,
num_inputs
-
1
)
header
=
header_template
%
(
module_name
,
header_file
,
datetime
.
date
.
today
()
.
isoformat
(),
os
.
path
.
basename
(
__file__
),
module_name
,
num_inputs
-
1
)
print
(
header
,
file
=
file
)
print
(
header
,
file
=
file
)
for
input_name
in
conditions
[:
len
(
conditions
)
-
1
]:
for
input_name
in
conditions
[:
len
(
conditions
)
-
1
]:
print
(
" input
%
s,"
%
(
input_name
),
file
=
file
)
print
(
" input
%
s,"
%
(
input_name
),
file
=
file
)
...
@@ -564,13 +569,14 @@ module %s (
...
@@ -564,13 +569,14 @@ module %s (
print
(
"endmodule"
,
file
=
file
)
print
(
"endmodule"
,
file
=
file
)
def
action_decoder_verilog
(
actions
,
action_vals
,
module_name
,
file
=
None
):
def
action_decoder_verilog
(
actions
,
action_vals
,
module_name
,
header_file
=
""
,
file
=
None
):
header_template
=
"""/*******************************************************************************
header_template
=
"""/*!
* Module:
%
s
* <b>Module:</b>
%
s
* Date:
%
s
* @file
%
s
* Author: auto-generated file, see
%
s
* @date
%
s
* Description: Decode sequencer code to 1-hot actions
* @author auto-generated file, see
%
s
*******************************************************************************/
* @brief Decode sequencer code to 1-hot actions
*/
`timescale 1ns/1ps
`timescale 1ns/1ps
...
@@ -578,6 +584,10 @@ module %s (
...
@@ -578,6 +584,10 @@ module %s (
input clk,
input clk,
input enable,
input enable,
input [
%2
d:0] data,"""
input [
%2
d:0] data,"""
if
header_file
:
header_file
=
os
.
path
.
basename
(
header_file
)
else
:
header_file
=
""
v
=
max
(
action_vals
.
values
())
v
=
max
(
action_vals
.
values
())
num_inputs
=
0
;
num_inputs
=
0
;
while
v
:
while
v
:
...
@@ -591,7 +601,7 @@ module %s (
...
@@ -591,7 +601,7 @@ module %s (
names
.
append
(
a
)
names
.
append
(
a
)
maximal_length
=
max
([
len
(
n
)
for
n
in
names
])
maximal_length
=
max
([
len
(
n
)
for
n
in
names
])
header
=
header_template
%
(
module_name
,
datetime
.
date
.
today
()
.
isoformat
(),
os
.
path
.
basename
(
__file__
),
module_name
,
num_inputs
-
1
)
header
=
header_template
%
(
module_name
,
header_file
,
datetime
.
date
.
today
()
.
isoformat
(),
os
.
path
.
basename
(
__file__
),
module_name
,
num_inputs
-
1
)
print
(
header
,
file
=
file
)
print
(
header
,
file
=
file
)
for
output_name
in
names
[:
len
(
names
)
-
1
]:
for
output_name
in
names
[:
len
(
names
)
-
1
]:
print
(
" output reg
%
s,"
%
(
output_name
),
file
=
file
)
print
(
" output reg
%
s,"
%
(
output_name
),
file
=
file
)
...
@@ -862,14 +872,14 @@ if not action_decoder_verilog_path:
...
@@ -862,14 +872,14 @@ if not action_decoder_verilog_path:
action_decoder_verilog
(
actions
,
action_vals
,
action_decoder_module_name
)
action_decoder_verilog
(
actions
,
action_vals
,
action_decoder_module_name
)
else
:
else
:
with
open
(
os
.
path
.
abspath
(
os
.
path
.
join
(
os
.
path
.
dirname
(
__file__
),
action_decoder_verilog_path
)),
"w"
)
as
out_file
:
with
open
(
os
.
path
.
abspath
(
os
.
path
.
join
(
os
.
path
.
dirname
(
__file__
),
action_decoder_verilog_path
)),
"w"
)
as
out_file
:
action_decoder_verilog
(
actions
,
action_vals
,
action_decoder_module_name
,
out_file
)
action_decoder_verilog
(
actions
,
action_vals
,
action_decoder_module_name
,
action_decoder_verilog_path
,
out_file
)
print
(
"AHCI FSM actions decoder is written to
%
s"
%
(
os
.
path
.
abspath
(
os
.
path
.
join
(
os
.
path
.
dirname
(
__file__
),
action_decoder_verilog_path
))))
print
(
"AHCI FSM actions decoder is written to
%
s"
%
(
os
.
path
.
abspath
(
os
.
path
.
join
(
os
.
path
.
dirname
(
__file__
),
action_decoder_verilog_path
))))
if
not
condition_mux_verilog_path
:
if
not
condition_mux_verilog_path
:
condition_mux_verilog
(
conditions
,
condition_vals
,
condition_mux_module_name
,
condition_mux_fanout
)
condition_mux_verilog
(
conditions
,
condition_vals
,
condition_mux_module_name
,
condition_mux_fanout
)
else
:
else
:
with
open
(
os
.
path
.
abspath
(
os
.
path
.
join
(
os
.
path
.
dirname
(
__file__
),
condition_mux_verilog_path
)),
"w"
)
as
out_file
:
with
open
(
os
.
path
.
abspath
(
os
.
path
.
join
(
os
.
path
.
dirname
(
__file__
),
condition_mux_verilog_path
)),
"w"
)
as
out_file
:
condition_mux_verilog
(
conditions
,
condition_vals
,
condition_mux_module_name
,
condition_mux_fanout
,
out_file
)
condition_mux_verilog
(
conditions
,
condition_vals
,
condition_mux_module_name
,
condition_mux_fanout
,
condition_mux_verilog_path
,
out_file
)
print
(
"AHCI FSM conditions multiplexer is written to
%
s"
%
(
os
.
path
.
abspath
(
os
.
path
.
join
(
os
.
path
.
dirname
(
__file__
),
condition_mux_verilog_path
))))
print
(
"AHCI FSM conditions multiplexer is written to
%
s"
%
(
os
.
path
.
abspath
(
os
.
path
.
join
(
os
.
path
.
dirname
(
__file__
),
condition_mux_verilog_path
))))
code
=
code_generator
(
sequence
,
action_vals
,
condition_vals
,
labels
)
code
=
code_generator
(
sequence
,
action_vals
,
condition_vals
,
labels
)
...
...
py393sata/create_ahci_registers.py
View file @
d7d90f4c
...
@@ -28,7 +28,10 @@ __status__ = "Development"
...
@@ -28,7 +28,10 @@ __status__ = "Development"
# All unspecified ranges/fields default to fT:RO, fC:0 (readonly, reset value = 0)
# All unspecified ranges/fields default to fT:RO, fC:0 (readonly, reset value = 0)
#RID = 0x02 # Revision ID (use for bitstream version)
#RID = 0x02 # Revision ID (use for bitstream version)
RID
=
0x0a
# Revision ID
"""
**** Modify next value for new file versions, re-run this file *****
"""
RID
=
0x0b
# Revision ID
VID
=
0xfffe
# What to use for non-PCI "vendorID"?
VID
=
0xfffe
# What to use for non-PCI "vendorID"?
DID
=
0x0001
DID
=
0x0001
SSVID
=
0xfffe
SSVID
=
0xfffe
...
...
system_defines.vh
View file @
d7d90f4c
/*!
* @file system_defines.vh
* @date 2015-02-28
* @author Andrey Filippov
*
* @brief Preprocessor macros definitions to be included in AHCI SATA project
* files when built as a stanalone project (https://github.com/Elphel/x393_sata).
* Not used when AHCI SATA is a part of the x393 project.
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* system_defines.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* system_defines.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
// This file may be used to define same pre-processor macros to be included into each parsed file
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
`define SYSTEM_DEFINES
...
...
wrapper/GTXE2_GPL.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: GTXE2_GPL
* <b>Module:</b>GTXE2_GPL
* Date: 2015-09-08
* @file GTXE2_GPL.v
* Author: Alexey
* @date 2015-09-08
* Description: emulates GTXE2_CHANNEL primitive behaviour.
* @author Alexey
*
* @brief emulates GTXE2_CHANNEL primitive behaviour.
* The file is gathered from multiple files
* The file is gathered from multiple files
*
*
* Copyright (c) 2015 Elphel, Inc.
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* GTXE2_GPL.v is free software; you can redistribute it and/or modify
* GTXE2_GPL.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -31,7 +36,7 @@
...
@@ -31,7 +36,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
/**
/**
* Original unisims primitive's interfaces, according to xilinx's user guide:
* Original unisims primitive's interfaces, according to xilinx's user guide:
* "7 Series FPGAs GTX/GTH Transceivers User Guide UG476(v1.11)", which is further
* "7 Series FPGAs GTX/GTH Transceivers User Guide UG476(v1.11)", which is further
...
...
wrapper/clock_inverter.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: clock_inverter
* <b>Module:</b>clock_inverter
* Date:2016-02-11
* @file clock_inverter.v
* Author: andrey
* @date 2016-02-11
* Description: Glitch-free clock controlled inverter
* @author Andrey Filippov
*
* @brief Glitch-free clock controlled inverter
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
*
* Copyright (c) 2016 Elphel, Inc .
* clock_inverter.v is free software; you can redistribute it and/or modify
* clock_inverter.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -17,7 +22,7 @@
...
@@ -17,7 +22,7 @@
*
*
* You should have received a copy of the GNU General Public License
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
******************************************************************************
/
*/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
clock_inverter
(
module
clock_inverter
(
...
...
wrapper/gtxe2_channel_wrapper.v
View file @
d7d90f4c
/*******************************************************************************
/*!
* Module: gtxe2_channel_wrapper
* <b>Module:</b>gtxe2_channel_wrapper
* Date: 2015-09-07
* @file gtxe2_channel_wrapper.v
* Author: Alexey
* @date 2015-09-07
* Description: wrapper to switch between closed unisims primitive and open-source one
* @author Alexey
*
* @brief wrapper to switch between closed unisims primitive and open-source one
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
*
* Copyright (c) 2015 Elphel, Inc.
* GTXE2_GPL.v is free software; you can redistribute it and/or modify
* GTXE2_GPL.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
...
@@ -30,7 +35,7 @@
...
@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
* with at least one of the Free Software programs.
*
******************************************************************************
/
*/
`include
"system_defines.vh"
`include
"system_defines.vh"
module
gtxe2_channel_wrapper
(
module
gtxe2_channel_wrapper
(
// clocking ports, UG476 p.37
// clocking ports, UG476 p.37
...
...
x393_sata.bit
View file @
d7d90f4c
No preview for this file type
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment