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Commit d7d90f4c authored by Andrey Filippov's avatar Andrey Filippov
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Updated headers for doxygen, matching those in x393 project

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ahci/ahci_ctrl_stat.v
View file @ d7d90f4c
/*******************************************************************************
* Module: ahci_ctrl_stat
* Date:2016-01-12
* Author: Andrey Filippov
* Description: Copy of significant register fields, updating them in
/*!
* <b>Module:</b>ahci_ctrl_stat
* @file ahci_ctrl_stat.v
* @date 2016-01-12
* @author Andrey Filippov
*
* @brief Copy of significant register fields, updating them in
* axi_ahci_regs registers (software accessible)
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_ctrl_stat.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -18,7 +23,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_ctrl_stat #(
......
ahci/ahci_dma.v
View file @ d7d90f4c
/*******************************************************************************
* Module: ahci_dma
* Date:2016-01-01
* Author: Andrey Filippov
* Description: DMA R/W over 64-AXI channel for AHCI implementation
/*!
* <b>Module:</b>ahci_dma
* @file ahci_dma.v
* @date 2016-01-01
* @author Andrey Filippov
*
* @brief DMA R/W over 64-AXI channel for AHCI implementation
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_dma.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma (
......
ahci/ahci_dma_rd_fifo.v
View file @ d7d90f4c
/*******************************************************************************
* Module: ahci_dma_rd_fifo
* Date:2016-01-01
* Author: Andrey Filippov
* Description: cross clocks, word-realign, 64->32
/*!
* <b>Module:</b>ahci_dma_rd_fifo
* @file ahci_dma_rd_fifo.v
* @date 2016-01-01
* @author Andrey Filippov
*
* @brief cross clocks, word-realign, 64->32
* Convertion from x64 QWORD-aligned AXI data @hclk to
* 32-bit word-aligned data at mclk
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_dma_rd_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -32,7 +37,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma_rd_fifo#(
......
ahci/ahci_dma_rd_stuff.v
View file @ d7d90f4c
/*******************************************************************************
* Module: ahci_dma_rd_stuff
* Date:2016-01-01
* Author: Andrey Filippov
* Description: Stuff DWORD data with missing words into continuous 32-bit data
/*!
* <b>Module:</b>ahci_dma_rd_stuff
* @file ahci_dma_rd_stuff.v
* @date 2016-01-01
* @author Andrey Filippov
*
* @brief Stuff DWORD data with missing words into continuous 32-bit data
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_dma_rd_stuff.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma_rd_stuff(
......
ahci/ahci_dma_wr_fifo.v
View file @ d7d90f4c
/*******************************************************************************
* Module: ahci_dma_wr_fifo
* Date:2016-01-02
* Author: Andrey Filippov
* Description: cross clocks, word-realign, 32 -> 64 with byte write mask
/*!
* <b>Module:</b>ahci_dma_wr_fifo
* @file ahci_dma_wr_fifo.v
* @date 2016-01-02
* @author Andrey Filippov
*
* @brief cross clocks, word-realign, 32 -> 64 with byte write mask
* Convertion from x32 DWORD data received from FIS-es @ mclk to QWORD-aligned
* AXI data @hclk
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_dma_wr_fifo.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -32,7 +37,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_dma_wr_fifo#(
......
ahci/ahci_fis_receive.v
View file @ d7d90f4c
/*******************************************************************************
* Module: ahci_fis_receive
* Date:2016-01-06
* Author: Andrey Filippov
* Description: Receives incoming FIS-es, forwards DMA ones to DMA engine
/*!
* <b>Module:</b>ahci_fis_receive
* @file ahci_fis_receive.v
* @date 2016-01-06
* @author Andrey Filippov
*
* @brief Receives incoming FIS-es, forwards DMA ones to DMA engine
* Stores received FIS-es if requested
*
* 'fis_first_vld' is asserted when the FIFO output contains first DWORD
......@@ -13,7 +15,10 @@
* one of the 3 states (fis_ok, fis_err and fis_ferr) are raised
* This module also receives/updates device signature and PxTFD ERR and STS.
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_fis_receive.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -26,7 +31,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_fis_receive#(
......
ahci/ahci_fis_transmit.v
View file @ d7d90f4c
/*******************************************************************************
* Module: ahci_fis_transmit
* Date:2016-01-07
* Author: Andrey Filippov
* Description: Fetches commands, command tables, creates/sends FIS
/*!
* <b>Module:</b>ahci_fis_transmit
* @file ahci_fis_transmit.v
* @date 2016-01-07
* @author Andrey Filippov
*
* @brief Fetches commands, command tables, creates/sends FIS
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_fis_transmit.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_fis_transmit #(
......
ahci/ahci_fsm.v
View file @ d7d90f4c
/*******************************************************************************
* Module: ahci_fsm
* Date:2016-01-10
* Author: Andrey Filippov
* Description: AHCI host+port0 state machine
/*!
* <b>Module:</b>ahci_fsm
* @file ahci_fsm.v
* @date 2016-01-10
* @author Andrey Filippov
*
* @brief AHCI host+port0 state machine
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_fsm.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_fsm
......@@ -318,7 +323,6 @@ module ahci_fsm
wire clear_pisn32; // additional clear when in P:NotRunning state
assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending
assign update_all = fsm_jump[0];
assign ssts_ipm_dnp = phy_ready_chng_r && (phy_ready_prev == 0); // device not present or communication not established
......
ahci/ahci_sata_layers.v
View file @ d7d90f4c
/*******************************************************************************
* Module: ahci_sata_layers
* Date:2016-01-19
* Author: Andrey Filippov
* Description: Link and PHY SATA layers
/*!
* <b>Module:</b>ahci_sata_layers
* @file ahci_sata_layers.v
* @date 2016-01-19
* @author Andrey Filippov
*
* @brief Link and PHY SATA layers
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_sata_layers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_sata_layers #(
......
ahci/ahci_top.v
View file @ d7d90f4c
/*******************************************************************************
* Module: ahci_top
* Date:2016-01-09
* Author: Andrey Filippov
* Description: Top module of the AHCI implementation
/*!
* <b>Module:</b>ahci_top
* @file ahci_top.v
* @date 2016-01-09
* @author Andrey Filippov
*
* @brief Top module of the AHCI implementation
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module ahci_top#(
......
ahci/axi_ahci_regs.v
View file @ d7d90f4c
/*******************************************************************************
* Module: axi_ahci_regs
* Date:2015-12-29
* Author: Andrey Filippov
* Description: Registers for single-port AHCI over AXI implementation
/*!
* <b>Module:</b>axi_ahci_regs
* @file axi_ahci_regs.v
* @date 2015-12-29
* @author Andrey Filippov
*
* @brief Registers for single-port AHCI over AXI implementation
* Combination of PCI Headers, PCI power management, and HBA memory
* 128 DWORD registers
* Registers, with bits being RO, RW, RWC, RW1
*
* Copyright (c) 2015 Elphel, Inc .
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* axi_ahci_regs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -33,7 +38,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
......
ahci/axi_hp_abort.v
View file @ d7d90f4c
/*******************************************************************************
* Module: axi_hp_abort
* Date:2016-02-07
* Author: Andrey Filippov
* Description: Trying to gracefully reset AXI HP after aborted transmission
/*!
* <b>Module:</b>axi_hp_abort
* @file axi_hp_abort.v
* @date 2016-02-07
* @author Andrey Filippov
*
* @brief Trying to gracefully reset AXI HP after aborted transmission
* For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0)
* For write - keep track aof all what was sent so far, assuming aw is always ahead of w
* Reset only by global reset (system POR) - probably it is not possible to just
* reset PL or relaod bitfile,
*
* Copyright (c) 2016 Elphel, Inc .
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* axi_hp_abort.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -21,7 +26,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module axi_hp_abort(
......
ahci/freq_meter.v
View file @ d7d90f4c
/*******************************************************************************
* Module: freq_meter
* Date:2016-02-13
* Author: Andrey Filippov
* Description: Measure device clock frequency to set the local clock
/*!
* <b>Module:</b>freq_meter
* @file freq_meter.v
* @date 2016-02-13
* @author Andrey Filippov
*
* @brief Measure device clock frequency to set the local clock
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* freq_meter.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module freq_meter#(
......
ahci/sata_ahci_top.v
View file @ d7d90f4c
/*******************************************************************************
* Module: sata_ahci_top
* Date: 2015-07-11
* Author: Alexey
* Description: sata for z7nq top-level module
/*!
* <b>Module:</b>sata_ahci_top
* @file sata_ahci_top.v
* @date 2015-07-11
* @author Alexey
*
* @brief Top of the AHCI implementation of the host adapter
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* sata_ahci_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`timescale 1ns/1ps
/*
* Takes commands from axi iface as a slave, transfers data with another axi iface as a master
......
device/oob_dev.v
View file @ d7d90f4c
/*******************************************************************************
* Module: oob
* Date: 2015-07-11
* Author: Alexey
* Description: sata oob unit implementation
/*!
* <b>Module:</b>oob_dev
* @file oob_dev.v
* @date 2015-07-11
* @author Alexey
*
* Copyright (c) 2015 Elphel, Inc.
* oob.v is free software; you can redistribute it and/or modify
* @brief sata oob unit implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* oob_dev.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* oob.v file is distributed in the hope that it will be useful,
* oob_dev.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
/*
* For now both device and host shall be set up to SATA2 speeds.
* Need to think how to change speed grades on fly (either to broaden
......
device/sata_phy_dev.v
View file @ d7d90f4c
/*******************************************************************************
* Module: sata_phy
* Date: 2015-07-11
* Author: Alexey
* Description: phy-level, including oob, clock generation and GTXE2
/*!
* <b>Module:</b>sata_phy_dev
* @file sata_phy_dev.v
* @date 2015-07-11
* @author Alexey
*
* Copyright (c) 2015 Elphel, Inc.
* sata_phy.v is free software; you can redistribute it and/or modify
* @brief phy-level, including oob, clock generation and GTXE2
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* sata_phy_dev.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sata_phy.v file is distributed in the hope that it will be useful,
* sata_phy_dev.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
//`include "oob_dev.v"
module sata_phy_dev #(
parameter DATA_BYTE_WIDTH = 4
......
generated/action_decoder.v
View file @ d7d90f4c
/*******************************************************************************
* Module: action_decoder
* Date:2016-12-07
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions
*******************************************************************************/
/*!
* <b>Module:</b>action_decoder
* @file action_decoder.v
* @date 2016-12-08
* @author auto-generated file, see ahci_fsm_sequence.py
* @brief Decode sequencer code to 1-hot actions
*/
`timescale 1ns/1ps
......
generated/condition_mux.v
View file @ d7d90f4c
/*******************************************************************************
* Module: condition_mux
* Date:2016-12-07
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition
*******************************************************************************/
/*!
* <b>Module:</b>condition_mux
* @file condition_mux.v
* @date 2016-12-08
* @author auto-generated file, see ahci_fsm_sequence.py
* @brief Select condition
*/
`timescale 1ns/1ps
......
host/crc.v
View file @ d7d90f4c
/*******************************************************************************
* Module: crc
* Date: 2015-07-11
* Author: Alexey
* Description: crc calculations for the link layer
/*!
* <b>Module:</b>crc
* @file crc.v
* @date 2015-07-11
* @author Alexey
*
* @brief crc calculations for the link layer
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* crc.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
/* same as for a scrambler, @ doc p.561 */
// TODO make it parallel, make another widths support
module crc #(
......
host/drp_other_registers.v
View file @ d7d90f4c
/*******************************************************************************
* Module: drp_other_registers
* Date:2016-03-13
* Author: andrey
* Description: Additional registers controlled/read back over DRP
/*!
* <b>Module:</b>drp_other_registers
* @file drp_other_registers.v
* @date 2016-03-13
* @author Andrey Filippov
*
* @brief Additional registers controlled/read back over DRP
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* drp_other_registers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module drp_other_registers#(
......
host/elastic1632.v
View file @ d7d90f4c
/*******************************************************************************
* Module: elastic1632
* Date:2016-02-03
* Author: andrey
* Description: Elastic buffer with 16-bit data input and 32-bit output
/*!
* <b>Module:</b>elastic1632
* @file elastic1632.v
* @date 2016-02-03
* @author Andrey Filippov
*
* @brief Elastic buffer with 16-bit data input and 32-bit output
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* elastic1632.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module elastic1632#(
......
host/gtx_10x8dec.v
View file @ d7d90f4c
/*******************************************************************************
* Module: gtx_10x8dec
* Date: 2015-07-11
* Author: Alexey
* Description: 8x10 encoder implementation
/*!
* <b>Module:</b>gtx_10x8dec
* @file gtx_10x8dec.v
* @date 2015-07-11
* @author Alexey
*
* @brief 8x10 encoder implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_10x8dec.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
module gtx_10x8dec(
input wire rst,
input wire clk,
......
host/gtx_8x10enc.v
View file @ d7d90f4c
/*******************************************************************************
* Module: gtx_8x10enc
* Date: 2015-07-11
* Author: Alexey
* Description: 8x10 encoder implementation
/*!
* <b>Module:</b>gtx_8x10enc
* @file gtx_8x10enc.v
* @date 2015-07-11
* @author Alexey
*
* @brief 8x10 encoder implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_8x10enc.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
module gtx_8x10enc(
input wire rst,
input wire clk,
......
host/gtx_comma_align.v
View file @ d7d90f4c
/*******************************************************************************
* Module: gtx_comma_align
* Date: 2015-07-11
* Author: Alexey
* Description: comma aligner implementation
/*!
* <b>Module:</b>gtx_comma_align
* @file gtx_comma_align.v
* @date 2015-07-11
* @author Alexey
*
* @brief comma aligner implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_comma_align.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
module gtx_comma_align(
input wire rst,
input wire clk,
......
host/gtx_elastic.v
View file @ d7d90f4c
/*******************************************************************************
* Module: gtx_elastic
* Date: 2015-07-11
* Author: Alexey
* Description: elastic buffer implementation
/*!
* <b>Module:</b>gtx_elastic
* @file gtx_elastic.v
* @date 2015-07-11
* @author Alexey
*
* @brief elastic buffer implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_elastic.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
module gtx_elastic #(
parameter DEPTH_LOG2 = 4, // 3, // => 8 total rows
parameter OFFSET = 8 // 4 // distance between read and write pointers, = wr_ptr - rd_ptr
......
host/gtx_wrap.v
View file @ d7d90f4c
/*******************************************************************************
* Module: gtx_wrap
* Date: 2015-08-24
* Author: Alexey
* Description: shall replace gtx's PCS part functions, bypassing PCS itself in gtx
/*!
* <b>Module:</b>gtx_wrap
* @file gtx_wrap.v
* @date 2015-08-24
* @author Alexey
*
* @brief shall replace gtx's PCS part functions, bypassing PCS itself in gtx
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* gtx_wrap.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
//`include "gtx_8x10enc.v"
//`include "gtx_10x8dec.v"
//`include "gtx_comma_align.v"
......
host/link.v
View file @ d7d90f4c
/*******************************************************************************
* Module: link
* Date: 2015-07-11
* Author: Alexey
* Description: sata link layer implementation
/*!
* <b>Module:</b>link
* @file link.v
* @date 2015-07-11
* @author Alexey
*
* @brief sata link layer implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* link.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
//`include "scrambler.v"
//`include "crc.v"
module link #(
......
host/oob.v
View file @ d7d90f4c
/*******************************************************************************
* Module: oob
* Date: 2015-07-11
* Author: Alexey
* Description: sata oob unit implementation
/*!
* <b>Module:</b>oob
* @file oob.v
* @date 2015-07-11
* @author Alexey
*
* @brief sata oob unit implementation
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* oob.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
/*
* For now both device and host shall be set up to SATA2 speeds.
* Need to think how to change speed grades on fly (either to broaden
......
host/oob_ctrl.v
View file @ d7d90f4c
/*******************************************************************************
* Module: oob_ctrl
* Date: 2015-07-11
* Author: Alexey
* Description: module to start oob sequences and to handle errors
/*!
* <b>Module:</b>oob_ctrl
* @file oob_ctrl.v
* @date 2015-07-11
* @author Alexey
*
* @brief module to start oob sequences and to handle errors
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* oob_ctrl.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
//`include "oob.v"
module oob_ctrl #(
parameter DATA_BYTE_WIDTH = 4,
......
host/sata_phy.v
View file @ d7d90f4c
/*******************************************************************************
* Module: sata_phy
* Date: 2015-07-11
* Author: Alexey
* Description: phy-level, including oob, clock generation and GTXE2
/*!
* <b>Module:</b>sata_phy
* @file sata_phy.v
* @date 2015-07-11
* @author Alexey
*
* @brief phy-level, including oob, clock generation and GTXE2
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* sata_phy.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
//`include "oob_ctrl.v"
//`include "gtx_wrap.v"
module sata_phy #(
......
host/scrambler.v
View file @ d7d90f4c
/*******************************************************************************
* Module: scrambler
* Date: 2015-07-11
* Author: Alexey
* Description: a scrambler for the link layer
/*!
* <b>Module:</b>scrambler
* @file scrambler.v
* @date 2015-07-11
* @author Alexey
*
* @brief a scrambler for the link layer
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* scrambler.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
/*
* Algorithm is taken from the doc, p.565. TODO make it parallel
*/
......
includes/ahci_defaults.vh
View file @ d7d90f4c
......@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h00000000000000000000000000000000000000000101000A001000000001FFFE)
, .INIT_0C (256'h00000000000000000000000000000000000000000101000B001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
includes/ahci_localparams.vh
View file @ d7d90f4c
......@@ -97,7 +97,7 @@
// RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'ha;
localparam PCI_Header__RID__RID__DFLT = 'hb;
// RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
......
py393sata/ahci_fsm_sequence.py
View file @ d7d90f4c
......@@ -490,13 +490,14 @@ def bin_cnk (n,k):
result.append(d)
return result
def condition_mux_verilog(conditions, condition_vals, module_name, fanout, file=None):
header_template="""/*******************************************************************************
* Module: %s
* Date:%s
* Author: auto-generated file, see %s
* Description: Select condition
*******************************************************************************/
def condition_mux_verilog(conditions, condition_vals, module_name, fanout, header_file="", file=None):
header_template="""/*!
* <b>Module:</b>%s
* @file %s
* @date %s
* @author auto-generated file, see %s
* @brief Select condition
*/
`timescale 1ns/1ps
......@@ -505,6 +506,10 @@ module %s (
input ce, // enable recording all conditions
input [%2d:0] sel,
output condition,"""
if header_file:
header_file = os.path.basename(header_file)
else:
header_file=""
v=max(condition_vals.values())
num_inputs = 0;
while v:
......@@ -512,7 +517,7 @@ module %s (
v >>= 1
maximal_length = max([len(n) for n in conditions])
numregs = (len(conditions) + fanout) // fanout # one more bit for 'always' (sel == 0)
header = header_template%(module_name, datetime.date.today().isoformat(), os.path.basename(__file__), module_name, num_inputs-1)
header = header_template%(module_name, header_file, datetime.date.today().isoformat(), os.path.basename(__file__), module_name, num_inputs-1)
print(header,file=file)
for input_name in conditions[:len(conditions)-1]:
print(" input %s,"%(input_name), file=file)
......@@ -564,13 +569,14 @@ module %s (
print("endmodule",file=file)
def action_decoder_verilog(actions, action_vals, module_name, file=None):
header_template="""/*******************************************************************************
* Module: %s
* Date:%s
* Author: auto-generated file, see %s
* Description: Decode sequencer code to 1-hot actions
*******************************************************************************/
def action_decoder_verilog(actions, action_vals, module_name, header_file="", file=None):
header_template="""/*!
* <b>Module:</b>%s
* @file %s
* @date %s
* @author auto-generated file, see %s
* @brief Decode sequencer code to 1-hot actions
*/
`timescale 1ns/1ps
......@@ -578,6 +584,10 @@ module %s (
input clk,
input enable,
input [%2d:0] data,"""
if header_file:
header_file = os.path.basename(header_file)
else:
header_file=""
v=max(action_vals.values())
num_inputs = 0;
while v:
......@@ -591,7 +601,7 @@ module %s (
names.append(a)
maximal_length = max([len(n) for n in names])
header = header_template%(module_name, datetime.date.today().isoformat(), os.path.basename(__file__), module_name, num_inputs-1)
header = header_template%(module_name, header_file, datetime.date.today().isoformat(), os.path.basename(__file__), module_name, num_inputs-1)
print(header,file=file)
for output_name in names[:len(names)-1]:
print(" output reg %s,"%(output_name),file=file)
......@@ -862,14 +872,14 @@ if not action_decoder_verilog_path:
action_decoder_verilog(actions, action_vals, action_decoder_module_name)
else:
with open(os.path.abspath(os.path.join(os.path.dirname(__file__), action_decoder_verilog_path)),"w") as out_file:
action_decoder_verilog(actions, action_vals, action_decoder_module_name, out_file)
action_decoder_verilog(actions, action_vals, action_decoder_module_name, action_decoder_verilog_path, out_file)
print ("AHCI FSM actions decoder is written to %s"%(os.path.abspath(os.path.join(os.path.dirname(__file__), action_decoder_verilog_path))))
if not condition_mux_verilog_path:
condition_mux_verilog(conditions, condition_vals, condition_mux_module_name, condition_mux_fanout)
else:
with open(os.path.abspath(os.path.join(os.path.dirname(__file__), condition_mux_verilog_path)),"w") as out_file:
condition_mux_verilog(conditions, condition_vals,condition_mux_module_name, condition_mux_fanout, out_file)
condition_mux_verilog(conditions, condition_vals,condition_mux_module_name, condition_mux_fanout, condition_mux_verilog_path, out_file)
print ("AHCI FSM conditions multiplexer is written to %s"%(os.path.abspath(os.path.join(os.path.dirname(__file__), condition_mux_verilog_path))))
code = code_generator (sequence, action_vals, condition_vals, labels)
......
py393sata/create_ahci_registers.py
View file @ d7d90f4c
......@@ -28,7 +28,10 @@ __status__ = "Development"
# All unspecified ranges/fields default to fT:RO, fC:0 (readonly, reset value = 0)
#RID = 0x02 # Revision ID (use for bitstream version)
RID = 0x0a # Revision ID
"""
**** Modify next value for new file versions, re-run this file *****
"""
RID = 0x0b # Revision ID
VID = 0xfffe # What to use for non-PCI "vendorID"?
DID = 0x0001
SSVID = 0xfffe
......
system_defines.vh
View file @ d7d90f4c
/*!
* @file system_defines.vh
* @date 2015-02-28
* @author Andrey Filippov
*
* @brief Preprocessor macros definitions to be included in AHCI SATA project
* files when built as a stanalone project (https://github.com/Elphel/x393_sata).
* Not used when AHCI SATA is a part of the x393 project.
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* system_defines.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* system_defines.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
......
wrapper/GTXE2_GPL.v
View file @ d7d90f4c
/*******************************************************************************
* Module: GTXE2_GPL
* Date: 2015-09-08
* Author: Alexey
* Description: emulates GTXE2_CHANNEL primitive behaviour.
/*!
* <b>Module:</b>GTXE2_GPL
* @file GTXE2_GPL.v
* @date 2015-09-08
* @author Alexey
*
* @brief emulates GTXE2_CHANNEL primitive behaviour.
* The file is gathered from multiple files
*
* Copyright (c) 2015 Elphel, Inc.
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* GTXE2_GPL.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -31,7 +36,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
/**
* Original unisims primitive's interfaces, according to xilinx's user guide:
* "7 Series FPGAs GTX/GTH Transceivers User Guide UG476(v1.11)", which is further
......
wrapper/clock_inverter.v
View file @ d7d90f4c
/*******************************************************************************
* Module: clock_inverter
* Date:2016-02-11
* Author: andrey
* Description: Glitch-free clock controlled inverter
/*!
* <b>Module:</b>clock_inverter
* @file clock_inverter.v
* @date 2016-02-11
* @author Andrey Filippov
*
* @brief Glitch-free clock controlled inverter
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* Copyright (c) 2016 Elphel, Inc .
* clock_inverter.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -17,7 +22,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
*/
`timescale 1ns/1ps
module clock_inverter(
......
wrapper/gtxe2_channel_wrapper.v
View file @ d7d90f4c
/*******************************************************************************
* Module: gtxe2_channel_wrapper
* Date: 2015-09-07
* Author: Alexey
* Description: wrapper to switch between closed unisims primitive and open-source one
/*!
* <b>Module:</b>gtxe2_channel_wrapper
* @file gtxe2_channel_wrapper.v
* @date 2015-09-07
* @author Alexey
*
* @brief wrapper to switch between closed unisims primitive and open-source one
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* Copyright (c) 2015 Elphel, Inc.
* GTXE2_GPL.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -30,7 +35,7 @@
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
*/
`include "system_defines.vh"
module gtxe2_channel_wrapper(
// clocking ports, UG476 p.37
......
x393_sata.bit
View file @ d7d90f4c
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