Commit b73a8e11 authored by Alexey Grebenkin's avatar Alexey Grebenkin
Browse files

Axi registers test synthesis

parent 4b361952

synt/axi_regs.xdc

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create_clock -period 20.000 -name axi_aclk -waveform {0.000 10.000} [get_nets axi_aclk]

top.v

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@@ -30,7 +30,6 @@ module top #( 
)

)

(

(

);

);



wire    [3:0]   fclk;

wire    [3:0]   fclk;

wire    [3:0]   frst;

wire    [3:0]   frst;

wire            axi_aclk;

wire            axi_aclk;
@@ -440,7 +439,7 @@ PS7 ps7_i ( 
// AXI PS Master GP1    

// AXI PS Master GP1    

// AXI PS Master GP1: Clock, Reset

// AXI PS Master GP1: Clock, Reset

    .MAXIGP1ACLK    (axi_aclk),         // AXI PS Master GP1 Clock , input

    .MAXIGP1ACLK    (axi_aclk),         // AXI PS Master GP1 Clock , input

    .MAXIGP1ARESETN (axi_rst),          // AXI PS Master GP1 Reset, output

    .MAXIGP1ARESETN (),          // AXI PS Master GP1 Reset, output

// AXI PS Master GP1: Read Address    

// AXI PS Master GP1: Read Address    

    .MAXIGP1ARADDR  (ARADDR),           // AXI PS Master GP1 ARADDR[31:0], output  

    .MAXIGP1ARADDR  (ARADDR),           // AXI PS Master GP1 ARADDR[31:0], output  

    .MAXIGP1ARVALID (ARVALID),          // AXI PS Master GP1 ARVALID, output

    .MAXIGP1ARVALID (ARVALID),          // AXI PS Master GP1 ARVALID, output