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Commit b492662c authored by Andrey Filippov's avatar Andrey Filippov
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fixed problems noticed by implementation messages

parent ba05fb7c
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.project
View file @ b492662c
......@@ -52,87 +52,87 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20151227131114232.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160121151720872.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20151227131114232.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160121151720872.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20151227131114232.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160121151720872.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20151227131114232.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160121151720872.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20151227131114232.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160121151720872.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20151227131114232.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160121151720872.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20151227130259322.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160121151452341.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20151227131114232.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160121151720872.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20151227130259322.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160121151452341.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20151227131114232.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160121151720872.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20151227130259322.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160121151452341.log</location>
</link>
<link>
<name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20151227131114232.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160121151720872.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20151227131114232.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160121151720872.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20151227131114232.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160121151720872.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-place.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20151227131114232.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160121151720872.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-route.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20151227131114232.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160121151720872.dcp</location>
</link>
<link>
<name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20151227130259322.dcp</location>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160121151452341.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ b492662c
......@@ -3,7 +3,7 @@ VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_124_ConstraintsFiles=top.xdc<-@\#\#@->top_timing.xdc<-@\#\#@->
VivadoSynthesis_124_ConstraintsFiles=top.xdc<-@\#\#@->ahci_timing.xdc<-@\#\#@->
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
......
ahci/ahci_dma.v
View file @ b492662c
......@@ -60,7 +60,7 @@ module ahci_dma (
output reg ct_busy, // cleared after 0x20 DWORDs are read out
// reading out command table data
input [ 4:0] ct_addr, // DWORD address
input ct_re, //
input [ 1:0] ct_re, // [0] - re, [1]-regen
output reg [31:0] ct_data, //
// After the first 0x80 bytes of the Command Table are read out, this module will read/process PRDs,
......@@ -232,6 +232,8 @@ module ahci_dma (
wire fifo_nempty_mclk;
reg en_extra_din_r;
reg [31:0] ct_data_reg;
// assign prd_done = done_dev_wr || done_dev_rd;
assign cmd_done_hclk = ((ct_busy_r==2'b10) && (prdtl_mclk == 0)) || done_flush || done_dev_rd;
......@@ -274,8 +276,11 @@ module ahci_dma (
assign afi_arqos = 4'h0;
assign afi_rdissuecap1en = 1'b0;
assign extra_din = en_extra_din_r && fifo_nempty_mclk;
// reg [31:0] ct_data_reg;
always @ (posedge mclk) begin
if (ct_re) ct_data <= ct_data_ram[ct_addr];
if (ct_re[0]) ct_data_reg <= ct_data_ram[ct_addr];
if (ct_re[1]) ct_data <= ct_data_reg;
if (ctba_ld) ctba_r <= ctba[31:7];
if (cmd_start) prdtl_mclk <= prdtl;
if (cmd_start) dev_wr_mclk <= dev_wr;
......
ahci/ahci_fis_receive.v
View file @ b492662c
......@@ -160,8 +160,8 @@ localparam DATA_TYPE_ERR = 3;
reg [ADDRESS_BITS-1:0] reg_addr_r;
reg [3:0] fis_dcount; // number of DWORDS left to be written to the "memory"
reg fis_save; // save FIS data
wire fis_end = (hba_data_in_type == DATA_TYPE_OK) || (hba_data_in_type == DATA_TYPE_ERR);
wire fis_end_w = data_in_ready && fis_end & ~(|fis_end_r);
wire is_fis_end = (hba_data_in_type == DATA_TYPE_OK) || (hba_data_in_type == DATA_TYPE_ERR);
wire fis_end_w = data_in_ready && is_fis_end & ~(|fis_end_r);
reg [1:0] fis_end_r;
reg fis_rec_run; // running received FIS
......@@ -170,7 +170,8 @@ localparam DATA_TYPE_ERR = 3;
wire is_FIS_HEAD = data_in_ready && (hba_data_in_type == DATA_TYPE_FIS_HEAD);
wire is_FIS_NOT_HEAD = data_in_ready && (hba_data_in_type != DATA_TYPE_FIS_HEAD);
wire data_in_ready = hba_data_in_valid && (hba_data_in_many || !(|was_data_in || hba_data_in_ready) );
// wire data_in_ready = hba_data_in_valid && (hba_data_in_many || (!(|was_data_in) && hba_data_in_ready));
wire data_in_ready = hba_data_in_valid && (hba_data_in_many || !(|was_data_in));
wire get_fis = get_dsfis || get_psfis || get_rfis || get_sdbfis || get_ufis || get_data_fis || get_ignore;
reg wreg_we_r;
......@@ -288,15 +289,15 @@ localparam DATA_TYPE_ERR = 3;
end
if (hba_rst) fis_rec_run <= 0;
else if (get_fis) fis_rec_run <= 1;
else if (fis_end && data_in_ready) fis_rec_run <= 0;
if (hba_rst) fis_rec_run <= 0;
else if (get_fis) fis_rec_run <= 1;
else if (is_fis_end && data_in_ready) fis_rec_run <= 0;
if (hba_rst) dwords_over <= 0;
else if (wreg_we_r && !(|fis_dcount)) dwords_over <= 1;
if (hba_rst) wreg_we_r <= 0;
else wreg_we_r <= fis_rec_run && data_in_ready && !fis_end && !dwords_over && (|fis_dcount || !wreg_we_r);
else wreg_we_r <= fis_rec_run && data_in_ready && !is_fis_end && !dwords_over && (|fis_dcount || !wreg_we_r);
fis_end_r <= {fis_end_r[0], fis_end_w};
......
ahci/ahci_fsm.v
View file @ b492662c
......@@ -261,7 +261,7 @@ module ahci_fsm
reg fsm_preload; // read first sequence data (2 cycles for regen)
// wire [7:0] precond_w = pgm_data[17:10]; // select what to use - cond_met_w valis after precond_w, same time as conditions
// reg [7:0] conditions;
wire pre_jump_w = (|async_pend_r) ? async_ackn : (cond_met_w & fsm_transitions[1]);
wire pre_jump_w = (|async_pend_r) ? async_ackn : |(cond_met_w & fsm_transitions[1]);
wire fsm_act_done = get_fis_done || xmit_done || (syncesc_send_pend && syncesc_send_done);
wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done
wire fsm_last_act_w = pgm_data[17];
......
ahci/ahci_sata_layers.v
View file @ b492662c
......@@ -198,7 +198,7 @@ module ahci_sata_layers #(
link #(
.DATA_BYTE_WIDTH(4)
) link_i (
) link (
.rst (rst), // input wire
.clk (clk), // input wire
// data inputs from transport layer
......@@ -268,7 +268,7 @@ module ahci_sata_layers #(
sata_phy #(
.DATA_BYTE_WIDTH(4)
) sata_phy_i (
) phy (
.extrst (exrst), // input wire
.clk (clk), // output wire
.rst (rst), // output wire
......
ahci/ahci_top.v
View file @ b492662c
......@@ -759,7 +759,7 @@ module ahci_top#(
.set_axi_rd_cache_mode (set_axi_cache_mode), // input
.ct_busy (dma_ct_busy), // output reg
.ct_addr (dma_ct_addr), // input[4:0]
.ct_re (dma_ct_re[0]), // input
.ct_re (dma_ct_re), // input[1:0]
.ct_data (dma_ct_data), // output[31:0] reg
.prd_done (), /// dma_prd_done), // output
......
ahci/sata_ahci_top.v
View file @ b492662c
......@@ -156,7 +156,13 @@
// wire sata_clk;
// wire sata_rst;
wire exrst;
wire hba_arst;
wire port_arst;
wire exrst = port_arst; // now both hba_arst and port_arst are the same?
// Data/type FIFO, host -> device
// Data System memory or FIS -> device
......@@ -207,6 +213,14 @@
// additional control signals for SATA layers
wire [3:0] sctl_ipm; // Interface power management transitions allowed
wire [3:0] sctl_spd; // Interface maximal speed
reg [2:0] hrst_r;
wire hrst = hrst_r[2];
always @ (posedge hclk or posedge arst) begin
if (arst) hrst_r <= 0;
else hrst_r <= (hrst_r << 1) | 1;
end
ahci_top #(
......@@ -219,10 +233,10 @@
.arst (arst), // input
.mclk (sata_clk), // input
.mrst (sata_rst), // input
.hba_arst (exrst), // output
.port_arst (), // output
.hba_arst (hba_arst), // output
.port_arst (port_arst), // output
.hclk (hclk), // input
.hrst (), // input
.hrst (hrst), // input
.awaddr (AWADDR), // input[31:0]
.awvalid (AWVALID), // input
......@@ -298,15 +312,18 @@
.afi_rcount (afi_rcount), // input[7:0]
.afi_racount (afi_racount), // input[2:0]
.afi_rdissuecap1en (afi_rdissuecap1en), // output
.h2d_data (h2d_data), // output[31:0]
.h2d_type (h2d_type), // output[1:0]
.h2d_valid (h2d_valid), // output
.h2d_ready (h2d_ready), // input
.d2h_data (d2h_data), // input[31:0]
.d2h_type (d2h_type), // input[1:0]
.d2h_valid (d2h_valid), // input
.d2h_many (d2h_many), // input
.d2h_ready (d2h_ready), // output
.phy_ready (phy_speed), // input[1:0]
.xmit_ok (xmit_ok), // input
.xmit_err (xmit_err), // input
......@@ -345,17 +362,20 @@
.reliable_clk (reliable_clk), // input
.rst (sata_rst), // output
.clk (sata_clk), // output
.h2d_data (h2d_data), // input[31:0]
.h2d_mask (2'h3), //h2d_mask), // input[1:0]
.h2d_type (h2d_type), // input[1:0]
.h2d_valid (h2d_valid), // input
.h2d_ready (h2d_ready), // output
.d2h_data (d2h_data), // output[31:0]
.d2h_mask (), // 2h_mask), // output[1:0]
.d2h_type (d2h_type), // output[1:0]
.d2h_valid (d2h_valid), // output
.d2h_many (d2h_many), // output
.d2h_ready (d2h_ready), // input
.phy_speed (phy_speed), // output[1:0]
.gtx_ready(), // output
.xmit_ok (xmit_ok), // output
......
host/gtx_wrap.v
View file @ b492662c
......@@ -144,8 +144,8 @@ if (DATA_BYTE_WIDTH == 4) begin
// 2*Fin = Fout => WIDTHin = 2*WIDTHout
// Andrey:
reg txdata_resync_strobe;
reg [15:0] txdata_enc_in_r;
reg [ 1:0] txcharisk_enc_in_r;
reg [15:0] txdata_enc_in_r; // TODO: remove async reset
reg [ 1:0] txcharisk_enc_in_r; // TODO: remove async reset
wire [38:0] txdata_resync_out;
wire txdata_resync_valid;
reg [1:0] txcomwake_gtx_f; // 2 registers just to match latency (data to the 3 next) in Alexey's code, probbaly not needed
......@@ -170,7 +170,7 @@ if (DATA_BYTE_WIDTH == 4) begin
always @ (posedge txreset or posedge txusrclk) begin
if (txreset) txdata_resync_strobe <= 0;
else if (txdata_resync_valid) txdata_resync_strobe <= ~txdata_resync_strobe;
/*
if (txreset) begin
txdata_enc_in_r <= 0;
txcharisk_enc_in_r <= 0;
......@@ -178,7 +178,7 @@ if (DATA_BYTE_WIDTH == 4) begin
txdata_enc_in_r <= txdata_resync_strobe? txdata_resync_out[31:16]: txdata_resync_out[15:0];
txcharisk_enc_in_r <= txdata_resync_strobe? txdata_resync_out[35:34]: txdata_resync_out[33:32];
end
*/
if (txreset) begin
txcomwake_gtx_f <= 0;
txcominit_gtx_f <= 0;
......@@ -189,6 +189,19 @@ if (DATA_BYTE_WIDTH == 4) begin
txelecidle_gtx_f <= {txdata_resync_out[38],txelecidle_gtx_f[1]};
end
end
// Changing to sync reset (otherwise WARNING: [DRC 23-20] Rule violation (REQP-1839) RAMB36 async control check ...)
always @ (posedge txusrclk) begin
if (txreset) begin
txdata_enc_in_r <= 0;
txcharisk_enc_in_r <= 0;
end else if (txdata_resync_valid) begin
txdata_enc_in_r <= txdata_resync_strobe? txdata_resync_out[31:16]: txdata_resync_out[15:0];
txcharisk_enc_in_r <= txdata_resync_strobe? txdata_resync_out[35:34]: txdata_resync_out[33:32];
end
end
assign txdata_enc_in = txdata_enc_in_r;
assign txcharisk_enc_in = txcharisk_enc_in_r;
assign txcominit_gtx = txcominit_gtx_f[0];
......@@ -437,7 +450,8 @@ if (DATA_BYTE_WIDTH == 4) begin
.DATA_DEPTH (4)
)
rxdata_resynchro(
.rst (~wrap_rxreset_),
// .rst (~wrap_rxreset_),
.rst (1'b0),
.rrst (~wrap_rxreset_),
.wrst (~wrap_rxreset_),
.rclk (rxusrclk2),
......
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