debugging with the driver (9c36c48f) · Commits · Elphel / x393_sata

.project

+17 −17

Original line number	Diff line number	Diff line
		@@ -52,87 +52,87 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160217173341424.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160222133823984.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160217173341424.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160222133823984.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160217173341424.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160222133823984.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160217173341424.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160222133823984.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160217173341424.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160222133823984.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160217173341424.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160222133823984.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160217173227982.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160222133537458.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160217173341424.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160222133823984.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160217173227982.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160222133537458.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160217173341424.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160222133823984.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160217173227982.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160222133537458.log</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt-phys.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160217173341424.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160222133823984.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt-power.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160217173341424.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160222133823984.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160217173341424.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160222133823984.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-place.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160217173341424.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160222133823984.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-route.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160217173341424.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160222133823984.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-synth.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160217173227982.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160222133537458.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

ahci/ahci_ctrl_stat.v

+61 −28

Original line number	Diff line number	Diff line
		@@ -53,6 +53,7 @@ module ahci_ctrl_stat #(
		input update_serr,
		input update_pcmd,
		input update_pci,
		input update_ghc,

		/// output reg st01_pending, // software turned PxCMD.ST from 0 to 1
		/// output reg st10_pending, // software turned PxCMD.ST from 1 to 0
		@@ -136,6 +137,8 @@ module ahci_ctrl_stat #(
		input pxci0_clear, // PxCI clear
		output pxci0, // pxCI current value

		input hba_reset_done, // at the end of the HBA reset, clear GHC.HR, GHC.IE

		/*
		*/
		output reg irq
		@@ -143,7 +146,7 @@ module ahci_ctrl_stat #(
		);
		`include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams

		wire swr_GHC__IE = soft_write_en && (soft_write_addr == GHC__GHC__IE__ADDR);
		// wire swr_GHC__IE = soft_write_en && (soft_write_addr == GHC__GHC__IE__ADDR);
		wire swr_GHC__IS = soft_write_en && (soft_write_addr == GHC__IS__IPS__ADDR);
		wire swr_HBA_PORT__PxCMD = soft_write_en && (soft_write_addr == HBA_PORT__PxCMD__ST__ADDR);
		wire swr_HBA_PORT__PxIS = soft_write_en && (soft_write_addr == HBA_PORT__PxIS__CPDS__ADDR);
		@@ -152,21 +155,25 @@ module ahci_ctrl_stat #(
		// wire swr_HBA_PORT__PxSSTS = soft_write_en && (soft_write_addr == HBA_PORT__PxSSTS__SPD__ADDR);
		wire swr_HBA_PORT__PxSERR = soft_write_en && (soft_write_addr == HBA_PORT__PxSERR__DIAG__X__ADDR);
		wire swr_HBA_PORT__PxCI = soft_write_en && (soft_write_addr == HBA_PORT__PxCI__CI__ADDR);
		wire swr_GHC__GHC = soft_write_en && (soft_write_addr == GHC__GHC__HR__ADDR);

		reg hba_rst_r = 1;
		reg rst_por;
		reg rst_hba; // @SuppressThisWarning VEditor : Unused, maybe will be used later
		reg rst_port; // @SuppressThisWarning VEditor : Unused, maybe will be used later

		reg ghc_ie_r;
		// reg ghc_ie_r;
		reg ghc_is_r;
		reg set_ghc_is_r; // active next cycle after one of individual non-masked bits in PxIS is set
		reg cleared_ghc; // active next cycle after ghc[1:0] is cleared
		reg [31:0] PxIE_r; // some bits will be unused by PxIS_MASK
		reg [31:0] PxIS_r; // some bits will be unused by PxIS_MASK
		reg [11:0] PxSSTS_r;
		reg [31:0] PxSERR_r; // Assuming it is not needed for HBA, just for the software
		reg [31:0] PxCMD_r;
		reg pxci0_r;
		reg [ 1:0] GHC_r; // only 2 bits are used here
		wire ghc_ie = GHC_r[1]; // bit 1 of GHC__GHC

		reg cirq_PRC; // clear PRC bit when clearing PxSERR.DIAG.N
		reg cirq_PC; // clear PC bit when clearing PxSERR.DIAG.X
		@@ -217,7 +224,7 @@ module ahci_ctrl_stat #(
		({4{ssts_det_dp}} & 4'h3) \|
		({4{ssts_det_offline}} & 4'h4);

		// to update only HAB/async changed bits (not by the software)
		// to update only HBA/async changed bits (not by the software)

		wire set_ssts_ipm = ssts_ipm_dnp \|\| ssts_ipm_active \|\| ssts_ipm_part \|\| ssts_ipm_slumb \|\| ssts_ipm_devsleep;
		wire set_ssts_spd = ssts_spd_dnp \|\| ssts_spd_gen1 \|\| ssts_spd_gen2\|\| ssts_spd_gen3;
		@@ -230,19 +237,23 @@ module ahci_ctrl_stat #(
		reg sirq_changed;
		reg pxcmd_changed;
		reg ghc_is_changed;
		reg ghc_ghc_changed;

		// wire [5:0] regs_changed={pxcmd_changed, serr_changed, ssts_changed, pxci_changed, sirq_changed,ghc_is_changed };
		wire [5:0] regs_changed={pxci_changed, pxcmd_changed, serr_changed, ssts_changed, sirq_changed,ghc_is_changed };
		wire [6:0] regs_changed={ghc_ghc_changed, pxci_changed, pxcmd_changed, serr_changed, ssts_changed, sirq_changed,ghc_is_changed };

		// wire [5:0] update;
		reg [5:1] updating;
		wire [5:0] update_first = {6{update_all}} &
		{regs_changed[5] && ~(\|regs_changed[4:0]),
		reg [6:1] updating;
		wire [6:0] update_first = {7{update_all}} &
		{regs_changed[6] && ~(\|regs_changed[5:0]),
		regs_changed[5] && ~(\|regs_changed[4:0]),
		regs_changed[4] && ~(\|regs_changed[3:0]),
		regs_changed[3] && ~(\|regs_changed[2:0]),
		regs_changed[2] && ~(\|regs_changed[1:0]),
		regs_changed[1] && ~ regs_changed[0],
		regs_changed[0]};
		wire [5:1] update_next = {updating[5] && ~(\|updating[4:1]),
		wire [6:1] update_next = {updating[6] && ~(\|updating[5:1]),
		updating[5] && ~(\|updating[4:1]),
		updating[4] && ~(\|updating[3:1]),
		updating[3] && ~(\|updating[2:1]),
		updating[2] && ~ updating[1],
		@@ -255,10 +266,11 @@ module ahci_ctrl_stat #(
		wire update_HBA_PORT__PxSERR = update_serr \|\| update_first[3] \|\| update_next[3];
		wire update_HBA_PORT__PxCMD = update_pcmd \|\| update_first[4] \|\| update_next[4];
		wire update_HBA_PORT__PxCI = update_pci \|\| update_first[5] \|\| update_next[5];
		wire update_GHC_GHC = update_ghc \|\| update_first[6] \|\| update_next[6];

		reg pfsm_started_r;

		assign update_busy = (update_all && (\|regs_changed)) \|\| (\|updating[5:1]);
		assign update_busy = (update_all && (\|regs_changed)) \|\| (\|updating[6:1]);
		assign update_pending = \| regs_changed;
		assign pcmd_fre = \|(HBA_PORT__PxCMD__FRE__MASK & PxCMD_r);
		assign serr_diag_X = \|(HBA_PORT__PxSERR__DIAG__X__MASK & PxSERR_r);
		@@ -372,7 +384,9 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK \| // 'hf0000000;

		always @(posedge mclk) begin
		if (mrst) irq <= 0;
		else irq <= ghc_ie_r && ghc_is_r;
		// else irq <= ghc_ie_r && ghc_is_r;
		else irq <= ghc_ie && ghc_is_r;

		end

		// generate reset types
		@@ -385,15 +399,14 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK \| // 'hf0000000;
		end

		// GHC_IE register (just one bit)
		always @(posedge mclk) begin
		if (rst_por) ghc_ie_r <= 0;
		else if (swr_GHC__IE) ghc_ie_r <= \|(soft_write_data & GHC__GHC__IE__MASK);

		end
		// always @(posedge mclk) begin
		// if (rst_por) ghc_ie_r <= 0;
		// else if (swr_GHC__IE) ghc_ie_r <= \|(soft_write_data & GHC__GHC__IE__MASK);
		// end

		// swr_GHC__IS register (just one bit)
		always @(posedge mclk) begin
		if (mrst) ghc_is_r <= 0; // any reset?
		if (mrst \|\| hba_reset_done) ghc_is_r <= 0; // any reset?
		else if (set_ghc_is_r) ghc_is_r <= 1;
		else if (swr_GHC__IS) ghc_is_r <= soft_write_data[0];
		end
		@@ -413,7 +426,17 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK \| // 'hf0000000;
		always @(posedge mclk) begin
		if (rst_por) set_ghc_is_r <= 0;
		// TODO: Not exactly clear - when ghc_is_r should be set after being RWC? After setting some not masked new individual interrupt?
		else set_ghc_is_r <= \|(sirq & PxIE_r);
		else set_ghc_is_r <= \|(sirq & PxIE_r) \|\| hba_reset_done;
		end

		// GHC__GHC register
		always @(posedge mclk) begin
		if (rst_por) cleared_ghc <= 0;
		else cleared_ghc <= hba_reset_done;

		if (rst_por) GHC_r <= 0;
		else if (cleared_ghc) GHC_r <= 0;
		else if (swr_GHC__GHC) GHC_r <= soft_write_data[1:0];
		end

		// HBA_PORT__PxSSTS register - updated from the HOST only
		@@ -449,7 +472,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK \| // 'hf0000000;
		else if (swr_HBA_PORT__PxCI) pxci0_r <= soft_write_data[0];
		end

		// HBA_PORT__PxCMD register - different behavious of differtnt fields
		// HBA_PORT__PxCMD register - different behaviors of differtnt fields
		// use PxCMD_MASK to prevent generation of unneeded register bits

		always @(posedge mclk) begin
		@@ -469,9 +492,10 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK \| // 'hf0000000;
		if (!pfsm_started_r) pcmd_st_cleared <= 0;
		// else if (swr_HBA_PORT__PxCMD) pcmd_st_cleared <= \|(HBA_PORT__PxCMD__ST__MASK & PxCMD_r & ~soft_write_data);
		else pcmd_st_cleared <= swr_HBA_PORT__PxCMD && (\|(HBA_PORT__PxCMD__ST__MASK & PxCMD_r & ~soft_write_data));

		end



		// Update AXI registers with the current local data
		always @ (posedge mclk) begin
		regs_addr <= ({ADDRESS_BITS{update_GHC__IS}} & GHC__IS__IPS__ADDR) \|
		@@ -479,16 +503,18 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK \| // 'hf0000000;
		({ADDRESS_BITS{update_HBA_PORT__PxSSTS}} & HBA_PORT__PxSSTS__SPD__ADDR) \|
		({ADDRESS_BITS{update_HBA_PORT__PxSERR}} & HBA_PORT__PxSERR__DIAG__X__ADDR) \|
		({ADDRESS_BITS{update_HBA_PORT__PxCMD}} & HBA_PORT__PxCMD__ICC__ADDR) \|
		({ADDRESS_BITS{update_HBA_PORT__PxCI}} & HBA_PORT__PxCI__CI__ADDR) ;
		({ADDRESS_BITS{update_HBA_PORT__PxCI}} & HBA_PORT__PxCI__CI__ADDR) \|
		({ADDRESS_BITS{update_GHC_GHC}} & GHC__GHC__AE__ADDR);
		//update_HBA_PORT__PxCI
		regs_din <= ({32{update_GHC__IS}} & {31'b0, ghc_is_r}) \|
		({32{update_HBA_PORT__PxIS}} & PxIS_r) \|
		({32{update_HBA_PORT__PxSSTS}} & {20'b0, PxSSTS_r[11:0]}) \|
		({32{update_HBA_PORT__PxSERR}} & PxSERR_r) \|
		({32{update_HBA_PORT__PxCMD}} & PxCMD_r) \|
		({32{update_HBA_PORT__PxCI}} & {31'b0, pxci0});
		({32{update_HBA_PORT__PxCI}} & {31'b0, pxci0}) \|
		({32{update_GHC_GHC}} & (GHC__GHC__AE__DFLT \| {30'b0, GHC_r})) ;

		regs_we <= update_GHC__IS \|\| update_HBA_PORT__PxIS \|\| update_HBA_PORT__PxSSTS \|\| update_HBA_PORT__PxSERR \| update_HBA_PORT__PxCMD \|\| update_HBA_PORT__PxCI;
		regs_we <= update_GHC__IS \|\| update_HBA_PORT__PxIS \|\| update_HBA_PORT__PxSSTS \|\| update_HBA_PORT__PxSERR \| update_HBA_PORT__PxCMD \|\| update_HBA_PORT__PxCI \|\| update_GHC_GHC;

		// pending updates
		if (mrst) pxci_changed <= 1; //0;
		@@ -515,10 +541,17 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK \| // 'hf0000000;
		else if (set_ghc_is_r) ghc_is_changed <= 1;
		else if (update_GHC__IS) ghc_is_changed <= 0;

		if (mrst) ghc_ghc_changed <= 1; //0;
		else if (set_ghc_is_r) ghc_ghc_changed <= 1;
		else if (update_GHC_GHC) ghc_ghc_changed <= 0;




		// updating registers if needed, 0 to 6 cycles, in priority sequence
		if (mrst) updating[5:1] <= 0;
		else if (update_all) updating[5:1] <= regs_changed[5:1] & ~update_first[5:1];
		else updating[5:1] <= updating[5:1] & ~ update_next[5:1];
		if (mrst) updating[6:1] <= 0;
		else if (update_all) updating[6:1] <= regs_changed[6:1] & ~update_first[6:1];
		else updating[6:1] <= updating[6:1] & ~ update_next[6:1];

		// detect software setting for PxCMD.ST 0->1 and 1->0
		/*

ahci/ahci_fsm.v

+3 −0

Original line number	Diff line number	Diff line
		@@ -134,6 +134,8 @@ module ahci_fsm
		input sctl_det_changed, // Software had written new value to sctl_det
		output sctl_det_reset, // clear sctl_det_changed

		output hba_rst_done, // reset GHC.HR and other bits

		output pxci0_clear, // PxCI clear
		input pxci0, // pxCI current value

		@@ -433,6 +435,7 @@ module ahci_fsm
		.PXSSTS_DET_1 (ssts_det_dnp), // output reg
		.SSTS_DET_OFFLINE (ssts_det_offline), // output reg
		.SCTL_DET_CLEAR (sctl_det_reset), // output reg
		.HBA_RST_DONE (hba_rst_done), // output reg
		// FIS RECEIVE
		.SET_UPDATE_SIG (set_update_sig), // output reg
		.UPDATE_SIG (update_sig), // output reg

ahci/ahci_top.v

+51 −17

File changed.

Preview size limit exceeded, changes collapsed.

ahci/sata_ahci_top.v

+3 −2

Original line number	Diff line number	Diff line
		@@ -177,7 +177,8 @@
		wire hba_arst; // @S uppressThisWarning VEditor unused
		wire port_arst; // @SuppressThisWarning VEditor unused
		wire port_arst_any;
		wire exrst = port_arst_any; // now both hba_arst and port_arst are the same?
		// wire exrst = port_arst_any; // now both hba_arst and port_arst are the same?
		wire exrst = port_arst_any \|\| hba_arst; // now both hba_arst and port_arst are the same (only difference in fsm)

Admin message