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Commit 9c36c48f authored by Andrey Filippov's avatar Andrey Filippov
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debugging with the driver

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.project
View file @ 9c36c48f
......@@ -52,87 +52,87 @@
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160217173341424.log</location>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160217173341424.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160222133823984.log</location>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160217173341424.log</location>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160222133823984.log</location>
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ahci/ahci_ctrl_stat.v
View file @ 9c36c48f
This diff is collapsed.
ahci/ahci_fsm.v
View file @ 9c36c48f
......@@ -134,6 +134,8 @@ module ahci_fsm
input sctl_det_changed, // Software had written new value to sctl_det
output sctl_det_reset, // clear sctl_det_changed
output hba_rst_done, // reset GHC.HR and other bits
output pxci0_clear, // PxCI clear
input pxci0, // pxCI current value
......@@ -433,6 +435,7 @@ module ahci_fsm
.PXSSTS_DET_1 (ssts_det_dnp), // output reg
.SSTS_DET_OFFLINE (ssts_det_offline), // output reg
.SCTL_DET_CLEAR (sctl_det_reset), // output reg
.HBA_RST_DONE (hba_rst_done), // output reg
// FIS RECEIVE
.SET_UPDATE_SIG (set_update_sig), // output reg
.UPDATE_SIG (update_sig), // output reg
......
ahci/ahci_top.v
View file @ 9c36c48f
......@@ -361,7 +361,7 @@ module ahci_top#(
/// wire sactive0; // bit 0 of sActive DWORD received in SDB FIS
// Using even word count (will be rounded up), partial DWORD (last) will be handled by PRD length if needed
wire [31:0] xfer_cntr;
wire [31:2] xfer_cntr;
wire xfer_cntr_zero;
/// wire [11:0] data_in_dwords; // number of DWORDs received in data FIS (can be updated internally). Is it needed?
......@@ -420,7 +420,9 @@ module ahci_top#(
wire pcmd_cr_set; // command list run set
wire pcmd_cr_reset; // command list run reset
// wire pcmd_fr; // ahci_fis_receive:get_fis_busy - use frcv_busy
wire pcmd_fre; // FIS enable copy to memory
wire pcmd_fre0; // FIS enable copy to memory
wire pcmd_fre = pcmd_fre0 || 1; // FIS enable copy to memory
// wire pcmd_clear_bsy_drq; // == ahci_fis_receive:clear_bsy_drq
wire pcmd_clo; // RW1, causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit
// wire pcmd_clear_st; // RW clear ST (start) bit
......@@ -472,6 +474,7 @@ module ahci_top#(
wire pxci0_clear; // PxCI clear
wire pxci0; // pxCI current value
wire hba_rst_done; // HBA reset done - clear GHC.HR (and some other regs)
wire [9:0] last_jump_addr;
wire [31:0] debug_dma;
......@@ -580,6 +583,7 @@ module ahci_top#(
.sctl_det (sctl_det), // input[3:0]
.sctl_det_changed (sctl_det_changed), // input
.sctl_det_reset (sctl_det_reset), // output
.hba_rst_done (hba_rst_done), // output
.pxci0_clear (pxci0_clear), // output
.pxci0 (pxci0), // input
......@@ -629,7 +633,7 @@ module ahci_top#(
.decr_dwcr (frcv_decr_dwcr), // output increment pXferCntr after transmit by data transmitted)
.decr_dwcw (frcv_decr_dwcw), // output increment pXferCntr after transmit by data transmitted)
// .decr_DXC_dw (data_out_dwords), // output[11:2] **** Probably not needed
.pxcmd_fre (pcmd_fre), // input
.pxcmd_fre ( pcmd_fre), // input
.pPioXfer (pPioXfer), // input
.tfd_sts (tfd_sts), // input[7:0]
/// .tfd_err (tfd_err), // input[7:0]
......@@ -731,7 +735,8 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0]
.was_port_rst (was_port_rst), // output
.debug_in0 ({ debug_data_in_ready, // output
debug_fis_end_w, // output
debug_fis_end_r[1:0], // output[1:0]
xfer_cntr_zero,
debug_fis_end_r[0], // debug_fis_end_r[1:0], // output[1:0]
debug_get_fis_busy_r[1:0], // output[1:0]
debug_dma[25:0]}), // input[31:0]
// .debug_in1 ({xclk_period[7:0], // lower 8 bits of 12-bit value. Same frequency would be 0x800 (msb opposite to 3 next bits)
......@@ -795,6 +800,7 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0]
.update_serr (1'b0), // update_HBA_PORT__PxSERR), // input
.update_pcmd (1'b0), // update_HBA_PORT__PxCMD), // input
.update_pci (1'b0), // update_HBA_PORT__PxCI), // input
.update_ghc (1'b0), // update _GHC_GHC, // input
.pcmd_clear_icc (1'b0), // pcmd_clear_icc), // input
.pcmd_esp (pcmd_esp), // input
......@@ -802,7 +808,7 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0]
.pcmd_cr_set (pcmd_cr_set), // input
.pcmd_cr_reset (pcmd_cr_reset), // input
.pcmd_fr (frcv_busy), // input
.pcmd_fre (pcmd_fre), // output
.pcmd_fre (pcmd_fre0), // output
.pcmd_clear_bsy_drq (frcv_clear_bsy_drq), // input
.pcmd_clo (pcmd_clo), // output
.pcmd_clear_st (1'b0), // pcmd_clear_st), // input
......@@ -855,6 +861,7 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0]
.sctl_det_reset (sctl_det_reset), // input
.pxci0_clear (pxci0_clear), // input
.pxci0 (pxci0), // output
.hba_reset_done (hba_rst_done), // input
.irq (irq) // output reg
);
......@@ -1087,7 +1094,7 @@ wire [9:0] xmit_dbg_01;
);
// Datascope code
`define DATASCOPE_V2
//`define DATASCOPE_V2
// Datascope interface (write to memory that can be software-read)
`ifdef USE_DATASCOPE
......@@ -1171,13 +1178,13 @@ debug_dma_h2d
};
*/
`endif // DATASCOPE_V2
`ifdef DATASCOPE_V1
//`endif // DATASCOPE_V2
`else
//`ifdef DATASCOPE_V1
localparam DATASCOPE_CFIS_START=0;
localparam DATASCOPE_INCOMING_POST=32;
reg [ADDRESS_BITS-1:0] datascope_waddr_r;
reg [ADDRESS_BITS-1:0] datascope_waddr_r=0;
reg [1:0] datascope_run;
reg datascope_link_run;
......@@ -1192,8 +1199,25 @@ debug_dma_h2d
reg [2:0] datascope_incoming_run;
reg [7:0] datascope_incoming_cntr;
reg datascope_receive_fis;
reg [9:0] datascope_last_jump_addr=0;
reg [1:0] datascope_new_jump = 0;
reg [15:0] datascope_jump_cntr = 0;
//last_jump_addr[9:0]
always @(posedge mclk) begin
if (mrst) datascope_new_jump[0] <= 0;
else datascope_new_jump[0] <= datascope_last_jump_addr != last_jump_addr;
if (mrst) datascope_new_jump[1] <= 0;
else datascope_new_jump[1] <= datascope_new_jump[0];
if (mrst) datascope_last_jump_addr <= 0;
if (datascope_new_jump) datascope_last_jump_addr <= last_jump_addr;
if (datascope_we) datascope_jump_cntr <= datascope_jump_cntr+1;
if (mrst) datascope_receive_fis <= 0;
else if (datascope_incoming_start) datascope_receive_fis <= 1;
else if (frcv_get_dsfis ||
......@@ -1224,15 +1248,21 @@ debug_dma_h2d
end
assign datascope_clk = mclk;
assign datascope_waddr = datascope_waddr_r;
// assign datascope_waddr = datascope_waddr_r;
assign datascope_waddr = last_jump_addr;
// assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || fsnd_done || d2h_ready || xmit_ok || xmit_err;
// assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || fsnd_done|| xmit_ok || xmit_err; /// || d2h_ready ;
// assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || d2h_ready || datascope_link_run;
assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || datascope_incoming_run[0] || datascope_link_run;
/// assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || datascope_incoming_run[0] || datascope_link_run;
//
assign datascope_we = &datascope_new_jump;
// assign datascope_di = {14'h3fff,fsnd_pCmdToIssue, xfer_cntr_zero, datascope_jump_cntr};
assign datascope_di = {2'h3, fsnd_pCmdToIssue, xfer_cntr_zero, 2'b0, last_jump_addr[9:0],datascope_jump_cntr};
// assign datascope_di = d2h_ready? {d2h_type,
/*
assign datascope_di = datascope_incoming_run[0]? {d2h_type,
debug_in_link[26], // state idle
debug_in_link[4:0], // encoded state (1 cycle later)
......@@ -1259,6 +1289,8 @@ debug_dma_h2d
debug_in_link[24], // fsnd_dx_err[1], //fsnd_dx_err[2:0],
debug_in_link[23],
datascope_id[2:0], {12-ADDRESS_BITS{1'b0}}, datascope_waddr_r});
*/
/*
assign debug_out[ 4: 0] = debug_states_encoded;
assign debug_out[7: 5] = {
......@@ -1340,8 +1372,10 @@ assign debug_out[7: 5] = {
datascope_run[1] <= datascope_run[0];
if (fsnd_cfis_xmit) datascope_waddr_r <= DATASCOPE_CFIS_START;
else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;
/// if (fsnd_cfis_xmit) datascope_waddr_r <= DATASCOPE_CFIS_START;
/// if (mrst) datascope_waddr_r <= DATASCOPE_CFIS_START;
/// else
if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;
if (mrst) datascope_id <= 0;
......
ahci/sata_ahci_top.v
View file @ 9c36c48f
......@@ -174,10 +174,11 @@
// wire sata_clk;
// wire sata_rst;
wire hba_arst; // @SuppressThisWarning VEditor unused
wire hba_arst; // @S uppressThisWarning VEditor unused
wire port_arst; // @SuppressThisWarning VEditor unused
wire port_arst_any;
wire exrst = port_arst_any; // now both hba_arst and port_arst are the same?
// wire exrst = port_arst_any; // now both hba_arst and port_arst are the same?
wire exrst = port_arst_any || hba_arst; // now both hba_arst and port_arst are the same (only difference in fsm)
......
generated/action_decoder.v
View file @ 9c36c48f
/*******************************************************************************
* Module: action_decoder
* Date:2016-02-16
* Date:2016-02-20
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions
*******************************************************************************/
......@@ -28,6 +28,7 @@ module action_decoder (
output reg PXSSTS_DET_1,
output reg SSTS_DET_OFFLINE,
output reg SCTL_DET_CLEAR,
output reg HBA_RST_DONE,
output reg SET_UPDATE_SIG,
output reg UPDATE_SIG,
output reg UPDATE_ERR_STS,
......@@ -80,38 +81,39 @@ module action_decoder (
PXSSTS_DET_1 <= enable && data[ 6] && data[ 1];
SSTS_DET_OFFLINE <= enable && data[ 7] && data[ 1];
SCTL_DET_CLEAR <= enable && data[ 8] && data[ 1];
SET_UPDATE_SIG <= enable && data[ 9] && data[ 1];
UPDATE_SIG <= enable && data[10] && data[ 1];
UPDATE_ERR_STS <= enable && data[ 3] && data[ 2];
UPDATE_PIO <= enable && data[ 4] && data[ 2];
UPDATE_PRDBC <= enable && data[ 5] && data[ 2];
CLEAR_BSY_DRQ <= enable && data[ 6] && data[ 2];
CLEAR_BSY_SET_DRQ <= enable && data[ 7] && data[ 2];
SET_BSY <= enable && data[ 8] && data[ 2];
SET_STS_7F <= enable && data[ 9] && data[ 2];
SET_STS_80 <= enable && data[10] && data[ 2];
XFER_CNTR_CLEAR <= enable && data[ 4] && data[ 3];
DECR_DWCR <= enable && data[ 5] && data[ 3];
DECR_DWCW <= enable && data[ 6] && data[ 3];
FIS_FIRST_FLUSH <= enable && data[ 7] && data[ 3];
CLEAR_CMD_TO_ISSUE <= enable && data[ 8] && data[ 3];
DMA_ABORT <= enable && data[ 9] && data[ 3];
DMA_PRD_IRQ_CLEAR <= enable && data[10] && data[ 3];
XMIT_COMRESET <= enable && data[ 5] && data[ 4];
SEND_SYNC_ESC <= enable && data[ 6] && data[ 4];
SET_OFFLINE <= enable && data[ 7] && data[ 4];
R_OK <= enable && data[ 8] && data[ 4];
R_ERR <= enable && data[ 9] && data[ 4];
FETCH_CMD <= enable && data[10] && data[ 4];
ATAPI_XMIT <= enable && data[ 6] && data[ 5];
CFIS_XMIT <= enable && data[ 7] && data[ 5];
DX_XMIT <= enable && data[ 8] && data[ 5];
GET_DATA_FIS <= enable && data[ 9] && data[ 5];
GET_DSFIS <= enable && data[10] && data[ 5];
GET_IGNORE <= enable && data[ 7] && data[ 6];
GET_PSFIS <= enable && data[ 8] && data[ 6];
GET_RFIS <= enable && data[ 9] && data[ 6];
GET_SDBFIS <= enable && data[10] && data[ 6];
GET_UFIS <= enable && data[ 8] && data[ 7];
HBA_RST_DONE <= enable && data[ 9] && data[ 1];
SET_UPDATE_SIG <= enable && data[10] && data[ 1];
UPDATE_SIG <= enable && data[ 3] && data[ 2];
UPDATE_ERR_STS <= enable && data[ 4] && data[ 2];
UPDATE_PIO <= enable && data[ 5] && data[ 2];
UPDATE_PRDBC <= enable && data[ 6] && data[ 2];
CLEAR_BSY_DRQ <= enable && data[ 7] && data[ 2];
CLEAR_BSY_SET_DRQ <= enable && data[ 8] && data[ 2];
SET_BSY <= enable && data[ 9] && data[ 2];
SET_STS_7F <= enable && data[10] && data[ 2];
SET_STS_80 <= enable && data[ 4] && data[ 3];
XFER_CNTR_CLEAR <= enable && data[ 5] && data[ 3];
DECR_DWCR <= enable && data[ 6] && data[ 3];
DECR_DWCW <= enable && data[ 7] && data[ 3];
FIS_FIRST_FLUSH <= enable && data[ 8] && data[ 3];
CLEAR_CMD_TO_ISSUE <= enable && data[ 9] && data[ 3];
DMA_ABORT <= enable && data[10] && data[ 3];
DMA_PRD_IRQ_CLEAR <= enable && data[ 5] && data[ 4];
XMIT_COMRESET <= enable && data[ 6] && data[ 4];
SEND_SYNC_ESC <= enable && data[ 7] && data[ 4];
SET_OFFLINE <= enable && data[ 8] && data[ 4];
R_OK <= enable && data[ 9] && data[ 4];
R_ERR <= enable && data[10] && data[ 4];
FETCH_CMD <= enable && data[ 6] && data[ 5];
ATAPI_XMIT <= enable && data[ 7] && data[ 5];
CFIS_XMIT <= enable && data[ 8] && data[ 5];
DX_XMIT <= enable && data[ 9] && data[ 5];
GET_DATA_FIS <= enable && data[10] && data[ 5];
GET_DSFIS <= enable && data[ 7] && data[ 6];
GET_IGNORE <= enable && data[ 8] && data[ 6];
GET_PSFIS <= enable && data[ 9] && data[ 6];
GET_RFIS <= enable && data[10] && data[ 6];
GET_SDBFIS <= enable && data[ 8] && data[ 7];
GET_UFIS <= enable && data[ 9] && data[ 7];
end
endmodule
generated/condition_mux.v
View file @ 9c36c48f
/*******************************************************************************
* Module: condition_mux
* Date:2016-02-16
* Date:2016-02-20
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition
*******************************************************************************/
......
helpers/ahci_fsm_sequence.py
View file @ 9c36c48f
......@@ -47,6 +47,7 @@ actions = ['NOP',
# CTRL_STAT
'PXSERR_DIAG_X', 'SIRQ_DHR', 'SIRQ_DP', 'SIRQ_DS', 'SIRQ_IF', 'SIRQ_INF', 'SIRQ_PS', 'SIRQ_SDB', 'SIRQ_TFE', 'SIRQ_UF',
'PFSM_STARTED', 'PCMD_CR_CLEAR', 'PCMD_CR_SET', 'PXCI0_CLEAR', 'PXSSTS_DET_1', 'SSTS_DET_OFFLINE', 'SCTL_DET_CLEAR',
'HBA_RST_DONE',
# FIS RECEIVE
'SET_UPDATE_SIG', 'UPDATE_SIG', 'UPDATE_ERR_STS', 'UPDATE_PIO', 'UPDATE_PRDBC', 'CLEAR_BSY_DRQ',
'CLEAR_BSY_SET_DRQ', 'SET_BSY', 'SET_STS_7F', 'SET_STS_80', 'XFER_CNTR_CLEAR', 'DECR_DWCR', 'DECR_DWCW', 'FIS_FIRST_FLUSH',
......@@ -83,7 +84,7 @@ conditions = [
sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'H:Init'},
{LBL:'HBA_RST', ADDR: 0x2, ACT: NOP},
{ GOTO:'H:Init'},
{ GOTO:'H:HBA_RST'},
{LBL:'PORT_RST', ADDR: 0x4, ACT: NOP},
{ GOTO:'H:Init'},
......@@ -94,6 +95,8 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{LBL:'ST_CLEARED',ADDR: 0x8,ACT: NOP}, # TODO: make sure this jump is not from P:Init
{ GOTO:'P:StartBitCleared'},
{LBL:'H:HBA_RST', ACT: 'HBA_RST_DONE'}, # Reset GHC.HR and other things
{ GOTO:'H:Init'},
{LBL:'H:Init', ACT: NOP},
{ GOTO:'H:WaitForAhciEnable'},
......
host/gtx_wrap.v
View file @ 9c36c48f
......@@ -88,6 +88,7 @@ module gtx_wrap #(
output wire txresetdone,
input wire txcominit,
input wire txcomwake,
output wire txcomfinish, // @txusrclk2
// elastic buffer status
output wire rxelsfull,
output wire rxelsempty,
......@@ -207,7 +208,7 @@ if (DATA_BYTE_WIDTH == 4) begin
reg [ 1:0] txcharisk_enc_in_r; // TODO: remove async reset
wire [38:0] txdata_resync_out;
wire txdata_resync_valid;
reg [1:0] txcomwake_gtx_f; // 2 registers just to match latency (data to the 3 next) in Alexey's code, probbaly not needed
reg [1:0] txcomwake_gtx_f; // 2 registers just to match latency (data to the 3 next) in Alexey's code, probably not needed
reg [1:0] txcominit_gtx_f;
reg [1:0] txelecidle_gtx_f;
......@@ -1261,7 +1262,7 @@ gtxe2_channel_wrapper(
.TXPCSRESET (txpcsreset),
.TXPMARESET (1'b0),
.TXRESETDONE (txresetdone_gtx),
.TXCOMFINISH (),
.TXCOMFINISH (txcomfinish),
.TXCOMINIT (txcominit_gtx),
.TXCOMSAS (1'b0),
.TXCOMWAKE (txcomwake_gtx),
......
host/sata_phy.v
View file @ 9c36c48f
......@@ -531,6 +531,7 @@ gtx_wrap
.txresetdone (txresetdone), // output wire
.txcominit (txcominit), // input wire
.txcomwake (txcomwake), // input wire
.txcomfinish (), // output wire
.rxelsfull (rxelsfull), // output wire
.rxelsempty (rxelsempty), // output wire
.txdata (txdata), // input [31:0] wire
......
includes/ahxi_fsm_code.vh
View file @ 9c36c48f
, .INIT_00 (256'h00100000000E0000000C00000033000000200000000A0000000A0000000A0000)
, .INIT_01 (256'h001944521C399446543044170000001900880019003002020204008400220006)
, .INIT_02 (256'h001900050019C82E000C04020110002924FB2503024000190003004204040000)
, .INIT_03 (256'h845284BE44374C682C4214190012003900880018000A02080022001901020090)
, .INIT_04 (256'h00190110003901100019144601020030020202040039B07D707A041000398C6B)
, .INIT_05 (256'h64540C2504580000004E24FB250300C0004C24FB250300C0005C000000390000)
, .INIT_06 (256'hD10550F8903900A00104006B0202005000E2A89368F018E918CB98A758D73882)
, .INIT_07 (256'h0060003900000039B07D00000050004400220039B07D707A307730F001080071)
, .INIT_08 (256'h00050091C88F002200240091288B28FF000C0110008624FB25030240009CD0FD)
, .INIT_09 (256'h48A528A128FF00140039487F0CAD28FF0110009724FB25030140005004020091)
, .INIT_0A (256'h8839089C040800AD011000AB24FB250300C000500081005048A5002200240039)
, .INIT_0B (256'h00C004080039889C040800090039889C50BA0024004800B5D0FD50F8012000B1)
, .INIT_0C (256'h011000CF24FB250304200039889C50BA00240028011000C5C50324FB24FB0220)
, .INIT_0D (256'h0050C8E028FF000C011000DB24FB25030440003934D2000000D4001100D4C8D2)
, .INIT_0E (256'h00F60082011000ED24FB250300C000390401011000E624FB2503018000500101)
, .INIT_0F (256'h02010101002100FD021001010021004400F6000000F6011000F424FB250300C0)
, .INIT_10 (256'h0000000000000000000000000000000000000039004101050210010100000101)
, .INITP_00 (256'hC8220098170902401E272722222800309418810820809C802018880022222222)
, .INITP_01 (256'h88882227209C82720A09C22089C680272181A01CB889C8605A2A89C882068270)
, .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000888)
, .INIT_00 (256'h00100000000E0000000C02020035000000220000000C0000000A0000000C0000)
, .INIT_01 (256'h1C3B9448543244190000001B0108001B00500402040401040022000600120000)
, .INIT_02 (256'h001BC8300014000C0210002B24FD25050440001B0003004200180000001B4454)
, .INIT_03 (256'h44394C6A2C44141B0012003B01080028000A04080022001B01020110001B0005)
, .INIT_04 (256'h003B0210001B14480102005004020404003BB07F707C0060003B8C6D845484C0)
, .INIT_05 (256'h045A0000005024FD25050140004E24FD25050140005E0000003B0000001B0210)
, .INIT_06 (256'h903B01200204006D0402009000E4A89568F218EB18CD98A958D9388464560C27)
, .INIT_07 (256'h0000003BB07F0000005200840022003BB07F707C307930F202080073D10750FA)
, .INIT_08 (256'hC891002200440093288D290100140210008824FD25050440009ED0FF00A0003B)
, .INIT_09 (256'h29010024003B48810CAF29010210009924FD250502400052000C009300050093)
, .INIT_0A (256'h003000AF021000AD24FD2505014000520081005248A700220044003B48A728A3)
, .INIT_0B (256'h003B889E00300009003B889E50BC0044008800B7D0FF50FA022000B3883B089E)
, .INIT_0C (256'h24FD250500C0003B889E50BC00440048021000C7C50524FD24FD042000C20030)
, .INIT_0D (256'h29010014021000DD24FD25050180003B34D4000000D6001100D6C8D4021000D1)
, .INIT_0E (256'h021000EF24FD25050140003B0401021000E824FD25050280005201010052C8E2)
, .INIT_0F (256'h002100FF041001030021008400F8000000F8021000F624FD2505014000F80082)
, .INIT_10 (256'h0000000000000000000000000000003B00410107041001030000010302010103)
, .INITP_00 (256'h8220098170902401E272722222800309418810820809C8020188800222222222)
, .INITP_01 (256'h8882227209C82720A09C22089C680272181A01CB889C8605A2A89C882068270C)
, .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000008888)
py393sata/x393sata.py
View file @ 9c36c48f
......@@ -1080,6 +1080,12 @@ sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status(),sata.reset_ie(),sata.err_count()
_=mem.mem_dump (0x80000ff0, 4,4)
_=mem.mem_dump (0x80001000, 0x120,4)
for block in range (1,1024):
print("\n======== Reading block %d ==============="%block)
sata.arm_logger()
......
tb/tb_ahci.tf
View file @ 9c36c48f
......@@ -416,7 +416,7 @@ top dut(
assign device_rst = dut.axi_rst;
sata_device dev(
.rst (device_rst),
.rst (1'b1), // FOREVER device_rst),
.RXN (txn),
.RXP (txp),
.TXN (rxn),
......@@ -1284,7 +1284,11 @@ initial begin //Host
maxigp1_print ('h1014,"DATASCOPE 5"); //
maxigp1_print ('h1018,"DATASCOPE 6"); //
maxigp1_print ('h101c,"DATASCOPE 7"); //
// Reset HBA
maxigp1_writep (GHC__GHC__HR__ADDR << 2, 1); // Reset HBA
#12000;
@(posedge CLK);
maxigp1_print (GHC__GHC__HR__ADDR << 2,"GHC__GHC__HR__ADDR after pause");
/*
// Reset port
maxigp1_print ('h3ff << 2,"DEBUG_REGISTER");
......@@ -1394,7 +1398,7 @@ end
initial begin
// #30000;
#70000;
#100000;
// #29630;
// #30000;
// #250000;
......
tb_ahci_01.sav
View file @ 9c36c48f
This diff is collapsed.
wrapper/GTXE2_GPL.v
View file @ 9c36c48f
......@@ -3005,21 +3005,22 @@ always @ (posedge DRPCLK) begin
if (DRPEN) drp_raddr <= DRPADDR;
end
wire reset_or_GTRXRESET = reset || GTRXRESET;
initial
forever @ (posedge reset)
forever @ (posedge reset_or_GTRXRESET)
begin
tx_rst_done <= 1'b0;
@ (negedge reset);
@ (negedge reset_or_GTRXRESET);
repeat (80)
@ (posedge GTREFCLK0);
tx_rst_done <= 1'b1;
end
initial
forever @ (posedge reset)
forever @ (posedge reset_or_GTRXRESET)
begin
rx_rst_done <= 1'b0;
@ (negedge reset);
@ (negedge reset_or_GTRXRESET);
repeat (100)
@ (posedge GTREFCLK0);
rx_rst_done <= 1'b1;
......
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