Commit 8a819cb8 authored by Andrey Filippov's avatar Andrey Filippov

re-generated headers fro new bitstream version

parent dec1994b
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->VivadoTimingReportImplemented_@_rawfile<-@\#\#@-> com.elphel.store.context.VivadoTimingReportImplemented=
eclipse.preferences.version=1 eclipse.preferences.version=1
VivadoSynthesis_@_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> VivadoSynthesis_@_ConstraintsFiles=top.xdc<-@\#\#@->ahci_timing.xdc<-@\#\#@->
VivadoSynthesis_@_MaxMsg=10000 VivadoSynthesis_@_MaxMsg=10000
VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@-> VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_@_ShowInfo=false VivadoSynthesis_@_ShowInfo=false
......
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->VivadoTimingReportImplemented_@_rawfile<-@\#\#@-> com.elphel.store.context.VivadoTimingReportImplemented=
eclipse.preferences.version=1 eclipse.preferences.version=1
...@@ -327,7 +327,8 @@ module axi_ahci_regs#( ...@@ -327,7 +327,8 @@ module axi_ahci_regs#(
end end
always @ (hba_clk) begin /// always @ (hba_clk) begin
always @(posedge hba_clk) begin
was_hba_rst_r <= {was_hba_rst_aclk, was_hba_rst_r[2:1]}; was_hba_rst_r <= {was_hba_rst_aclk, was_hba_rst_r[2:1]};
was_port_rst_r <= {was_port_rst_aclk, was_port_rst_r[2:1]}; was_port_rst_r <= {was_port_rst_aclk, was_port_rst_r[2:1]};
end end
......
...@@ -2,6 +2,6 @@ ...@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800) , .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000) , .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000) , .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE) , .INIT_0C (256'h000000000000000000000000000000000000000001010003001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000) , .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001) , .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
...@@ -97,7 +97,7 @@ ...@@ -97,7 +97,7 @@
// RO: HBA Revision ID // RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62; localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff; localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'h2; localparam PCI_Header__RID__RID__DFLT = 'h3;
// RO: Base Class Code: 1 - Mass Storage Device // RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62; localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000; localparam PCI_Header__CC__BCC__MASK = 'hff000000;
......
...@@ -27,7 +27,8 @@ __status__ = "Development" ...@@ -27,7 +27,8 @@ __status__ = "Development"
#import sys #import sys
# All unspecified ranges/fields default to fT:RO, fC:0 (readonly, reset value = 0) # All unspecified ranges/fields default to fT:RO, fC:0 (readonly, reset value = 0)
RID = 0x02 # Revision ID (use for bitstream version) #RID = 0x02 # Revision ID (use for bitstream version)
RID = 0x03 # Revision ID (use for bitstream version)
VID = 0xfffe # What to use for non-PCI "vendorID"? VID = 0xfffe # What to use for non-PCI "vendorID"?
DID = 0x0001 DID = 0x0001
SSVID = 0xfffe SSVID = 0xfffe
......
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