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Commit dec1994b authored by Andrey Filippov's avatar Andrey Filippov
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updated settings

parent f11d8347
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Showing with 60 additions and 130 deletions
.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs
View file @ dec1994b
FPGA_project_0_SimulationTopFile=tb/tb_top.v
FPGA_project_1_SimulationTopModule=tb
FPGA_project_2_ImplementationTopFile=top.v
FPGA_project_3_ImplementationTopModule=top
FPGA_project_4_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->
FPGA_project_@_ImplementationTopFile=top.v
FPGA_project_@_ImplementationTopModule=top
FPGA_project_@_SimulationTopFile=tb/tb_top.v
FPGA_project_@_SimulationTopModule=tb
FPGA_project_@_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_ImplementationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.ISExst.prefs
View file @ dec1994b
ISExst_170_constraints=ddrc_test01.xcf
ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@->
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@->
ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->
ISExst_@_constraints=ddrc_test01.xcf
com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ dec1994b
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true
VivadoBitstream_125_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->
VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_@_force=true
com.elphel.store.context.VivadoBitstream=<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoPlace.prefs
View file @ dec1994b
VivadoPlace_111_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->
VivadoPlace_@_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ dec1994b
VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_124_ConstraintsFiles=top.xdc<-@\#\#@->ahci_timing.xdc<-@\#\#@->
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->
VivadoSynthesis_@_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_@_MaxMsg=10000
VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_@_ShowInfo=false
VivadoSynthesis_@_flatten_hierarchy=none
VivadoSynthesis_@_parser_mode=1
VivadoSynthesis_@_verbose=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_@_parser_mode<-@\#\#@->VivadoSynthesis_@_OtherProblems<-@\#\#@->VivadoSynthesis_@_ShowInfo<-@\#\#@->VivadoSynthesis_@_MaxMsg<-@\#\#@->VivadoSynthesis_@_ConstraintsFiles<-@\#\#@->VivadoSynthesis_@_flatten_hierarchy<-@\#\#@->VivadoSynthesis_@_verbose<-@\#\#@->
com.elphel.store.version.VivadoSynthesis=1.1
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs
View file @ dec1994b
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->
VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs
View file @ dec1994b
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->VivadoTimingReportImplemented_@_rawfile<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs
View file @ dec1994b
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->
VivadoTimingReportSynthesis_@_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_@_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.iverilog.prefs
View file @ dec1994b
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_119_GTKWaveSavFile<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_122_GrepFindErrWarn<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_95_IcarusTopFile<-@\#\#@->iverilog_@_IcarusTopFile<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_GrepFindErrWarn<-@\#\#@->iverilog_@_IVerilogOther<-@\#\#@->iverilog_@_Param_Exe<-@\#\#@->iverilog_@_VVP_Exe<-@\#\#@->iverilog_@_GtkWave_Exe<-@\#\#@->
com.elphel.store.context.iverilog=iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_GrepFindErrWarn<-@\#\#@->iverilog_@_IcarusTopFile<-@\#\#@->
com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1
iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_103_TopModulesOther=glbl<-@\#\#@->
iverilog_104_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_105_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_105_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_106_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_110_ShowNoProblem=true
iverilog_111_ShowNoProblem=true
iverilog_113_SaveLogsPreprocessor=true
iverilog_114_SaveLogsSimulator=true
iverilog_115_SaveLogsSimulator=true
iverilog_119_GTKWaveSavFile=tb_top_02.sav
iverilog_120_GTKWaveSavFile=tb_ahci_01.sav
iverilog_122_GrepFindErrWarn=error|warning|sorry
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_89_ShowNoProblem=true
iverilog_95_IcarusTopFile=tb/tb_ahci.tf
iverilog_99_GrepFindErrWarn=error|warning|sorry
iverilog_@_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_@_GTKWaveSavFile=tb_ahci_01.sav
iverilog_@_GrepFindErrWarn=error|warning|sorry
iverilog_@_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_@_IcarusTopFile=tb/tb_ahci.tf
iverilog_@_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_@_Param_Exe=/usr/local/bin/iverilog
iverilog_@_SaveLogsPreprocessor=true
iverilog_@_SaveLogsSimulator=true
iverilog_@_ShowNoProblem=true
iverilog_@_TopModulesOther=glbl<-@\#\#@->
iverilog_@_VVP_Exe=/usr/local/bin/vvp
.settings/com.elphel.vdt.FPGA_project.prefs
View file @ dec1994b
FPGA_project_0_SimulationTopFile=tb/tb_top.v
FPGA_project_1_SimulationTopModule=tb
FPGA_project_2_ImplementationTopFile=top.v
FPGA_project_3_ImplementationTopModule=top
FPGA_project_4_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->
FPGA_project_@_ImplementationTopFile=top.v
FPGA_project_@_ImplementationTopModule=top
FPGA_project_@_SimulationTopFile=tb/tb_top.v
FPGA_project_@_SimulationTopModule=tb
FPGA_project_@_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_ImplementationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1
.settings/com.elphel.vdt.ISExst.prefs
View file @ dec1994b
ISExst_170_constraints=ddrc_test01.xcf
ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@->
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@->
ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->
ISExst_@_constraints=ddrc_test01.xcf
com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ dec1994b
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true
VivadoBitstream_125_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->
VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_@_force=true
com.elphel.store.context.VivadoBitstream=<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoPlace.prefs
View file @ dec1994b
VivadoPlace_111_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->
VivadoPlace_@_verbose_place=true
com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ dec1994b
VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_124_ConstraintsFiles=top.xdc<-@\#\#@->ahci_timing.xdc<-@\#\#@->
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->
VivadoSynthesis_@_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_@_MaxMsg=10000
VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_@_ShowInfo=false
VivadoSynthesis_@_flatten_hierarchy=none
VivadoSynthesis_@_parser_mode=1
VivadoSynthesis_@_verbose=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_@_parser_mode<-@\#\#@->VivadoSynthesis_@_OtherProblems<-@\#\#@->VivadoSynthesis_@_ShowInfo<-@\#\#@->VivadoSynthesis_@_MaxMsg<-@\#\#@->VivadoSynthesis_@_ConstraintsFiles<-@\#\#@->VivadoSynthesis_@_flatten_hierarchy<-@\#\#@->VivadoSynthesis_@_verbose<-@\#\#@->
com.elphel.store.version.VivadoSynthesis=1.1
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs
View file @ dec1994b
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->
VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs
View file @ dec1994b
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->VivadoTimingReportImplemented_@_rawfile<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs
View file @ dec1994b
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->
VivadoTimingReportSynthesis_@_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_@_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.iverilog.prefs
View file @ dec1994b
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_122_IVerilogOther<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_119_GTKWaveSavFile<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_122_GrepFindErrWarn<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_95_IcarusTopFile<-@\#\#@->iverilog_@_IcarusTopFile<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_GrepFindErrWarn<-@\#\#@->iverilog_@_IVerilogOther<-@\#\#@->iverilog_@_Param_Exe<-@\#\#@->iverilog_@_VVP_Exe<-@\#\#@->iverilog_@_GtkWave_Exe<-@\#\#@->
com.elphel.store.context.iverilog=iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_GrepFindErrWarn<-@\#\#@->iverilog_@_IcarusTopFile<-@\#\#@->
com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1
iverilog_101_TopModulesOther=glbl<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@->
iverilog_103_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_103_TopModulesOther=glbl<-@\#\#@->
iverilog_104_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_105_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_105_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_106_IncludeDir=${verilog_project_loc}/tb<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->
iverilog_110_ShowNoProblem=true
iverilog_111_ShowNoProblem=true
iverilog_113_SaveLogsPreprocessor=true
iverilog_114_SaveLogsSimulator=true
iverilog_115_SaveLogsSimulator=true
iverilog_119_GTKWaveSavFile=tb_top_02.sav
iverilog_120_GTKWaveSavFile=tb_ahci_01.sav
iverilog_122_GrepFindErrWarn=error|warning|sorry
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_89_ShowNoProblem=true
iverilog_95_IcarusTopFile=tb/tb_ahci.tf
iverilog_99_GrepFindErrWarn=error|warning|sorry
iverilog_@_ExtraFiles=x393/glbl.v<-@\#\#@->
iverilog_@_GTKWaveSavFile=tb_ahci_01.sav
iverilog_@_GrepFindErrWarn=error|warning|sorry
iverilog_@_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_@_IcarusTopFile=tb/tb_ahci.tf
iverilog_@_IncludeDir=${verilog_project_loc}/x393<-@\#\#@->${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/host<-@\#\#@->${verilog_project_loc}/tb<-@\#\#@->
iverilog_@_Param_Exe=/usr/local/bin/iverilog
iverilog_@_SaveLogsPreprocessor=true
iverilog_@_SaveLogsSimulator=true
iverilog_@_ShowNoProblem=true
iverilog_@_TopModulesOther=glbl<-@\#\#@->
iverilog_@_VVP_Exe=/usr/local/bin/vvp
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