Commit 8961bd29 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

more debugging with the AHCI driver, changed memory allocation for Python tests

parent f5b1c7a6

.project

+17 −17
Original line number Original line Diff line number Diff line
@@ -52,87 +52,87 @@ 
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ahci/ahci_ctrl_stat.v

+16 −6
Original line number Original line Diff line number Diff line
@@ -139,6 +139,8 @@ module ahci_ctrl_stat #( 
    output                        pxci0,             // pxCI current value

    output                        pxci0,             // pxCI current value

    

    

    input                         hba_reset_done,    // at the end of the HBA reset, clear GHC.HR, GHC.IE

    input                         hba_reset_done,    // at the end of the HBA reset, clear GHC.HR, GHC.IE

    output                        unsolicited_en,    // enable processing of cominit_got and PxERR.DIAG.W interrupts from

                                                     // this bit is reset at reset, set when PxSSTS.DET==3 or PxSCTL.DET==4

    

    

/*

/*

*/    

*/
@@ -187,22 +189,22 @@ module ahci_ctrl_stat #( 
                                         {32{sirq_INF}} & HBA_PORT__PxIS__INFS__MASK | // 'h4000000;

                                         {32{sirq_INF}} & HBA_PORT__PxIS__INFS__MASK | // 'h4000000;

                                         {32{sirq_OF }} & HBA_PORT__PxIS__OFS__MASK |  // 'h1000000;

                                         {32{sirq_OF }} & HBA_PORT__PxIS__OFS__MASK |  // 'h1000000;

                                         {32{sirq_PRC}} & HBA_PORT__PxIS__PRCS__MASK | // 'h400000;

                                         {32{sirq_PRC}} & HBA_PORT__PxIS__PRCS__MASK | // 'h400000;

                                         {32{sirq_PC}} &  HBA_PORT__PxIS__PCS__MASK |  // 'h40;

                                         {32{sirq_PC & unsolicited_en}} &  HBA_PORT__PxIS__PCS__MASK |  // 'h40;

                                         {32{sirq_DP}} &  HBA_PORT__PxIS__DPS__MASK |  // 'h20;

                                         {32{sirq_DP}} &  HBA_PORT__PxIS__DPS__MASK |  // 'h20;

                                         {32{sirq_UF }} & HBA_PORT__PxIS__UFS__MASK |  // 'h10;

                                         {32{sirq_UF }} & HBA_PORT__PxIS__UFS__MASK |  // 'h10;

                                         {32{sirq_SDB}} & HBA_PORT__PxIS__SDBS__MASK | // 'h8;

                                         {32{sirq_SDB}} & HBA_PORT__PxIS__SDBS__MASK | // 'h8;

                                         {32{sirq_DS }} & HBA_PORT__PxIS__DSS__MASK |  // 'h4;

                                         {32{sirq_DS }} & HBA_PORT__PxIS__DSS__MASK |  // 'h4;

                                         {32{sirq_PS }} & HBA_PORT__PxIS__PSS__MASK |  // 'h2;

                                         {32{sirq_PS }} & HBA_PORT__PxIS__PSS__MASK |  // 'h2;

                                         {32{sirq_DHR}} & HBA_PORT__PxIS__DHRS__MASK;  // 'h1;

                                         {32{sirq_DHR}} & HBA_PORT__PxIS__DHRS__MASK;  // 'h1;



// See if sirq_PC should also be enabled by unsolicited_en. Or not?

    wire                   [31:0] serr = {32{sirq_PC}} &  HBA_PORT__PxSERR__DIAG__X__MASK | // 'h4000000;

    wire                   [31:0] serr = {32{sirq_PC & unsolicited_en}} &  HBA_PORT__PxSERR__DIAG__X__MASK | // 'h4000000;

                                         {32{sirq_UF }} & HBA_PORT__PxSERR__DIAG__F__MASK | // 'h2000000;

                                         {32{sirq_UF }} & HBA_PORT__PxSERR__DIAG__F__MASK | // 'h2000000;

                                         {32{serr_DT }} & HBA_PORT__PxSERR__DIAG__T__MASK | // 'h1000000;

                                         {32{serr_DT }} & HBA_PORT__PxSERR__DIAG__T__MASK | // 'h1000000;

                                         {32{serr_DS }} & HBA_PORT__PxSERR__DIAG__S__MASK | // 'h800000;

                                         {32{serr_DS }} & HBA_PORT__PxSERR__DIAG__S__MASK | // 'h800000;

                                         {32{serr_DH }} & HBA_PORT__PxSERR__DIAG__H__MASK | // 'h400000;

                                         {32{serr_DH }} & HBA_PORT__PxSERR__DIAG__H__MASK | // 'h400000;

                                         {32{serr_DC }} & HBA_PORT__PxSERR__DIAG__C__MASK | // 'h200000;

                                         {32{serr_DC }} & HBA_PORT__PxSERR__DIAG__C__MASK | // 'h200000;

                                         {32{serr_DB }} & HBA_PORT__PxSERR__DIAG__B__MASK | // 'h80000;

                                         {32{serr_DB }} & HBA_PORT__PxSERR__DIAG__B__MASK | // 'h80000;

                                         {32{serr_DW }} & HBA_PORT__PxSERR__DIAG__W__MASK | // 'h40000;

                                         {32{serr_DW & unsolicited_en}} & HBA_PORT__PxSERR__DIAG__W__MASK | // 'h40000;

                                         {32{serr_DI }} & HBA_PORT__PxSERR__DIAG__I__MASK | // 'h20000;

                                         {32{serr_DI }} & HBA_PORT__PxSERR__DIAG__I__MASK | // 'h20000;

                                         {32{sirq_PRC}} & HBA_PORT__PxSERR__DIAG__N__MASK | // 'h10000;

                                         {32{sirq_PRC}} & HBA_PORT__PxSERR__DIAG__N__MASK | // 'h10000;

//                                         {32{sirq_IF | sirq_INF }} & HBA_PORT__PxSERR__ERR__E__MASK | // 'h800;

//                                         {32{sirq_IF | sirq_INF }} & HBA_PORT__PxSERR__ERR__E__MASK | // 'h800;
@@ -276,13 +278,14 @@ module ahci_ctrl_stat #( 
    wire                          update_GHC_GHC =          update_ghc  || update_first[6] || update_next[6];

    wire                          update_GHC_GHC =          update_ghc  || update_first[6] || update_next[6];

    

    

    reg                           pfsm_started_r;    

    reg                           pfsm_started_r;    

    reg                           unsolicited_en_r;

    

    

    assign update_busy = (update_all && (|regs_changed)) || (|updating[6:1]);

    assign update_busy = (update_all && (|regs_changed)) || (|updating[6:1]);

    assign update_pending =  | regs_changed;

    assign update_pending =  | regs_changed;

    assign pcmd_fre = |(HBA_PORT__PxCMD__FRE__MASK & PxCMD_r); 

    assign pcmd_fre = |(HBA_PORT__PxCMD__FRE__MASK & PxCMD_r); 

    assign serr_diag_X = |(HBA_PORT__PxSERR__DIAG__X__MASK & PxSERR_r);

    assign serr_diag_X = |(HBA_PORT__PxSERR__DIAG__X__MASK & PxSERR_r);

    assign ssts_det = PxSSTS_r[3:0];

    assign ssts_det = PxSSTS_r[3:0];

    

    assign unsolicited_en = unsolicited_en_r;

//    assign cirq_PRC = swr_HBA_PORT__PxSERR && |(soft_write_data & HBA_PORT__PxSERR__DIAG__N__MASK);

//    assign cirq_PRC = swr_HBA_PORT__PxSERR && |(soft_write_data & HBA_PORT__PxSERR__DIAG__N__MASK);

//    assign cirq_PC =  swr_HBA_PORT__PxSERR && |(soft_write_data & HBA_PORT__PxSERR__DIAG__X__MASK);

//    assign cirq_PC =  swr_HBA_PORT__PxSERR && |(soft_write_data & HBA_PORT__PxSERR__DIAG__X__MASK);
@@ -383,6 +386,13 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; 
    assign pcmd_clo = PxCMD_r[3];   // causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit

    assign pcmd_clo = PxCMD_r[3];   // causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit

    assign pcmd_st =  PxCMD_r[0];   // current value

    assign pcmd_st =  PxCMD_r[0];   // current value

    

    

    always @(posedge mclk) begin

       if (mrst)                                                   unsolicited_en_r <= 0;

       else if (((PxSSTS_r & HBA_PORT__PxSSTS__DET__MASK) == 3) ||

                 (sctl_det == 4))                                  unsolicited_en_r <= 1;

    end





    always @(posedge mclk) begin 

    always @(posedge mclk) begin 

        pcmd_clear_icc_r <= pcmd_clear_icc;

        pcmd_clear_icc_r <= pcmd_clear_icc;

    end

    end

ahci/ahci_fsm.v

+10 −5
Original line number Original line Diff line number Diff line
@@ -236,6 +236,9 @@ module ahci_fsm 
    input                         ch_p,        // prefetchable - only used with non-zero PRDTL or ATAPI bit set

    input                         ch_p,        // prefetchable - only used with non-zero PRDTL or ATAPI bit set

    input                         ch_w,        // Write: system memory -> device

    input                         ch_w,        // Write: system memory -> device

    input                         ch_a,         // ATAPI: 1 means device should send PIO setup FIS for ATAPI command

    input                         ch_a,         // ATAPI: 1 means device should send PIO setup FIS for ATAPI command

    input                         unsolicited_en,    // enable processing of cominit_got and PxERR.DIAG.W interrupts from

                                                     // this bit is reset at reset, set when PxSSTS.DET==3 or PxSCTL.DET==4

    

    output reg             [ 9:0] last_jump_addr // debug feature

    output reg             [ 9:0] last_jump_addr // debug feature

///    input                   [4:0] ch_cfl,      // length of the command FIS in DW, 0 means none. 0 and 1 - illegal,

///    input                   [4:0] ch_cfl,      // length of the command FIS in DW, 0 means none. 0 and 1 - illegal,

                                               // maximal is 16 (0x10)

                                               // maximal is 16 (0x10)
@@ -281,7 +284,8 @@ module ahci_fsm 
    

    

    reg                      [1:0] async_pend_r; // waiting to process cominit_got

    reg                      [1:0] async_pend_r; // waiting to process cominit_got

    reg                            async_from_st; // chnge to multi-bit if there will be more sources for async transitions

    reg                            async_from_st; // chnge to multi-bit if there will be more sources for async transitions

    wire                           asynq_rq = (cominit_got && unsolicited_cominit_en) || pcmd_st_cleared;

//    wire                           asynq_rq = (cominit_got && unsolicited_cominit_en) || pcmd_st_cleared;

    wire                           asynq_rq = (cominit_got && unsolicited_en) || pcmd_st_cleared;

                                   // OK to wait for some time fsm_act_busy is supposed to never hang up

                                   // OK to wait for some time fsm_act_busy is supposed to never hang up

    wire                           async_ackn = !fsm_preload && async_pend_r[0] && ((fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]);   // OK to process async jump

    wire                           async_ackn = !fsm_preload && async_pend_r[0] && ((fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]);   // OK to process async jump

//    reg                            x_rdy_collision_pend;

//    reg                            x_rdy_collision_pend;
@@ -297,8 +301,8 @@ module ahci_fsm 
    

    

    wire                           conditions_ce =  // copy all conditions to the register so they will not change while iterating through them

    wire                           conditions_ce =  // copy all conditions to the register so they will not change while iterating through them

                                       !fsm_transitions_w && !fsm_transitions[0];

                                       !fsm_transitions_w && !fsm_transitions[0];

    reg                            unsolicited_cominit_en; // allow unsolicited COMINITs

//    reg                            unsolicited_cominit_en; // allow unsolicited COMINITs

    wire                           en_cominit; // en_cominit

//    wire                           en_cominit; // en_cominit

    

    

    assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending

    assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending

    assign update_all = fsm_jump[0];

    assign update_all = fsm_jump[0];
@@ -337,7 +341,7 @@ module ahci_fsm 
    localparam LABEL_ST_CLEARED = 11'h008;

    localparam LABEL_ST_CLEARED = 11'h008;





    always @ (posedge mclk) begin

    always @ (posedge mclk) begin

        if      (hba_rst)                     unsolicited_cominit_en <= !was_port_rst;

///        if      (hba_rst)                     unsolicited_cominit_en <= !was_port_rst;

//      else if (en_cominit || comreset_send) unsolicited_cominit_en <= en_cominit;

//      else if (en_cominit || comreset_send) unsolicited_cominit_en <= en_cominit;
@@ -467,7 +471,8 @@ module ahci_fsm 
        .SET_OFFLINE        (set_offline),       // output reg 

        .SET_OFFLINE        (set_offline),       // output reg 

        .R_OK               (send_R_OK),         // output reg 

        .R_OK               (send_R_OK),         // output reg 

        .R_ERR              (send_R_ERR),        // output reg

        .R_ERR              (send_R_ERR),        // output reg

        .EN_COMINIT         (en_cominit),        // output reg

//        .EN_COMINIT         (en_cominit),        // output reg

        .EN_COMINIT         (),                  // output reg

    // FIS TRANSMIT/WAIT DONE

    // FIS TRANSMIT/WAIT DONE

        .FETCH_CMD          (fetch_cmd),         // output reg 

        .FETCH_CMD          (fetch_cmd),         // output reg 

        .ATAPI_XMIT         (atapi_xmit),        // output reg 

        .ATAPI_XMIT         (atapi_xmit),        // output reg

ahci/ahci_top.v

+33 −20
Original line number Original line Diff line number Diff line
@@ -485,6 +485,10 @@ module ahci_top#( 
    wire                   [31:0] debug_dma1;

    wire                   [31:0] debug_dma1;

    wire                   [31:0] debug_dma_h2d;

    wire                   [31:0] debug_dma_h2d;





    wire                          unsolicited_en;    // enable processing of cominit_got and PxERR.DIAG.W interrupts from

                                                     // this bit is reset at reset, set when PxSSTS.DET==3 or PxSCTL.DET==4



    

    assign comreset_send = comreset_send0 && 0;

    assign comreset_send = comreset_send0 && 0;

    

    

    // Async FF

    // Async FF
@@ -673,6 +677,7 @@ module ahci_top#( 
        .ch_a                     (fsnd_ch_a),          // input

        .ch_a                     (fsnd_ch_a),          // input

///        .ch_cfl          (fsnd_ch_cfl),        // input[4:0] 

///        .ch_cfl          (fsnd_ch_cfl),        // input[4:0] 

///        .dwords_sent     (data_out_dwords)     // input[11:0] ????

///        .dwords_sent     (data_out_dwords)     // input[11:0] ????

        .unsolicited_en           (unsolicited_en),     // input

        .last_jump_addr           (last_jump_addr)

        .last_jump_addr           (last_jump_addr)

    );

    );
@@ -870,6 +875,7 @@ wire[1:0] debug_get_fis_busy_r; // output[1:0] 
        .pxci0_clear             (pxci0_clear),             // input

        .pxci0_clear             (pxci0_clear),             // input

        .pxci0                   (pxci0),                   // output

        .pxci0                   (pxci0),                   // output

        .hba_reset_done          (hba_rst_done),            // input

        .hba_reset_done          (hba_rst_done),            // input

        .unsolicited_en          (unsolicited_en),          // output

        .irq                     (irq)                      // output reg 

        .irq                     (irq)                      // output reg 

    );

    );
@@ -1104,6 +1110,8 @@ wire [9:0] xmit_dbg_01; 
// Datascope code

// Datascope code

//`define DATASCOPE_V2

//`define DATASCOPE_V2

// Datascope interface (write to memory that can be software-read)

// Datascope interface (write to memory that can be software-read)

`define DATASCOPE_FIS_DATA 1



`ifdef USE_DATASCOPE

`ifdef USE_DATASCOPE





`ifdef DATASCOPE_V2

`ifdef DATASCOPE_V2
@@ -1256,21 +1264,9 @@ debug_dma_h2d 
    end    

    end    

    

    

    assign datascope_clk = mclk;

    assign datascope_clk = mclk;

//    assign datascope_waddr = datascope_waddr_r;

`ifdef DATASCOPE_FIS_DATA    

    assign datascope_waddr = last_jump_addr;

    assign datascope_waddr = datascope_waddr_r;



    assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || datascope_incoming_run[0] || datascope_link_run;



//    assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || fsnd_done|| xmit_ok || xmit_err; ///   || d2h_ready ;

//    assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || d2h_ready || datascope_link_run;

///    assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || datascope_incoming_run[0] || datascope_link_run;

//    



     assign datascope_we = &datascope_new_jump;

//     assign datascope_di = {14'h3fff,fsnd_pCmdToIssue,  xfer_cntr_zero, datascope_jump_cntr};

     assign datascope_di = {2'h3, fsnd_pCmdToIssue,  xfer_cntr_zero, 2'b0, last_jump_addr[9:0],datascope_jump_cntr};  

       

//    assign datascope_di = d2h_ready? {d2h_type,

/*

    assign datascope_di = datascope_incoming_run[0]? {d2h_type,

    assign datascope_di = datascope_incoming_run[0]? {d2h_type,

                                      debug_in_link[26], // state idle

                                      debug_in_link[26], // state idle

                                      debug_in_link[4:0], // encoded state (1 cycle later)

                                      debug_in_link[4:0], // encoded state (1 cycle later)
@@ -1297,6 +1293,26 @@ debug_dma_h2d 
                                                                                                       debug_in_link[24], // fsnd_dx_err[1], //fsnd_dx_err[2:0],

                                                                                                       debug_in_link[24], // fsnd_dx_err[1], //fsnd_dx_err[2:0],

                                                                                                       debug_in_link[23],

                                                                                                       debug_in_link[23],

                                                                                                       datascope_id[2:0], {12-ADDRESS_BITS{1'b0}}, datascope_waddr_r});

                                                                                                       datascope_id[2:0], {12-ADDRESS_BITS{1'b0}}, datascope_waddr_r});

    always @(posedge mclk) begin

        if    (fsnd_cfis_xmit) datascope_waddr_r <= DATASCOPE_CFIS_START; // start from command FIS

///        if    (mrst) datascope_waddr_r <= DATASCOPE_CFIS_START;

        else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;

    end



`else    

    assign datascope_waddr = last_jump_addr;

    assign datascope_we = &datascope_new_jump;

    assign datascope_di = {2'h3, fsnd_pCmdToIssue,  xfer_cntr_zero, 2'b0, last_jump_addr[9:0],datascope_jump_cntr};  

`endif



//    assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || fsnd_done|| xmit_ok || xmit_err; ///   || d2h_ready ;

//    assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || d2h_ready || datascope_link_run;

//    



//     assign datascope_di = {14'h3fff,fsnd_pCmdToIssue,  xfer_cntr_zero, datascope_jump_cntr};

       

//    assign datascope_di = d2h_ready? {d2h_type,

/*

*/

*/





/*

/*
@@ -1366,7 +1382,8 @@ assign debug_out[7: 5] = { 
                                             h2d_data[11:0]} :    // 12 bits

                                             h2d_data[11:0]} :    // 12 bits

                                             {{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};

                                             {{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};





*/  always @(posedge mclk) begin

*/

  always @(posedge mclk) begin

        if      (mrst)                                      datascope_run[0] <= 0;

        if      (mrst)                                      datascope_run[0] <= 0;

        else if (fsnd_cfis_xmit)                            datascope_run[0] <= 1;

        else if (fsnd_cfis_xmit)                            datascope_run[0] <= 1;

        else if (h2d_valid && h2d_ready && (h2d_type == 2)) datascope_run[0] <= 0;

        else if (h2d_valid && h2d_ready && (h2d_type == 2)) datascope_run[0] <= 0;
@@ -1380,10 +1397,6 @@ assign debug_out[7: 5] = { 
        

        

        datascope_run[1] <= datascope_run[0];

        datascope_run[1] <= datascope_run[0];

        

        

///     if    (fsnd_cfis_xmit) datascope_waddr_r <= DATASCOPE_CFIS_START;

///        if    (mrst) datascope_waddr_r <= DATASCOPE_CFIS_START;

///     else

        if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;

        

        

        

        

        if      (mrst)           datascope_id <= 0;

        if      (mrst)           datascope_id <= 0;

py393sata/x393sata.py

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