Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393_sata
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393_sata
Commits
8236e82b
Commit
8236e82b
authored
Mar 11, 2016
by
Andrey Filippov
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
removed unused/unmaintained files
parent
78539c1a
Changes
15
Hide whitespace changes
Inline
Side-by-side
Showing
15 changed files
with
18 additions
and
7095 deletions
+18
-7095
.project
.project
+17
-17
com.elphel.vdt.FPGA_project.prefs
.settings/com.elphel.vdt.FPGA_project.prefs
+1
-1
axi_regs.v
dma/axi_regs.v
+0
-150
dma_adapter.v
dma/dma_adapter.v
+0
-547
dma_control.v
dma/dma_control.v
+0
-444
dma_regs.v
dma/dma_regs.v
+0
-297
sata_top.v
dma/sata_top.v
+0
-711
top.v
dma/top.v
+0
-1027
create_ahci_registers.py
helpers/create_ahci_registers.py
+0
-640
command.v
host/command.v
+0
-298
sata_host.v
host/sata_host.v
+0
-722
transport.v
host/transport.v
+0
-1269
ahci_fsm_sequence.py
py393sata/ahci_fsm_sequence.py
+0
-0
tb_top.v
tb/tb_top.v
+0
-670
test_top.v
tb/test_top.v
+0
-302
No files found.
.project
View file @
8236e82b
...
...
@@ -52,87 +52,87 @@
<link>
<name>
vivado_logs/VivadoBitstream.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-201603
08235749196
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-201603
11095400893
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoOpt.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-201603
08235749196
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-201603
11095400893
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoOptPhys.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-201603
08235749196
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-201603
11095400893
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoOptPower.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-201603
08235749196
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-201603
11095400893
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoPlace.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-201603
08235749196
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-201603
11095400893
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoRoute.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-201603
08235749196
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-201603
11095400893
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoSynthesis.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-201603
08235632422
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-201603
11095237675
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoTimimgSummaryReportImplemented.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-201603
08235749196
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-201603
11095400893
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoTimimgSummaryReportSynthesis.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-201603
08235632422
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-201603
11095237675
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoTimingReportImplemented.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-201603
08235749196
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-201603
11095400893
.log
</location>
</link>
<link>
<name>
vivado_logs/VivadoTimingReportSynthesis.log
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-201603
08235632422
.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-201603
11095237675
.log
</location>
</link>
<link>
<name>
vivado_state/x393_sata-opt-phys.dcp
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-201603
08235749196
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-201603
11095400893
.dcp
</location>
</link>
<link>
<name>
vivado_state/x393_sata-opt-power.dcp
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-201603
08235749196
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-201603
11095400893
.dcp
</location>
</link>
<link>
<name>
vivado_state/x393_sata-opt.dcp
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-201603
08235749196
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-201603
11095400893
.dcp
</location>
</link>
<link>
<name>
vivado_state/x393_sata-place.dcp
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-place-201603
08235749196
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-place-201603
11095400893
.dcp
</location>
</link>
<link>
<name>
vivado_state/x393_sata-route.dcp
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-route-201603
08235749196
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-route-201603
11095400893
.dcp
</location>
</link>
<link>
<name>
vivado_state/x393_sata-synth.dcp
</name>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-201603
08235632422
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-201603
11095237675
.dcp
</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.FPGA_project.prefs
View file @
8236e82b
FPGA_project_0_SimulationTopFile=tb/tb_top.v
FPGA_project_1_SimulationTopModule=tb
FPGA_project_2_ImplementationTopFile=
dma/
top.v
FPGA_project_2_ImplementationTopFile=top.v
FPGA_project_3_ImplementationTopModule=top
FPGA_project_4_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1
...
...
dma/axi_regs.v
deleted
100644 → 0
View file @
78539c1a
/*******************************************************************************
* Module: axi_regs
* Date: 2015-07-11
* Author: Alexey
* Description: slave axi interface buffer
*
* Copyright (c) 2015 Elphel, Inc.
* axi_regs.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* axi_regs.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
//`include "axibram_read.v"
//`include "axibram_write.v"
module
axi_regs
(
input
wire
ACLK
,
// AXI PS Master GP1 Clock , input
input
wire
ARESETN
,
// AXI PS Master GP1 Reset, output
// AXI PS Master GP1: Read Address
input
wire
[
31
:
0
]
ARADDR
,
// AXI PS Master GP1 ARADDR[31:0], output
input
wire
ARVALID
,
// AXI PS Master GP1 ARVALID, output
output
wire
ARREADY
,
// AXI PS Master GP1 ARREADY, input
input
wire
[
11
:
0
]
ARID
,
// AXI PS Master GP1 ARID[11:0], output
input
wire
[
3
:
0
]
ARLEN
,
// AXI PS Master GP1 ARLEN[3:0], output
input
wire
[
1
:
0
]
ARSIZE
,
// AXI PS Master GP1 ARSIZE[1:0], output
input
wire
[
1
:
0
]
ARBURST
,
// AXI PS Master GP1 ARBURST[1:0], output
// AXI PS Master GP1: Read Data
output
wire
[
31
:
0
]
RDATA
,
// AXI PS Master GP1 RDATA[31:0], input
output
wire
RVALID
,
// AXI PS Master GP1 RVALID, input
input
wire
RREADY
,
// AXI PS Master GP1 RREADY, output
output
wire
[
11
:
0
]
RID
,
// AXI PS Master GP1 RID[11:0], input
output
wire
RLAST
,
// AXI PS Master GP1 RLAST, input
output
wire
[
1
:
0
]
RRESP
,
// AXI PS Master GP1 RRESP[1:0], input
// AXI PS Master GP1: Write Address
input
wire
[
31
:
0
]
AWADDR
,
// AXI PS Master GP1 AWADDR[31:0], output
input
wire
AWVALID
,
// AXI PS Master GP1 AWVALID, output
output
wire
AWREADY
,
// AXI PS Master GP1 AWREADY, input
input
wire
[
11
:
0
]
AWID
,
// AXI PS Master GP1 AWID[11:0], output
input
wire
[
3
:
0
]
AWLEN
,
// AXI PS Master GP1 AWLEN[3:0], outpu:t
input
wire
[
1
:
0
]
AWSIZE
,
// AXI PS Master GP1 AWSIZE[1:0], output
input
wire
[
1
:
0
]
AWBURST
,
// AXI PS Master GP1 AWBURST[1:0], output
// AXI PS Master GP1: Write Data
input
wire
[
31
:
0
]
WDATA
,
// AXI PS Master GP1 WDATA[31:0], output
input
wire
WVALID
,
// AXI PS Master GP1 WVALID, output
output
wire
WREADY
,
// AXI PS Master GP1 WREADY, input
input
wire
[
11
:
0
]
WID
,
// AXI PS Master GP1 WID[11:0], output
input
wire
WLAST
,
// AXI PS Master GP1 WLAST, output
input
wire
[
3
:
0
]
WSTRB
,
// AXI PS Master GP1 WSTRB[3:0], output
// AXI PS Master GP1: Write response
output
wire
BVALID
,
// AXI PS Master GP1 BVALID, input
input
wire
BREADY
,
// AXI PS Master GP1 BREADY, output
output
wire
[
11
:
0
]
BID
,
// AXI PS Master GP1 BID[11:0], input
output
wire
[
1
:
0
]
BRESP
,
// AXI PS Master GP1 BRESP[1:0], input
// registers iface
input
wire
[
31
:
0
]
bram_rdata
,
output
wire
[
31
:
0
]
bram_waddr
,
output
wire
[
31
:
0
]
bram_wdata
,
output
wire
[
31
:
0
]
bram_raddr
,
output
wire
[
3
:
0
]
bram_wstb
,
output
wire
bram_wen
,
output
wire
bram_ren
,
output
wire
bram_regen
)
;
/*
* Converntional MAXI interface from x393 project
*/
// Interface's instantiation
axibram_write
#(
.
ADDRESS_BITS
(
16
)
)
axibram_write
(
.
aclk
(
ACLK
)
,
.
arst
(
ARESETN
)
,
.
awaddr
(
AWADDR
)
,
.
awvalid
(
AWVALID
)
,
.
awready
(
AWREADY
)
,
.
awid
(
AWID
)
,
.
awlen
(
AWLEN
)
,
.
awsize
(
AWSIZE
)
,
.
awburst
(
AWBURST
)
,
.
wdata
(
WDATA
)
,
.
wvalid
(
WVALID
)
,
.
wready
(
WREADY
)
,
.
wid
(
WID
)
,
.
wlast
(
WLAST
)
,
.
wstb
(
WSTRB
)
,
.
bvalid
(
BVALID
)
,
.
bready
(
BREADY
)
,
.
bid
(
BID
)
,
.
bresp
(
BRESP
)
,
.
pre_awaddr
()
,
.
start_burst
()
,
.
dev_ready
(
1'b1
)
,
.
bram_wclk
()
,
.
bram_waddr
(
bram_waddr
[
15
:
0
])
,
.
pre_bram_wen
()
,
.
bram_wen
(
bram_wen
)
,
.
bram_wstb
(
bram_wstb
)
,
.
bram_wdata
(
bram_wdata
)
)
;
axibram_read
#(
.
ADDRESS_BITS
(
16
)
)
axibram_read
(
.
aclk
(
ACLK
)
,
.
arst
(
ARESETN
)
,
.
araddr
(
ARADDR
)
,
.
arvalid
(
ARVALID
)
,
.
arready
(
ARREADY
)
,
.
arid
(
ARID
)
,
.
arlen
(
ARLEN
)
,
.
arsize
(
ARSIZE
)
,
.
arburst
(
ARBURST
)
,
.
rdata
(
RDATA
)
,
.
rvalid
(
RVALID
)
,
.
rready
(
RREADY
)
,
.
rid
(
RID
)
,
.
rlast
(
RLAST
)
,
.
rresp
(
RRESP
)
,
.
pre_araddr
()
,
.
start_burst
()
,
.
dev_ready
(
1'b1
)
,
.
bram_rclk
()
,
.
bram_raddr
(
bram_raddr
[
15
:
0
])
,
.
bram_ren
(
bram_ren
)
,
.
bram_regen
(
bram_regen
)
,
.
bram_rdata
(
bram_rdata
)
)
;
endmodule
dma/dma_adapter.v
deleted
100644 → 0
View file @
78539c1a
/*******************************************************************************
* Module: dma_adapter
* Date: 2015-07-11
* Author: Alexey
* Description: temporary interconnect to membridge testing purposes only
*
* Copyright (c) 2015 Elphel, Inc.
* dma_adapter.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dma_adapter.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
/*
* The module is temporary
* It could make transactions from DMA data buffer to membridge and vice versa.
* Processes 1 transaction of 16 x 64bit-words at a time.
* Waits until 1 read or 1 write is completely done.
* After that it deasserts busy and is ready to process a new transaction.
*
* The whole purpose of a module as a system block is to be a buffer between
* a big dma data storage and axi interface. So it shall recieve data and control
* for 1 burst and pass it to axi.
*/
module
dma_adapter
(
input
wire
clk
,
input
wire
rst
,
// cmd iface
input
wire
cmd_type
,
// 1 = wr, 0 = rd
input
wire
cmd_val
,
// issue a cmd
input
wire
[
31
:
7
]
cmd_addr
,
// [2:0] - 64-bit (8-bytes) word offset, [6:3] - 16-words transfer offset
output
wire
cmd_busy
,
// no-pipelined cmd execution, 1 cmd at a time
// data iface
input
wire
[
63
:
0
]
wr_data_in
,
input
wire
wr_val_in
,
output
wire
wr_ack_out
,
output
wire
[
63
:
0
]
rd_data_out
,
output
wire
rd_val_out
,
input
wire
rd_ack_in
,
// membridge iface
output
wire
[
7
:
0
]
cmd_ad
,
output
wire
cmd_stb
,
input
wire
[
7
:
0
]
status_ad
,
input
wire
status_rq
,
output
wire
status_start
,
input
wire
frame_start_chn
,
input
wire
next_page_chn
,
output
wire
cmd_wrmem
,
output
wire
page_ready_chn
,
output
wire
frame_done_chn
,
output
wire
[
15
:
0
]
line_unfinished_chn1
,
input
wire
suspend_chn1
,
output
wire
xfer_reset_page_rd
,
output
wire
buf_wpage_nxt
,
output
wire
buf_wr
,
output
wire
[
63
:
0
]
buf_wdata
,
output
wire
xfer_reset_page_wr
,
output
wire
buf_rpage_nxt
,
output
wire
buf_rd
,
input
wire
[
63
:
0
]
buf_rdata
,
// additinal wire to indicate if membridge recieved a packet
input
wire
rdata_done
// = membridge.is_last_in_page & membridge.afi_rready;
)
;
reg
[
2
:
0
]
membr_state
;
// cmd handling
// if not busy and got cmd with val => cmd recieved, assert busy, start a respective algorithm
wire
wr_start
;
wire
rd_start
;
wire
dma_start
;
reg
wr_done
;
reg
rd_done
;
reg
cmd_type_r
;
reg
[
31
:
7
]
cmd_addr_r
;
reg
cmd_busy_r
;
wire
set_busy
;
wire
clr_busy
;
assign
set_busy
=
~
cmd_busy_r
&
cmd_val
;
assign
clr_busy
=
cmd_busy_r
&
(
wr_done
|
rd_done
)
;
assign
cmd_busy
=
cmd_busy_r
;
assign
wr_start
=
set_busy
&
cmd_type
;
assign
rd_start
=
set_busy
&
~
cmd_type
;
always
@
(
posedge
clk
)
begin
cmd_type_r
<=
rst
?
1'b0
:
set_busy
?
cmd_type
:
cmd_type_r
;
cmd_addr_r
<=
rst
?
25'b0
:
set_busy
?
cmd_addr
[
31
:
7
]
:
cmd_addr_r
[
31
:
7
]
;
cmd_busy_r
<=
(
cmd_busy_r
|
set_busy
)
&
~
rst
&
~
clr_busy
;
end
/*
* Read/write data state machine
* For better readability the state machine is splitted to two pieces:
* the first one is responsible only for the CMD WRITE case handling,
* the second one, respectively, for CMD READ
*
* Simultaniously with each fsm starts a membridge fsm, which, if being 1st time launched,
* sets up membridge's registers, or, if have been launched before, just programs read/write
* address.
*
* Current implementation is extremely slow, but simple and reliable
* After all other parts are implemented and this place occurs to be a bottleneck
* then replace it (and may be membridge too) with something more ... pipelined
*/
// check if memberidge was already set up
reg
membr_is_set
;
always
@
(
posedge
clk
)
membr_is_set
<=
(
membr_is_set
|
dma_start
)
&
~
rst
;
// common state register
reg
[
3
:
0
]
rdwr_state
;
// Get data from buffer
localparam
IDLE
=
0
;
//localparam READ_IDLE = 0;
localparam
READ_WAIT_ADDR
=
3
;
localparam
READ_DATA
=
4
;
wire
rd_reset_page
;
reg
rd_next_page
;
wire
[
63
:
0
]
rd_data
;
reg
[
6
:
0
]
rd_data_count
;
reg
rd_en
;
wire
rd_stop
;
wire
[
6
:
0
]
rd_cnt_to_pull
;
assign
rd_cnt_to_pull
=
7'hf
;
assign
rd_stop
=
rd_ack_in
&
rd_data_count
==
rd_cnt_to_pull
;
assign
rd_reset_page
=
1'b0
;
assign
rd_data
=
buf_rdata
;
assign
rd_val_out
=
rd_en
;
assign
rd_data_out
=
rd_data
;
/*always @ (posedge clk)
if (rst)
begin
rdwr_state <= READ_IDLE;
rd_done <= 1'b0;
rd_data_count <= 7'h0;
rd_next_page <= 1'b0;
rd_en <= 1'b0;
end
else
case (rdwr_state)
READ_IDLE:
begin
rdwr_state <= rd_start ? READ_WAIT_ADDR : READ_IDLE;
rd_done <= 1'b0;
rd_data_count <= 7'h0;
rd_next_page <= 1'b0;
rd_en <= 1'b0;
end
READ_WAIT_ADDR: // wait until address information is sent to the bus and input buffer got data
begin
rdwr_state <= membr_state == READ_IDLE & rdata_done ? READ_DATA : READ_WAIT_ADDR;
rd_done <= 1'b0;
rd_data_count <= 7'h0;
rd_next_page <= 1'b0;
rd_en <= 1'b0;
end
READ_DATA:
begin
rdwr_state <= rd_stop ? READ_IDLE : READ_DATA;
rd_done <= rd_stop ? 1'b1 : 1'b0;
rd_data_count <= rd_ack_in ? rd_data_count + 1'b1 : rd_data_count;
rd_next_page <= rd_stop ? 1'b1 : 1'b0;
rd_en <= rd_ack_in ? 1'b1 : 1'b0;
end
default: // write is processing
begin
rdwr_state <= READ_IDLE;
rd_done <= 1'b0;
rd_data_count <= 7'h0;
rd_next_page <= 1'b0;
rd_en <= 1'b0;
end
endcase
*/
// Put data into buffer
//localparam WRITE_IDLE = 0;
localparam
WRITE_DATA
=
1
;
localparam
WRITE_WAIT_ADDR
=
2
;
reg
wr_en
;
reg
wr_reset_page
;
reg
wr_next_page
;
reg
[
63
:
0
]
wr_data
;
reg
[
6
:
0
]
wr_data_count
;
reg
wr_page_ready
;
reg
wr_val
;
wire
[
6
:
0
]
wr_cnt_to_push
;
wire
wr_stop
;
assign
wr_cnt_to_push
=
7'hf
;
assign
wr_stop
=
wr_val_in
&
wr_data_count
==
wr_cnt_to_push
;
assign
wr_ack_out
=
wr_val_in
&
rdwr_state
==
WRITE_DATA
;
//assign wr_data_in = wr_data;
// assuming for now we write only pre-defined 16 64-bit words
always
@
(
posedge
clk
)
if
(
rst
)
begin
rdwr_state
<=
IDLE
;
rd_done
<=
1'b0
;
rd_data_count
<=
7'h0
;
rd_next_page
<=
1'b0
;
rd_en
<=
1'b0
;
wr_done
<=
1'b0
;
wr_data_count
<=
7'd0
;
wr_val
<=
1'b0
;
wr_data
<=
64'h0
;
wr_next_page
<=
1'b0
;
wr_reset_page
<=
1'b0
;
wr_en
<=
1'b0
;
wr_page_ready
<=
1'b0
;
end
else
case
(
rdwr_state
)
IDLE:
begin
rdwr_state
<=
rd_start
?
READ_WAIT_ADDR
:
wr_start
?
WRITE_DATA
:
IDLE
;
rd_done
<=
1'b0
;
rd_data_count
<=
7'h0
;
rd_next_page
<=
1'b0
;
rd_en
<=
1'b0
;
wr_data_count
<=
7'd0
;
wr_done
<=
1'b0
;
wr_data
<=
64'h0
;
wr_next_page
<=
1'b0
;
wr_reset_page
<=
wr_start
?
1'b1
:
1'b0
;
wr_en
<=
1'b0
;
wr_page_ready
<=
1'b0
;
end
WRITE_DATA:
begin
wr_done
<=
wr_stop
&
membr_state
==
IDLE
?
1'b1
:
1'b0
;
wr_data_count
<=
wr_val_in
?
wr_data_count
+
1'b1
:
wr_data_count
;
wr_data
<=
wr_data_in
;
wr_next_page
<=
wr_stop
?
1'b1
:
1'b0
;
wr_reset_page
<=
1'b0
;
wr_en
<=
wr_val_in
;
wr_page_ready
<=
wr_stop
?
1'b1
:
1'b0
;
rdwr_state
<=
wr_stop
&
membr_state
==
IDLE
?
IDLE
:
wr_stop
?
WRITE_WAIT_ADDR
:
WRITE_DATA
;
rd_done
<=
1'b0
;
rd_data_count
<=
7'h0
;
rd_next_page
<=
1'b0
;
rd_en
<=
1'b0
;
end
WRITE_WAIT_ADDR:
// in case all data is written into a buffer, but address is still being issued on axi bus
begin
wr_done
<=
membr_state
==
IDLE
?
1'b1
:
1'b0
;
wr_data_count
<=
7'd0
;
wr_data
<=
64'h0
;
wr_next_page
<=
1'b0
;
wr_reset_page
<=
1'b0
;
wr_en
<=
1'b0
;
wr_page_ready
<=
1'b0
;
rdwr_state
<=
membr_state
==
IDLE
?
IDLE
:
WRITE_WAIT_ADDR
;
rd_done
<=
1'b0
;
rd_data_count
<=
7'h0
;
rd_next_page
<=
1'b0
;
rd_en
<=
1'b0
;
end
READ_WAIT_ADDR:
// wait until address information is sent to the bus and input buffer got data
begin
rdwr_state
<=
membr_state
==
IDLE
&
rdata_done
?
READ_DATA
:
READ_WAIT_ADDR
;
rd_done
<=
1'b0
;
rd_data_count
<=
7'h0
;
rd_next_page
<=
1'b0
;
rd_en
<=
1'b0
;
wr_done
<=
1'b0
;
wr_data_count
<=
7'd0
;
wr_data
<=
64'h0
;
wr_next_page
<=
1'b0
;
wr_reset_page
<=
1'b0
;
wr_en
<=
1'b0
;
wr_page_ready
<=
1'b0
;
end
READ_DATA:
begin
rdwr_state
<=
rd_stop
?
IDLE
:
READ_DATA
;
rd_done
<=
rd_stop
?
1'b1
:
1'b0
;
rd_data_count
<=
rd_ack_in
?
rd_data_count
+
1'b1
:
rd_data_count
;
rd_next_page
<=
rd_stop
?
1'b1
:
1'b0
;
rd_en
<=
rd_ack_in
?
1'b1
:
1'b0
;
wr_done
<=
1'b0
;
wr_data_count
<=
7'd0
;
wr_data
<=
64'h0
;
wr_next_page
<=
1'b0
;
wr_reset_page
<=
1'b0
;
wr_en
<=
1'b0
;
wr_page_ready
<=
1'b0
;
end
default:
// read is executed
begin
wr_done
<=
1'b0
;
wr_data_count
<=
7'd0
;
wr_data
<=
64'h0
;
wr_next_page
<=
1'b0
;
wr_reset_page
<=
1'b0
;
wr_en
<=
1'b0
;
wr_page_ready
<=
1'b0
;
rdwr_state
<=
IDLE
;
rd_done
<=
1'b0
;
rd_data_count
<=
7'h0
;
rd_next_page
<=
1'b0
;
rd_en
<=
1'b0
;
end
endcase
// membridge interface assigments
assign
status_start
=
1'b0
;
// no need until status is used
assign
cmd_wrmem
=
~
cmd_type_r
;
assign
xfer_reset_page_wr
=
rd_reset_page
;
assign
buf_rpage_nxt
=
rd_next_page
;
assign
buf_rd
=
rd_en
;
assign
buf_wdata
=
wr_data
;
assign
buf_wr
=
wr_en
;
assign
buf_wpage_nxt
=
wr_next_page
;
assign
xfer_reset_page_rd
=
wr_reset_page
;
assign
page_ready_chn
=
cmd_wrmem
?
1'b0
:
wr_page_ready
;
assign
frame_done_chn
=
1'b1
;
/*
* Transfer address and membridge set-ups state machine
*/
localparam
MEMBR_IDLE
=
0
;
localparam
MEMBR_MODE
=
1
;
localparam
MEMBR_WIDTH
=
2
;
localparam
MEMBR_LEN
=
3
;
localparam
MEMBR_START
=
4
;
localparam
MEMBR_SIZE
=
5
;
localparam
MEMBR_LOADDR
=
6
;
localparam
MEMBR_CTRL
=
7
;
reg
[
31
:
0
]
membr_data
;
reg
[
15
:
0
]
membr_addr
;
reg
membr_start
;
reg
membr_done
;
reg
membr_setup
;
// indicates the first tick of the state
wire
membr_inprocess
;
assign
dma_start
=
wr_start
|
rd_start
;
always
@
(
posedge
clk
)
if
(
rst
)
begin
membr_data
<=
32'h0
;
membr_addr
<=
16'h0
;
membr_start
<=
1'b0
;
membr_setup
<=
1'b0
;
membr_done
<=
1'b0
;
membr_state
<=
MEMBR_IDLE
;
end
else
case
(
membr_state
)
MEMBR_IDLE:
begin
membr_data
<=
32'h0
;
membr_addr
<=
16'h200
;
membr_start
<=
dma_start
?
1'b1
:
1'b0
;
membr_setup
<=
dma_start
?
1'b1
:
1'b0
;
membr_done
<=
1'b0
;
membr_state
<=
dma_start
&
membr_is_set
?
MEMBR_LOADDR
:
dma_start
?
MEMBR_MODE
:
MEMBR_IDLE
;
end
MEMBR_MODE:
begin
membr_data
<=
32'h3
;
membr_addr
<=
16'h207
;
membr_start
<=
membr_inprocess
?
1'b0
:
1'b1
;
membr_setup
<=
membr_inprocess
|
membr_setup
?
1'b0
:
1'b1
;
membr_done
<=
1'b0
;
membr_state
<=
membr_inprocess
|
membr_setup
?
MEMBR_MODE
:
MEMBR_WIDTH
;
end
MEMBR_WIDTH:
begin
membr_data
<=
32'h10
;
membr_addr
<=
16'h206
;
membr_start
<=
membr_inprocess
?
1'b0
:
1'b1
;
membr_setup
<=
membr_inprocess
|
membr_setup
?
1'b0
:
1'b1
;
membr_done
<=
1'b0
;
membr_state
<=
membr_inprocess
|
membr_setup
?
MEMBR_WIDTH
:
MEMBR_LEN
;
end
MEMBR_LEN:
begin
membr_data
<=
32'h10
;
membr_addr
<=
16'h205
;
membr_start
<=
membr_inprocess
?
1'b0
:
1'b1
;
membr_setup
<=
membr_inprocess
|
membr_setup
?
1'b0
:
1'b1
;
membr_done
<=
1'b0
;
membr_state
<=
membr_inprocess
|
membr_setup
?
MEMBR_LEN
:
MEMBR_START
;
end
MEMBR_START:
begin
membr_data
<=
32'h0
;
membr_addr
<=
16'h204
;
membr_start
<=
membr_inprocess
?
1'b0
:
1'b1
;
membr_setup
<=
membr_inprocess
|
membr_setup
?
1'b0
:
1'b1
;
membr_done
<=
1'b0
;
membr_state
<=
membr_inprocess
|
membr_setup
?
MEMBR_START
:
MEMBR_SIZE
;
end
MEMBR_SIZE:
begin
membr_data
<=
32'h10
;
membr_addr
<=
16'h203
;
membr_start
<=
membr_inprocess
?
1'b0
:
1'b1
;
membr_setup
<=
membr_inprocess
|
membr_setup
?
1'b0
:
1'b1
;
membr_done
<=
1'b0
;
membr_state
<=
membr_inprocess
|
membr_setup
?
MEMBR_SIZE
:
MEMBR_LOADDR
;
end
MEMBR_LOADDR:
begin
membr_data
<=
{
7'h0
,
cmd_addr_r
[
31
:
7
]
};
membr_addr
<=
16'h202
;
membr_start
<=
membr_inprocess
?
1'b0
:
1'b1
;
membr_setup
<=
membr_inprocess
|
membr_setup
?
1'b0
:
1'b1
;
membr_done
<=
1'b0
;
membr_state
<=
membr_inprocess
|
membr_setup
?
MEMBR_LOADDR
:
MEMBR_CTRL
;
end
MEMBR_CTRL:
begin
membr_data
<=
{
28'h0000000
,
4'b0011
};
membr_addr
<=
16'h200
;
membr_start
<=
membr_inprocess
?
1'b0
:
1'b1
;
membr_setup
<=
1'b0
;
membr_done
<=
membr_inprocess
|
membr_setup
?
1'b0
:
1'b1
;
membr_state
<=
membr_inprocess
|
membr_setup
?
MEMBR_CTRL
:
MEMBR_IDLE
;
end
default:
begin
membr_data
<=
32'h0
;
membr_addr
<=
16'h0
;
membr_start
<=
1'b0
;
membr_setup
<=
1'b0
;
membr_done
<=
1'b0
;
membr_state
<=
MEMBR_IDLE
;
end
endcase
// write to memridge registers fsm
localparam
STATE_IDLE
=
3'h0
;
localparam
STATE_CMD_0
=
3'h1
;
localparam
STATE_CMD_1
=
3'h2
;
localparam
STATE_DATA_0
=
3'h3
;
localparam
STATE_DATA_1
=
3'h4
;
localparam
STATE_DATA_2
=
3'h5
;
localparam
STATE_DATA_3
=
3'h6
;
reg
[
2
:
0
]
state
;