Commit 78da3183 authored by Andrey Filippov's avatar Andrey Filippov

modifying RX input settings

parent 0e68732d
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
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...@@ -21,8 +21,13 @@ ...@@ -21,8 +21,13 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module ahci_sata_layers #( module ahci_sata_layers #(
parameter BITS_TO_START_XMIT = 6, // wait H2D FIFO to have 1 << BITS_TO_START_XMIT to start FIS transmission (or all FIS fits) `ifdef USE_DATASCOPE
parameter DATA_BYTE_WIDTH = 4 parameter ADDRESS_BITS = 10, //for datascope
parameter DATASCOPE_START_BIT = 14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
parameter DATASCOPE_POST_MEAS = 16, // number of measurements to perform after event
`endif
parameter BITS_TO_START_XMIT = 6, // wait H2D FIFO to have 1 << BITS_TO_START_XMIT to start FIS transmission (or all FIS fits)
parameter DATA_BYTE_WIDTH = 4
)( )(
input exrst, // master reset that resets PLL and GTX input exrst, // master reset that resets PLL and GTX
input reliable_clk, // use aclk that runs independently of the GTX input reliable_clk, // use aclk that runs independently of the GTX
...@@ -91,6 +96,14 @@ module ahci_sata_layers #( ...@@ -91,6 +96,14 @@ module ahci_sata_layers #(
output wire txn_out, output wire txn_out,
input wire rxp_in, input wire rxp_in,
input wire rxn_in, input wire rxn_in,
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
output datascope_clk,
output [ADDRESS_BITS-1:0] datascope_waddr,
output datascope_we,
output [31:0] datascope_di,
`endif
`ifdef USE_DRP `ifdef USE_DRP
input drp_rst, input drp_rst,
input drp_clk, input drp_clk,
...@@ -320,6 +333,11 @@ module ahci_sata_layers #( ...@@ -320,6 +333,11 @@ module ahci_sata_layers #(
sata_phy #( sata_phy #(
`ifdef USE_DATASCOPE
.ADDRESS_BITS (ADDRESS_BITS), // for datascope
.DATASCOPE_START_BIT (DATASCOPE_START_BIT),
.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS),
`endif
.DATA_BYTE_WIDTH(4) .DATA_BYTE_WIDTH(4)
) phy ( ) phy (
.extrst (exrst), // input wire .extrst (exrst), // input wire
...@@ -350,7 +368,14 @@ module ahci_sata_layers #( ...@@ -350,7 +368,14 @@ module ahci_sata_layers #(
.cplllock_debug (), .cplllock_debug (),
.usrpll_locked_debug(), .usrpll_locked_debug(),
.re_aligned (serr_DS), // output reg .re_aligned (serr_DS), // output reg
`ifdef USE_DATASCOPE
.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output
.datascope_di (datascope_di), // output[31:0]
.datascope_trig (ll_frame_ackn), // input datascope external trigger
`endif
`ifdef USE_DRP `ifdef USE_DRP
.drp_rst (drp_rst), // input .drp_rst (drp_rst), // input
......
...@@ -182,6 +182,16 @@ module ahci_top#( ...@@ -182,6 +182,16 @@ module ahci_top#(
output irq, // CPU interrupt request output irq, // CPU interrupt request
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
input datascope1_clk,
input [ADDRESS_BITS-1:0] datascope1_waddr,
input datascope1_we,
input [31:0] datascope1_di,
`endif
`ifdef USE_DRP `ifdef USE_DRP
output drp_en, // @aclk strobes drp_ad output drp_en, // @aclk strobes drp_ad
output drp_we, output drp_we,
...@@ -715,7 +725,9 @@ module ahci_top#( ...@@ -715,7 +725,9 @@ module ahci_top#(
.debug_in0 (debug_dma), // input[31:0] .debug_in0 (debug_dma), // input[31:0]
.debug_in1 (debug_dma1), // debug_in_link), // input[31:0] .debug_in1 (debug_dma1), // debug_in_link), // input[31:0]
.debug_in2 (debug_in_phy), // input[31:0] // debug from phy/link .debug_in2 (debug_in_phy), // input[31:0] // debug from phy/link
.debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer // .debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
.debug_in3 ({3'b0, debug_in_link[4:0], 14'b0,last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
`ifdef USE_DRP `ifdef USE_DRP
,.drp_en (drp_en), // output reg ,.drp_en (drp_en), // output reg
.drp_we (drp_we), // output reg .drp_we (drp_we), // output reg
...@@ -730,7 +742,12 @@ module ahci_top#( ...@@ -730,7 +742,12 @@ module ahci_top#(
,.datascope_clk (datascope_clk), // input ,.datascope_clk (datascope_clk), // input
.datascope_waddr (datascope_waddr), // input[9:0] .datascope_waddr (datascope_waddr), // input[9:0]
.datascope_we (datascope_we), // input .datascope_we (datascope_we), // input
.datascope_di (datascope_di) // input[31:0] .datascope_di (datascope_di), // input[31:0]
.datascope1_clk (datascope1_clk), // input
.datascope1_waddr (datascope1_waddr),// input[9:0]
.datascope1_we (datascope1_we), // input
.datascope1_di (datascope1_di) // input[31:0]
`endif `endif
/// .debug_in (debug_in[31:0]) /// .debug_in (debug_in[31:0])
); );
......
...@@ -132,7 +132,12 @@ module axi_ahci_regs#( ...@@ -132,7 +132,12 @@ module axi_ahci_regs#(
,input datascope_clk, ,input datascope_clk,
input [ADDRESS_BITS-1:0] datascope_waddr, input [ADDRESS_BITS-1:0] datascope_waddr,
input datascope_we, input datascope_we,
input [31:0] datascope_di input [31:0] datascope_di,
input datascope1_clk,
input [ADDRESS_BITS-1:0] datascope1_waddr,
input datascope1_we,
input [31:0] datascope1_di
`endif `endif
); );
`ifdef USE_DRP `ifdef USE_DRP
...@@ -142,11 +147,15 @@ module axi_ahci_regs#( ...@@ -142,11 +147,15 @@ module axi_ahci_regs#(
reg drp_ready_r; reg drp_ready_r;
`endif `endif
`ifdef USE_DATASCOPE `ifdef USE_DATASCOPE
localparam AXIBRAM_BITS = ADDRESS_BITS + 1; // number of axi address outputs (one more than ADDRESS_BITS when using datascope) // localparam AXIBRAM_BITS = ADDRESS_BITS + 1; // number of axi address outputs (one more than ADDRESS_BITS when using datascope)
localparam AXIBRAM_BITS = ADDRESS_BITS + 2; // number of axi address outputs (one more than ADDRESS_BITS when using datascope)
wire [31:0] datascope_rdata; wire [31:0] datascope_rdata;
reg [1:0] datascope_sel; // read datascope memory instead of the registers reg [1:0] datascope_sel; // read datascope memory instead of the registers
wire [31:0] datascope1_rdata;
reg [1:0] datascope1_sel; // read datascope memory instead of the registers
always @ (posedge aclk) begin always @ (posedge aclk) begin
datascope_sel <= {datascope_sel[0], bram_raddr[ADDRESS_BITS]}; datascope_sel <= {datascope_sel[0], ~bram_raddr[ADDRESS_BITS+1] & bram_raddr[ADDRESS_BITS]};
datascope1_sel <= {datascope1_sel[0], bram_raddr[ADDRESS_BITS+1] & ~bram_raddr[ADDRESS_BITS]};
end end
`else `else
localparam AXIBRAM_BITS = ADDRESS_BITS; // number of axi address outputs (one more than ADDRESS_BITS when using datascope) localparam AXIBRAM_BITS = ADDRESS_BITS; // number of axi address outputs (one more than ADDRESS_BITS when using datascope)
...@@ -433,7 +442,9 @@ sata_phy_rst_out will be released after the sata clock is stable ...@@ -433,7 +442,9 @@ sata_phy_rst_out will be released after the sata clock is stable
.bram_ren (bram_ren[0]), // output .bram_ren (bram_ren[0]), // output
.bram_regen (bram_ren[1]), // output .bram_regen (bram_ren[1]), // output
`ifdef USE_DATASCOPE `ifdef USE_DATASCOPE
.bram_rdata (datascope_sel[1] ? datascope_rdata : bram_rdata_r) // input[31:0] .bram_rdata ((datascope_sel[1] | datascope1_sel[1]) ?
(datascope1_sel[1]? datascope1_rdata : datascope_rdata) :
bram_rdata_r) // input[31:0]
`else `else
.bram_rdata (bram_rdata_r) // input[31:0] .bram_rdata (bram_rdata_r) // input[31:0]
`endif `endif
...@@ -510,6 +521,24 @@ sata_phy_rst_out will be released after the sata clock is stable ...@@ -510,6 +521,24 @@ sata_phy_rst_out will be released after the sata clock is stable
.web (8'hff), // input[7:0] .web (8'hff), // input[7:0]
.data_in (datascope_di) // input[31:0] .data_in (datascope_di) // input[31:0]
); );
ram_var_w_var_r #(
.REGISTERS (0),
.LOG2WIDTH_WR (5),
.LOG2WIDTH_RD (5),
.DUMMY(0)
) datascope1_mem_i (
.rclk (aclk), // input
.raddr (bram_raddr[9:0]), // input[9:0]
.ren (bram_ren[0]), // input
.regen (bram_ren[1]), // input
.data_out (datascope1_rdata), // output[31:0]
.wclk (datascope1_clk), // input
.waddr (datascope1_waddr), // input[9:0]
.we (datascope1_we), // input
.web (8'hff), // input[7:0]
.data_in (datascope1_di) // input[31:0]
);
`endif `endif
fifo_cross_clocks #( fifo_cross_clocks #(
......
...@@ -40,6 +40,11 @@ ...@@ -40,6 +40,11 @@
// parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen // parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
// parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen // parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle) parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
`ifdef USE_DATASCOPE
parameter DATASCOPE_START_BIT = 14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
parameter DATASCOPE_POST_MEAS = 256, // 16, // number of measurements to perform after event
`endif
parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec) parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software parameter RESET_TO_FIRST_ACCESS = 1 // keep port reset until first R/W any register by software
)( )(
...@@ -223,6 +228,13 @@ ...@@ -223,6 +228,13 @@
reg [2:0] nhrst_r; reg [2:0] nhrst_r;
wire hrst = !nhrst_r[2]; wire hrst = !nhrst_r[2];
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
wire datascope_clk;
wire [ADDRESS_BITS-1:0] datascope_waddr;
wire datascope_we;
wire [31:0] datascope_di;
`endif
`ifdef USE_DRP `ifdef USE_DRP
wire drp_en; wire drp_en;
...@@ -376,6 +388,14 @@ ...@@ -376,6 +388,14 @@
.sctl_ipm (sctl_ipm), // output[3:0] .sctl_ipm (sctl_ipm), // output[3:0]
.sctl_spd (sctl_spd), // output[3:0] .sctl_spd (sctl_spd), // output[3:0]
.irq (irq), // output .irq (irq), // output
`ifdef USE_DATASCOPE
.datascope1_clk (datascope_clk), // input
.datascope1_waddr (datascope_waddr), // input[9:0]
.datascope1_we (datascope_we), // input
.datascope1_di (datascope_di), // input[31:0]
`endif
`ifdef USE_DRP `ifdef USE_DRP
.drp_en (drp_en), // output reg .drp_en (drp_en), // output reg
.drp_we (drp_we), // output reg .drp_we (drp_we), // output reg
...@@ -389,7 +409,12 @@ ...@@ -389,7 +409,12 @@
); );
ahci_sata_layers #( ahci_sata_layers #(
.BITS_TO_START_XMIT(6), `ifdef USE_DATASCOPE
.ADDRESS_BITS (ADDRESS_BITS), // for datascope
.DATASCOPE_START_BIT (DATASCOPE_START_BIT), // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS), // number of measurements to perform after event
`endif
.BITS_TO_START_XMIT (6),
.DATA_BYTE_WIDTH(4) .DATA_BYTE_WIDTH(4)
) ahci_sata_layers_i ( ) ahci_sata_layers_i (
.exrst (exrst), // input .exrst (exrst), // input
...@@ -444,6 +469,12 @@ ...@@ -444,6 +469,12 @@
.txn_out (TXN), // output wire .txn_out (TXN), // output wire
.rxp_in (RXP), // input wire .rxp_in (RXP), // input wire
.rxn_in (RXN), // input wire .rxn_in (RXN), // input wire
`ifdef USE_DATASCOPE
.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output
.datascope_di (datascope_di), // output[31:0]
`endif
`ifdef USE_DRP `ifdef USE_DRP
.drp_rst (arst), // input .drp_rst (arst), // input
.drp_clk (ACLK), // input .drp_clk (ACLK), // input
......
...@@ -9,7 +9,9 @@ create_clock -name gtrefclk -period 6.666 -waveform {0.000 3.333} [get_nets sata ...@@ -9,7 +9,9 @@ create_clock -name gtrefclk -period 6.666 -waveform {0.000 3.333} [get_nets sata
create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/txoutclk] create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/txoutclk]
# recovered sata parallel clock # recovered sata parallel clock
create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk] ##create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk]
create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk_gtx]
###sata_top/ahci_sata_layers_i/phy/gtx_wrap/xclk_gtx sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/xclk_gtx
# txoutclk -> userpll, which gives us 2 clocks: userclk (150MHz) and userclk2 (75MHz) . The second one is sata host clk # txoutclk -> userpll, which gives us 2 clocks: userclk (150MHz) and userclk2 (75MHz) . The second one is sata host clk
###create_generated_clock -name usrclk [get_nets sata_top/ahci_sata_layers_i/phy/CLK] ###create_generated_clock -name usrclk [get_nets sata_top/ahci_sata_layers_i/phy/CLK]
......
...@@ -38,6 +38,11 @@ ...@@ -38,6 +38,11 @@
// All computations have been done in assumption of GTX interface being 20 bits wide! // All computations have been done in assumption of GTX interface being 20 bits wide!
//`include "system_defines.v" //`include "system_defines.v"
module gtx_wrap #( module gtx_wrap #(
`ifdef USE_DATASCOPE
parameter ADDRESS_BITS = 10, // for datascope
parameter DATASCOPE_START_BIT = 14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
parameter DATASCOPE_POST_MEAS = 16, // number of measurements to perform after event
`endif
parameter DATA_BYTE_WIDTH = 4, parameter DATA_BYTE_WIDTH = 4,
parameter TXPMARESET_TIME = 5'h1, parameter TXPMARESET_TIME = 5'h1,
parameter RXPMARESET_TIME = 5'h11, parameter RXPMARESET_TIME = 5'h11,
...@@ -100,6 +105,15 @@ module gtx_wrap #( ...@@ -100,6 +105,15 @@ module gtx_wrap #(
output wire dbg_rxdlysresetdone, output wire dbg_rxdlysresetdone,
output wire [1:0] txbufstatus output wire [1:0] txbufstatus
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
,output datascope_clk,
output [ADDRESS_BITS-1:0] datascope_waddr,
output datascope_we,
output reg [31:0] datascope_di,
input datascope_trig // external trigger event for the datascope
`endif
`ifdef USE_DRP `ifdef USE_DRP
,input drp_rst, ,input drp_rst,
input drp_clk, input drp_clk,
...@@ -110,9 +124,12 @@ module gtx_wrap #( ...@@ -110,9 +124,12 @@ module gtx_wrap #(
output drp_rdy, output drp_rdy,
output [15:0] drp_do output [15:0] drp_do
`endif `endif
); );
wire rxresetdone_gtx; wire rxresetdone_gtx;
wire txresetdone_gtx; wire txresetdone_gtx;
reg wrap_rxreset_; reg wrap_rxreset_;
...@@ -389,8 +406,8 @@ wire RXDLYSRESET; // 6 (rxdlysreset), ...@@ -389,8 +406,8 @@ wire RXDLYSRESET; // 6 (rxdlysreset),
wire RXDLYBYPASS; // 7 (1'b0), // Andrey: p.243: "0: Uses the RX delay alignment circuit." wire RXDLYBYPASS; // 7 (1'b0), // Andrey: p.243: "0: Uses the RX delay alignment circuit."
wire RXDLYEN; // 8 (1'b0), wire RXDLYEN; // 8 (1'b0),
wire RXDLYOVRDEN; // 9 (1'b0), wire RXDLYOVRDEN; // 9 (1'b0),
wire RXDDIEN; // 10 (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode" wire RXDDIEN; // 10 (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode"
wire RXLPMEN; // 11 (1'b0) 1 - enable LP, 0 - DXE
`ifdef USE_DRP `ifdef USE_DRP
sipo_to_xclk_measure #( sipo_to_xclk_measure #(
...@@ -427,7 +444,7 @@ wire RXDDIEN; // 10 (1'b1), // Andrey: p.243: "Set high in RX ...@@ -427,7 +444,7 @@ wire RXDDIEN; // 10 (1'b1), // Andrey: p.243: "Set high in RX
assign RXDLYEN = other_control[ 8]; // 8 (1'b0), assign RXDLYEN = other_control[ 8]; // 8 (1'b0),
assign RXDLYOVRDEN = other_control[ 9]; // 9 (1'b0), assign RXDLYOVRDEN = other_control[ 9]; // 9 (1'b0),
assign RXDDIEN = other_control[10]; // 10 (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode" assign RXDDIEN = other_control[10]; // 10 (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode"
assign RXLPMEN = other_control[11]; // 11 (1'b0) 1 - enable LP, 0 - DXE
`else `else
reg [19:0] rxdata_comma_in_r; reg [19:0] rxdata_comma_in_r;
assign rxdata_comma_in = rxdata_comma_in_r; assign rxdata_comma_in = rxdata_comma_in_r;
...@@ -474,6 +491,7 @@ wire RXDDIEN; // 10 (1'b1), // Andrey: p.243: "Set high in RX ...@@ -474,6 +491,7 @@ wire RXDDIEN; // 10 (1'b1), // Andrey: p.243: "Set high in RX
`else `else
assign RXDDIEN = 1'b0; // 10 (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode" assign RXDDIEN = 1'b0; // 10 (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode"
`endif `endif
assign RXLPMEN = 1'b0; // 11 (1'b0) 1 - enable LP, 0 - DXE
`endif `endif
// aligner status generation // aligner status generation
// if we detected comma & there was 1st realign after non-aligned state -> triggered, we wait until the next comma // if we detected comma & there was 1st realign after non-aligned state -> triggered, we wait until the next comma
...@@ -866,7 +884,8 @@ gtxe2_channel_wrapper #( ...@@ -866,7 +884,8 @@ gtxe2_channel_wrapper #(
.PMA_RSV4 (32'h00000000), .PMA_RSV4 (32'h00000000),
.RX_BIAS_CFG (12'b000000000100), .RX_BIAS_CFG (12'b000000000100),
.DMONITOR_CFG (24'h000A00), .DMONITOR_CFG (24'h000A00),
.RX_CM_SEL (2'b11), // .RX_CM_SEL (2'b11),
.RX_CM_SEL (2'b00), // Andrey
.RX_CM_TRIM (3'b010), .RX_CM_TRIM (3'b010),
.RX_DEBUG_CFG (12'b000000000000), .RX_DEBUG_CFG (12'b000000000000),
.RX_OS_CFG (13'b0000010000000), .RX_OS_CFG (13'b0000010000000),
...@@ -1162,7 +1181,7 @@ gtxe2_channel_wrapper( ...@@ -1162,7 +1181,7 @@ gtxe2_channel_wrapper(
.RXOOBRESET (1'b0), .RXOOBRESET (1'b0),
.RXPCSRESET (1'b0), .RXPCSRESET (1'b0),
.RXPMARESET (1'b0),//rxreset), // p78 .RXPMARESET (1'b0),//rxreset), // p78
.RXLPMEN (1'b0), .RXLPMEN (RXLPMEN), // 1'b0),
.RXCOMSASDET (), .RXCOMSASDET (),
.RXCOMWAKEDET (rxcomwakedet_gtx), .RXCOMWAKEDET (rxcomwakedet_gtx),
.RXCOMINITDET (rxcominitdet_gtx), .RXCOMINITDET (rxcominitdet_gtx),
...@@ -1252,6 +1271,57 @@ gtxe2_channel_wrapper( ...@@ -1252,6 +1271,57 @@ gtxe2_channel_wrapper(
.TXQPISENP () .TXQPISENP ()
); );
`ifdef USE_DATASCOPE
reg [ADDRESS_BITS - 1:0 ] datascope_post_cntr;
reg [ADDRESS_BITS - 1:0 ] datascope_waddr_r;
reg [2:0] datascope_start_r;
wire datascope_event;
reg datascope_event_r;
reg datascope_run;
reg datascope_post_run;
wire datascope_start_w = other_control[DATASCOPE_START_BIT]; // datascope requires USE_DRP to be defined
wire datascope_stop = (DATASCOPE_POST_MEAS == 0) ? datascope_event: (datascope_post_cntr == 0);
reg [2:0] datascope_trig_r;
assign datascope_waddr = datascope_waddr_r;
assign datascope_we = datascope_run;
assign datascope_clk = xclk;
assign datascope_event = (|rxnotintable_dec_out) || (|rxdisperr_dec_out) || realign || (datascope_trig_r[1] && !datascope_trig_r[2]) ;
always @ (posedge xclk) begin
datascope_trig_r <= {datascope_trig_r[1:0], datascope_trig};
datascope_start_r <= {datascope_start_r[1:0],datascope_start_w};
datascope_event_r <=datascope_event;
if (!datascope_start_r[1]) datascope_run <= 0;
else if (!datascope_start_r[2]) datascope_run <= 1;
else if (datascope_stop) datascope_run <= 0;
if (!datascope_run) datascope_post_run <= 0;
else if (datascope_event_r) datascope_post_run <= 1;
if (!datascope_post_run) datascope_post_cntr <= DATASCOPE_POST_MEAS;
else datascope_post_cntr <= datascope_post_cntr - 1;
if (!datascope_start_r[1] && datascope_start_r[0]) datascope_waddr_r <= 0; // for simulator
else if (datascope_run) datascope_waddr_r <= datascope_waddr_r + 1;
if (datascope_start_r[1]) datascope_di <= {
6'b0,
realign, // 25
comma, // 24
1'b0, // 23
state_aligned, // 22
rxnotintable_dec_out[1:0], // 21:20
rxdisperr_dec_out[1:0], // 19:18
rxcharisk_dec_out[1:0], // 17:16
rxdata_dec_out[15:0]}; // 15: 0
end
`endif
always @ (posedge gtrefclk) always @ (posedge gtrefclk)
debug <= ~rxelecidle | debug; debug <= ~rxelecidle | debug;
......
...@@ -728,7 +728,7 @@ assign rcvd_dword0[CODE_OKP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYT ...@@ -728,7 +728,7 @@ assign rcvd_dword0[CODE_OKP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYT
assign rcvd_dword0[CODE_ERRP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_ERRP ] == phy_data_in_r0); assign rcvd_dword0[CODE_ERRP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_ERRP ] == phy_data_in_r0);
assign rcvd_dword0[CODE_CONTP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_CONTP ] == phy_data_in_r0); assign rcvd_dword0[CODE_CONTP] = phy_isk_in_r0[0] && !(|phy_isk_in_r0[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_CONTP ] == phy_data_in_r0);
reg [PRIM_NUM - 1:0] debug_rcvd_dword; // at least oce received after reset reg [PRIM_NUM - 1:0] debug_rcvd_dword; // at least once received after reset
//reg [7:0] debug_alignp_cntr; //reg [7:0] debug_alignp_cntr;
///reg [7:0] debug_unknown_primitives; ///reg [7:0] debug_unknown_primitives;
///reg [7:0] debug_notaligned_primitives; ///reg [7:0] debug_notaligned_primitives;
...@@ -751,7 +751,6 @@ reg [15:0] debug_num_other; // other primitives - not aligh, sync or cont ...@@ -751,7 +751,6 @@ reg [15:0] debug_num_other; // other primitives - not aligh, sync or cont
reg [31:0] debug_unknown_dword; reg [31:0] debug_unknown_dword;
wire debug_is_sync_p_w = phy_isk_in_r0[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_SYNCP ] == phy_data_in_r0); wire debug_is_sync_p_w = phy_isk_in_r0[0] && !(|phy_isk_in_r[DATA_BYTE_WIDTH-1:1]) && (prim_data[CODE_SYNCP ] == phy_data_in_r0);
wire [STATES_COUNT - 1:0] debug_states_concat = { wire [STATES_COUNT - 1:0] debug_states_concat = {
state_idle state_idle
, state_sync_esc , state_sync_esc
...@@ -777,6 +776,8 @@ wire [STATES_COUNT - 1:0] debug_states_concat = { ...@@ -777,6 +776,8 @@ wire [STATES_COUNT - 1:0] debug_states_concat = {
, state_rcvr_goodend , state_rcvr_goodend
, state_rcvr_badend , state_rcvr_badend
}; };
reg [4:0] debug_states_encoded;
reg [STATES_COUNT - 1:0] debug_states_visited; reg [STATES_COUNT - 1:0] debug_states_visited;
always @ (posedge clk) begin always @ (posedge clk) begin
...@@ -825,6 +826,16 @@ always @ (posedge clk) begin ...@@ -825,6 +826,16 @@ always @ (posedge clk) begin
if (rst) debug_states_visited <= 0; if (rst) debug_states_visited <= 0;
else debug_states_visited <= debug_states_visited | debug_states_concat; else debug_states_visited <= debug_states_visited | debug_states_concat;
debug_states_encoded <= { |debug_states_concat[22:16],
|debug_states_concat[15: 8],
(|debug_states_concat[22:20]) | (|debug_states_concat[15:12]) | (|debug_states_concat[7:4]),
debug_states_concat[22] | (|debug_states_concat[19:18]) | (|debug_states_concat[15:14]) |
(|debug_states_concat[11:10]) | (|debug_states_concat[7:6]) | (|debug_states_concat[3:2]),
debug_states_concat[21] | debug_states_concat[19] | debug_states_concat[17] | debug_states_concat[15] |
debug_states_concat[13] | debug_states_concat[11] | debug_states_concat[ 9] | debug_states_concat[7] |
debug_states_concat[ 5] | debug_states_concat[ 3] | debug_states_concat[ 1]};
/* /*
if (rst) debug_rcvd_dword <= 0; if (rst) debug_rcvd_dword <= 0;
debug_alignp_r <= rcvd_dword[CODE_ALIGNP]; debug_alignp_r <= rcvd_dword[CODE_ALIGNP];
...@@ -851,6 +862,35 @@ always @ (posedge clk) begin ...@@ -851,6 +862,35 @@ always @ (posedge clk) begin
else if (debug_state_reset_r == 1) debug_notaligned_primitives <= debug_notaligned_primitives + 1; else if (debug_state_reset_r == 1) debug_notaligned_primitives <= debug_notaligned_primitives + 1;
*/ */
end end
/*wire state_idle;
reg state_sync_esc; // SyncEscape
reg state_nocommerr; // NoComErr
reg state_nocomm; // NoComm
reg state_align; // SendAlign - not used, handled by OOB
reg state_reset; // RESET
// tranmitter branch
reg state_send_rdy; // SendChkRdy