more debugging (0e68732d) · Commits · Elphel / x393_sata

.project

+17 −17

Original line number	Diff line number	Diff line
		@@ -52,87 +52,87 @@
		<link>
		<name>vivado_logs/VivadoBitstream.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160209233437529.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160211193930680.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOpt.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160209233437529.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160211193930680.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPhys.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160209233437529.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160211193930680.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoOptPower.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160209233437529.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160211193930680.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoPlace.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160209233437529.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160211193930680.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoRoute.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160209233437529.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160211193930680.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160209233314772.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160211193930680.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160209233437529.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160211193930680.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160209233314772.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160211193930680.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160209233437529.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160211193930680.log</location>
		</link>
		<link>
		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160209233314772.log</location>
		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160211193930680.log</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt-phys.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160209233437529.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160211193930680.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt-power.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160209233437529.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160211193930680.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-opt.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160209233437529.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160211193930680.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-place.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160209233437529.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160211193930680.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-route.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160209233437529.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160211193930680.dcp</location>
		</link>
		<link>
		<name>vivado_state/x393_sata-synth.dcp</name>
		<type>1</type>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160209233314772.dcp</location>
		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160211193930680.dcp</location>
		</link>
		</linkedResources>
		</projectDescription>

ahci/ahci_sata_layers.v

+6 −3

Original line number	Diff line number	Diff line
		@@ -225,8 +225,8 @@ module ahci_sata_layers #(
		/// assign serr_DS = phy_ready && (cominit_got); // RWC: Link sequence error
		/// assign serr_DC = phy_ready && (serr_DW); // RWC: CRC error in Link layer
		assign serr_DT = phy_ready && (0); // RWC: Transport state transition error
		assign serr_DS = phy_ready && (0); // RWC: Link sequence error
		assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
		// assign serr_DS = phy_ready && (0); // RWC: Link sequence error
		// assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
		// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
		assign serr_DI = phy_ready && (rxelsfull); // RWC: PHY Internal Error // just debugging
		assign serr_EP = phy_ready && (rxelsempty); // RWC: Protocol Error - a violation of SATA protocol detected // just debugging
		@@ -277,7 +277,8 @@ module ahci_sata_layers #(
		.sync_escape_req (syncesc_send), // input wire // TL demands to brutally cancel current transaction
		.sync_escape_ack (syncesc_send_done), // output wire // acknowlegement of a successful reception?
		.incom_stop_req (pcmd_st_cleared), // input wire // TL demands to stop current receiving session
		.link_established (link_established),
		.link_established (link_established), // output wire
		.link_bad_crc (serr_DC), // output wire // Bad CRC at EOF
		// inputs from phy
		.phy_ready (phy_ready), // input wire // phy is ready - link is established
		// data-primitives stream from phy
		@@ -348,6 +349,8 @@ module ahci_sata_layers #(

		.cplllock_debug (),
		.usrpll_locked_debug(),
		.re_aligned (serr_DS), // output reg


		`ifdef USE_DRP
		.drp_rst (drp_rst), // input

host/elastic1632.v

+41 −19

Original line number	Diff line number	Diff line
		@@ -23,7 +23,7 @@
		module elastic1632#(
		parameter DEPTH_LOG2 = 4, // => 16 total rows x16 is for free in Xilinx, but keep it asymmetrical to reduce
		// latency
		parameter OFFSET = 5 // distance between read and write pointers, = wr_ptr - rd_ptr
		parameter OFFSET = 7 // 5 // distance between read and write pointers, = wr_ptr - rd_ptr
		)(
		input wclk,
		input rclk,
		@@ -48,6 +48,7 @@ module elastic1632#(
		localparam ALIGN_PRIM = 32'h7B4A4ABC;
		localparam FIFO_DEPTH = 1 << DEPTH_LOG2;
		localparam CORR_OFFSET = OFFSET - 0;

		reg [15:0] data_in_r;
		reg [1:0] charisk_in_r;
		reg [1:0] notintable_in_r;
		@@ -57,7 +58,9 @@ reg msb_in_r; // input contains MSB
		reg inc_waddr;
		reg [DEPTH_LOG2:0] waddr;
		wire [DEPTH_LOG2-1:0] waddr_minus = waddr[DEPTH_LOG2-1:0] - 1;
		reg [DEPTH_LOG2:0] raddr;
		//reg [DEPTH_LOG2:0] raddr;
		wire [DEPTH_LOG2:0] raddr_w;
		reg [DEPTH_LOG2:0] raddr_r;
		reg [44:0] fifo_ram [0: FIFO_DEPTH -1];
		reg [0:0] prealign_ram[0: FIFO_DEPTH -1];
		reg [FIFO_DEPTH-1:0] fill;
		@@ -67,13 +70,15 @@ reg [2:0] aligned_rclk;
		reg [1:0] dav_rclk;
		wire skip_rclk;
		wire add_rclk;
		wire [44:0] rdata = fifo_ram[raddr[DEPTH_LOG2-1:0]];
		wire align_out = rdata[44];
		wire pre_align_out = prealign_ram[raddr[DEPTH_LOG2-1:0]];
		//wire [44:0] rdata = fifo_ram[raddr[DEPTH_LOG2-1:0]];
		reg [44:0] rdata_r;
		//wire align_out = rdata[44];
		wire align_out = rdata_r[44];
		//wire pre_align_out = prealign_ram[raddr[DEPTH_LOG2-1:0]];
		reg pre_align_out_r;
		reg align_out_r;
		reg [2:0] correct_r;
		wire correct = align_out && (!align_out_r \|\| (pre_align_out && !correct_r[2]));

		wire correct = align_out && (!align_out_r \|\| (pre_align_out_r && !correct_r[2]));

		reg [1:0] full_0; // full at waddr = waddr
		reg [1:0] full_1; // full at waddr = raddr+1
		@@ -85,7 +90,7 @@ wire is_alignp_w = ({data_in, data_in_r} == ALIGN_PRIM) &&
		({notintable_in, notintable_in_r} == 0) &&
		({disperror_in, disperror_in_r} == 0);

		wire [DEPTH_LOG2:0] dbg_diff = waddr-raddr;
		wire [DEPTH_LOG2:0] dbg_diff = waddr-raddr_r;
		wire dbg_dav1 = dav_rclk[1];
		wire dbg_full0 = full_0[1];
		wire dbg_full1 = full_1[1];
		@@ -132,27 +137,44 @@ always @(posedge wclk) begin
		end

		// FIFO read clock domain - system synchronous, 75MHz for SATA2
		localparam [DEPTH_LOG2:0] SIZED0 = 0;
		localparam [DEPTH_LOG2:0] SIZED1 = 1;
		localparam [DEPTH_LOG2:0] SIZED2 = 2;
		// assign raddr_w = aligned_rclk[1]? ( raddr_r + (add_rclk? 0 : (skip_rclk ? 2 : 1))) : 0;
		assign raddr_w = aligned_rclk[1]? ( raddr_r + (add_rclk? SIZED0 : (skip_rclk ? SIZED2 : SIZED1))) : SIZED0;


		always @(posedge rclk) begin

		raddr_r <= raddr_w;

		rdata_r <= fifo_ram[raddr_w[DEPTH_LOG2-1:0]];

		pre_align_out_r <= prealign_ram[raddr_w[DEPTH_LOG2-1:0]];

		if (!aligned32_in_r) aligned_rclk <= 0;
		else aligned_rclk <= {aligned_rclk[1:0],fill[OFFSET-2] \| aligned_rclk[0]};

		if (!aligned32_in_r) dav_rclk <= 0;
		else dav_rclk <= {dav_rclk[0],fill_out[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
		// else dav_rclk <= {dav_rclk[0],fill_out[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
		else dav_rclk <= {dav_rclk[0],fill_out[raddr_r[DEPTH_LOG2-1:0]] ^ raddr_r[DEPTH_LOG2]};

		if (!aligned32_in_r) full_0 <= 1;
		else full_0 <= {full_0[0], fill[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
		// else full_0 <= {full_0[0], fill[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
		else full_0 <= {full_0[0], fill[raddr_r[DEPTH_LOG2-1:0]] ^ raddr_r[DEPTH_LOG2]};

		if (!aligned32_in_r) full_1 <= 1;
		else full_1 <= {full_1[0], fill_1[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
		// else full_1 <= {full_1[0], fill_1[raddr[DEPTH_LOG2-1:0]] ^ raddr[DEPTH_LOG2]};
		else full_1 <= {full_1[0], fill_1[raddr_r[DEPTH_LOG2-1:0]] ^ raddr_r[DEPTH_LOG2]};


		if (!aligned_rclk[1]) raddr <=0;
		else if (!add_rclk) raddr <= raddr + (skip_rclk ? 2 : 1);
		// if (!aligned_rclk[1]) raddr <=0;
		// else if (!add_rclk) raddr <= raddr + (skip_rclk ? 2 : 1);

		disperror_out <= rdata[43:40];
		notintable_out <= rdata[39:36];
		charisk_out <= rdata[35:32];
		data_out <= rdata[31: 0];
		disperror_out <= rdata_r[43:40];
		notintable_out <= rdata_r[39:36];
		charisk_out <= rdata_r[35:32];
		data_out <= rdata_r[31: 0];

		align_out_r <= align_out;

		@@ -164,7 +186,7 @@ end
		assign skip_rclk = correct && dav_rclk[1];
		assign add_rclk = correct && !dav_rclk[1];
		assign isaligned_out = aligned_rclk[2];
		assign full = full_1[1] && !full_0[1];
		assign empty = !full_1[1] && full_0[1];
		assign full = aligned_rclk && full_1[1] && !full_0[1];
		assign empty = aligned_rclk && !full_1[1] && full_0[1];
		endmodule

host/gtx_wrap.v

+50 −4

Original line number	Diff line number	Diff line
		@@ -44,7 +44,10 @@ module gtx_wrap #(
		parameter RXCDRPHRESET_TIME = 5'h1,
		parameter RXCDRFREQRESET_TIME = 5'h1,
		parameter RXDFELPMRESET_TIME = 7'hf,
		parameter RXISCANRESET_TIME = 5'h1
		parameter RXISCANRESET_TIME = 5'h1,

		parameter ELASTIC_DEPTH = 4, //5,
		parameter ELASTIC_OFFSET = 7 // 5 //10
		)
		(
		output reg debug = 0,
		@@ -683,8 +686,8 @@ wire rxcominitdet_gtx;

		`else // OLD_ELASTIC
		elastic1632 #(
		.DEPTH_LOG2(4),
		.OFFSET(5)
		.DEPTH_LOG2 (ELASTIC_DEPTH), // 16 //4),
		.OFFSET (ELASTIC_OFFSET) // 10 //5)
		) elastic1632_i (
		.wclk (xclk), // input 150MHz, recovered
		.rclk (rxusrclk2), // input 75 MHz, system
		@@ -742,8 +745,51 @@ wire xclk_gtx;
		BUFG bufg_txoutclk (.O(txoutclk),.I(txoutclk_gtx));
		//BUFR bufr_xclk (.O(xclk),.I(xclk_mr),.CE(1'b1),.CLR(1'b0));
		//BUFMR bufmr_xclk (.O(xclk_mr),.I(xclk_gtx));
		`ifdef USE_DRP
		wire xclk_gtx_g;

		`ifdef STRAIGHT_XCLK
		BUFH BUFH_i (
		.O(), // output
		.I() // input
		);
		/* Instance template for module clock_inverter */
		clock_inverter clock_inverter_i (
		.rst (),
		.clk_in (), // input
		.invert (), // input
		.clk_out() // output
		);

		BUFG bug_xclk (.O(xclk),.I(xclk_gtx));
		`else
		BUFH bufr_xclk (.O (xclk_gtx_g),
		.I (xclk_gtx));

		clock_inverter bug_xclk (
		.rst (rxreset),
		.clk_in (xclk_gtx_g), // input
		.invert (other_control[15]), // input other_control[15] inverts xclk phase
		.clk_out (xclk)); // output
		`endif


		BUFG bug_xclk (.O(xclk),.I(~xclk_gtx));
		`else
		// VDT bug - incorrectly processes defines when calculating closure
		BUFH BUFH_i (
		.O(), // output
		.I() // input
		);
		/* Instance template for module clock_inverter */
		clock_inverter clock_inverter_i (
		.rst (),
		.clk_in (), // input
		.invert (), // input
		.clk_out() // output
		);

		BUFG bug_xclk (.O(xclk),.I(xclk_gtx));
		`endif

		gtxe2_channel_wrapper #(
		.SIM_RECEIVER_DETECT_PASS ("TRUE"),

host/link.v

+6 −2

Original line number	Diff line number	Diff line
		@@ -79,8 +79,9 @@ module link #(
		output wire sync_escape_ack, // acknowlegement of a successful reception
		input wire incom_stop_req, // TL demands to stop current recieving session
		output link_established, // received 3 back-to-back non-align primitives.
		output reg link_bad_crc, // got bad crc at EOF
		// inputs from phy
		input wire phy_ready, // phy is ready - link is established: Not yet - need 3 non-align primitives
		input wire phy_ready, // phy is ready - link is established
		input wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in, // data-primitives stream from phy
		input wire [DATA_BYTE_WIDTH - 1:0] phy_isk_in, // charisk
		input wire [DATA_BYTE_WIDTH - 1:0] phy_err_in, // disperr \| notintable
		@@ -320,6 +321,9 @@ end
		///assign alignes_pair = link_established_r && (alignes_pair_0 \| alignes_pair_1);
		assign alignes_pair = phy_ready && (alignes_pair_0 \| alignes_pair_1);

		always @ (posedge clk) begin
		link_bad_crc <= state_rcvr_eof & crc_bad;
		end

		// Whole transitions table, literally from doc pages 311-328
		assign set_sync_esc = sync_escape_req;

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