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x393_sata
Commit 6dea1234 authored by Alexey Grebenkin's avatar Alexey Grebenkin
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Synthesisable version with passed oob

parent 4c204cc3
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.settings/com.elphel.vdt.FPGA_project.prefs
View file @ 6dea1234
FPGA_project_0_SimulationTopFile=tb/tb_top.v
FPGA_project_1_SimulationTopModule=tb
FPGA_project_2_ImplementationTopFile=dma/top.v
FPGA_project_3_ImplementationTopModule=top
FPGA_project_4_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->
FPGA_project_5_part=xc7z030fbg484-1
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ 6dea1234
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->
VivadoBitstream_125_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 6dea1234
VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_122_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->
eclipse.preferences.version=1
dma/dma_regs.v
View file @ 6dea1234
......@@ -166,7 +166,7 @@ begin
reg04 <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf1) ? wdata : reg04;
reg08 <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf2) ? wdata : reg08;
reg0c <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf3) ? wdata : reg0c;
reg10 <= rst ? 32'h0 : dma_start_aclk ? 32'h0 : dma_done_aclk ? 32'hffffffff : reg10; // status reg
reg10 <= rst ? 32'h0 : dma_start_aclk ? 32'h0 : {31'h0, dma_done_aclk} ? 32'hffffffff : reg10; // status reg
reg14 <= rst ? 32'h0 : dma_done_aclk ? reg00 : reg14;
end
......
dma/sata_top.v
View file @ 6dea1234
......@@ -32,6 +32,12 @@
output wire sclk,
output wire sata_rst,
input wire extrst,
// reliable clock to source drp and cpll lock det circuits
input wire reliable_clk,
input wire hclk,
/*
* Commands interface
*/
......@@ -228,7 +234,7 @@ wire dma_type;
wire dma_start;
wire dma_done;
// axi-hp clock
wire hclk;
//wire hclk;
// dma_control <-> dma_adapter command iface
wire adp_busy;
wire [31:7] adp_addr;
......@@ -279,10 +285,9 @@ wire [63:0] buf_rdata;
wire rdata_done; // = membridge.is_last_in_page & membridge.afi_rready;
//assign rst = ARESETN;
// TODO
assign hclk = ACLK;
reg hrst;
always @ (posedge hclk)
hrst <= sata_rst;
axi_regs axi_regs(
// axi iface
......@@ -333,7 +338,7 @@ axi_regs axi_regs(
* Programmable sata controller registers
*/
dma_regs dma_regs(
.rst (sata_rst),
.rst (ARESETN),
.ACLK (ACLK),
.sclk (sclk),
// control iface
......@@ -473,7 +478,7 @@ dma_control dma_control(
dma_adapter dma_adapter(
.clk (hclk),
.rst (sata_rst),
.rst (hrst),
// command iface
.cmd_type (adp_type),
.cmd_val (adp_val),
......@@ -526,9 +531,9 @@ V .MEMBRIDGE_ADDR (),
.FRAME_HEIGHT_BITS (),
.FRAME_WIDTH_BITS ()
)*/ membridge(
.mrst (sata_rst), // input
.hrst (ARESETN), // input
.mclk (hclk), // input
.mrst (hrst), // input
.hrst (hrst), // input
.mclk (sclk), // input
.hclk (hclk), // input
.cmd_ad (cmd_ad),
.cmd_stb (cmd_stb),
......@@ -605,6 +610,8 @@ sata_host sata_host(
.rst (sata_rst),
// sata clk
.clk (sclk),
// reliable clock to source drp and cpll lock det circuits
.reliable_clk (reliable_clk),
// temporary
.al_cmd_in (cmd_out), // == {cmd_type, cmd_port, cmd_val, cmd_done_bad, cmd_done_good; cmd_busy}
.al_cmd_val_in (cmd_val_out),
......
dma/top.v
View file @ 6dea1234
......@@ -139,8 +139,8 @@ BUFG bufg_axi_aclk0_i (.O(axi_aclk0),.I(fclk[0]));
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
BUFG bufg_extrst_i (.O(extrst),.I(axi_rst_pre));
axi_hp_clk #(
.CLKIN_PERIOD(6.666),
.CLKFBOUT_MULT_AXIHP(6),
.CLKIN_PERIOD(20.000),
.CLKFBOUT_MULT_AXIHP(18),
.CLKFBOUT_DIV_AXIHP(6)
) axi_hp_clk_i (
.rst (axi_rst), // input
......@@ -151,10 +151,13 @@ axi_hp_clk #(
sata_top sata_top(
.sclk (sclk),
// reliable clock to source drp and cpll lock det circuits
.reliable_clk (axi_aclk0),
.hclk (hclk),
.sata_rst (sata_rst),
.extrst (extrst),
.ACLK (axi_aclk),
.ARESETN (axi_rst | sata_rst),
.ACLK (axi_aclk0),
.ARESETN (axi_rst/* | sata_rst*/),
// AXI PS Master GP1: Read Address
.ARADDR (ARADDR),
.ARVALID (ARVALID),
......@@ -569,7 +572,7 @@ PS7 ps7_i (
// AXI PS Master GP1
// AXI PS Master GP1: Clock, Reset
.MAXIGP1ACLK (axi_aclk), // AXI PS Master GP1 Clock , input
.MAXIGP1ACLK (axi_aclk0), // AXI PS Master GP1 Clock , input
.MAXIGP1ARESETN (), // AXI PS Master GP1 Reset, output
// AXI PS Master GP1: Read Address
.MAXIGP1ARADDR (ARADDR), // AXI PS Master GP1 ARADDR[31:0], output
......
host/command.v
View file @ 6dea1234
......@@ -25,6 +25,11 @@ module command(
input rst,
input clk,
// temporary TODO
input wire gtx_ready,
input wire phy_ready,
input wire [11:0] debug_cnt,
// tl cmd iface
output wire [2:0] cmd_type,
output wire cmd_val,
......@@ -217,10 +222,13 @@ assign sh_autoact_out = sh_autoact;
// temporaty command register TODO
reg [31:0] cmd;
assign al_cmd_out = cmd;
assign al_cmd_out[31:12] = cmd[31:12];
assign al_cmd_out[11:0] = debug_cnt;
always @ (posedge clk)
begin
cmd[31:4] <= rst ? 28'h0 : al_cmd_val_in ? al_cmd_in[31:4] : cmd[31:4];
cmd[27:4] <= rst ? 24'h0 : al_cmd_val_in ? al_cmd_in[27:4] : cmd[27:4];
cmd[31] <= rst ? 1'b1 : cmd[31];
cmd[30:28] <= rst ? 3'h0 : {1'b0, phy_ready, gtx_ready};
cmd[3] <= rst ? 1'b0 : al_cmd_val_in ? al_cmd_in[3] : cmd_val ? 1'b0 : cmd[3];
cmd[2] <= rst ? 1'b0 : al_cmd_val_in ? 1'b0 : cmd_done_bad ? 1'b1 : cmd[2];
cmd[1] <= rst ? 1'b0 : al_cmd_val_in ? 1'b0 : cmd_done_good ? 1'b1 : cmd[1];
......
host/gtx_elastic.v
View file @ 6dea1234
......@@ -64,7 +64,7 @@ localparam HI = DEPTH_LOG2 - 1; // hi bus index
reg [22:0] ram [(1 << DEPTH_LOG2) - 1:0];
// data to/from fifo
wire [22:0] inram;
wire [22:0] outram;
reg [22:0] outram;
// adresses in their natural clock domains
reg [HI:0] rd_addr;
reg [HI:0] wr_addr;
......@@ -142,7 +142,8 @@ endgenerate
assign full = wr_addr == rd_addr_r + 1'b1;
assign empty = wr_addr_r == rd_addr;
assign outram = ram[rd_addr];
always @ (posedge rclk)
outram <= ram[rd_addr];
always @ (posedge wclk)
if (we)
......@@ -283,7 +284,7 @@ wire clr_skip2_align;
wire clr_wait_next_p;
wire clr_send_ack;
always @ (wclk)
always @ (posedge wclk)
next_prim_loaded <= state_wait_next_p;
assign state_bypass_rmv = ~state_wait1_align & ~state_skip1_align & ~state_wait2_align & ~state_skip2_align & ~state_wait_next_p & ~state_send_ack;
......@@ -388,11 +389,15 @@ always @ (posedge rclk)
// choose 1 of 2 words of ALIGNP
wire [22:0] align_word;
assign align_word = {outram[22], 22'h007B4A} & {23{~align_altern}} | {outram[22], 22'h014ABC} & {23{align_altern}};
assign align_word = {outram[22], 22'h007B4A} & {23{align_altern}} | {outram[22], 22'h014ABC} & {23{~align_altern}};
// output data would be valid the next clock they are issued
reg pause_read_r;
always @ (posedge rclk)
pause_read_r <= pause_read;
// read when compensation is not issued and when fifo gets required fullfillment
assign re = ~pause_read & fifo_stable;
assign outdata = {23{~pause_read}} & outram | {23{pause_read}} & align_word;
assign outdata = {23{~pause_read_r}} & outram | {23{pause_read_r}} & align_word;
// indicates last cycle before the next primitive
wire fword_strobe_correction;
reg fword_strobe;
......
host/gtx_wrap.v
View file @ 6dea1234
......@@ -33,6 +33,7 @@ module gtx_wrap #(
parameter RXISCANRESET_TIME = 5'h1
)
(
output reg debug = 0,
output wire cplllock,
input wire cplllockdetclk,
input wire cpllreset,
......@@ -75,11 +76,15 @@ module gtx_wrap #(
wire rxresetdone_gtx;
wire txresetdone_gtx;
wire wrap_rxreset_;
wire wrap_txreset_;
reg rxresetdone_gtx_r;
reg txresetdone_gtx_r;
reg wrap_rxreset_;
reg wrap_txreset_;
// resets while PCS resets, active low
assign wrap_rxreset_ = rxuserrdy & rxresetdone_gtx;
assign wrap_txreset_ = txuserrdy & txresetdone_gtx;
always @ (posedge rxusrclk2)
wrap_rxreset_ <= rxuserrdy & rxresetdone_gtx_r;
always @ (posedge txusrclk2)
wrap_txreset_ <= txuserrdy & txresetdone_gtx_r;
wire [63:0] rxdata_gtx;
wire [7:0] rxcharisk_gtx;
......@@ -164,9 +169,19 @@ if (DATA_BYTE_WIDTH == 4) begin
.half_empty ()
);
assign txcomwake_gtx = txdata_resync_out[36];
assign txcominit_gtx = txdata_resync_out[37];
assign txelecidle_gtx = txdata_resync_out[38];
reg txcomwake_gtx_f;
reg txcominit_gtx_f;
reg txelecidle_gtx_f;
always @ (posedge txusrclk)
begin
txcomwake_gtx_f <= txdata_resync_out[36];
txcominit_gtx_f <= txdata_resync_out[37];
txelecidle_gtx_f <= txdata_resync_out[38];
end
assign txcomwake_gtx = txcomwake_gtx_f;
assign txcominit_gtx = txcominit_gtx_f;
assign txelecidle_gtx = txelecidle_gtx_f;
end
else
if (DATA_BYTE_WIDTH == 2) begin
......@@ -309,6 +324,8 @@ gtx_elastic(
*/
wire rxcomwakedet_gtx;
wire rxcominitdet_gtx;
reg rxcomwakedet_gtx_r;
reg rxcominitdet_gtx_r;
// insert resync if it's necessary
......@@ -323,15 +340,15 @@ if (DATA_BYTE_WIDTH == 4) begin
wire rxdata_resync_strobe;
wire [50:0] rxdata_resync_in;
wire [50:0] rxdata_resync_out;
reg [23:0] rxdata_resync_buf;
reg [25:0] rxdata_resync_buf;
assign rxdata_resync_strobe = lword_strobe;
assign rxdata_resync_in = {
isaligned, // 1
rxcomwakedet_gtx, // 1
rxcominitdet_gtx, // 1
rxresetdone_gtx, // 1
txresetdone_gtx, // 1
rxcomwakedet_gtx_r | rxdata_resync_buf[25], // 1
rxcominitdet_gtx_r | rxdata_resync_buf[24], // 1
rxresetdone_gtx_r, // 1
txresetdone_gtx_r, // 1
elastic_full | rxdata_resync_buf[23], // 1
elastic_empty | rxdata_resync_buf[22], // 1
rxdisperr_els_out, // 2
......@@ -340,7 +357,7 @@ if (DATA_BYTE_WIDTH == 4) begin
rxdata_els_out, // 16
rxdata_resync_buf[21:0]}; // 22 / 51 total
always @ (posedge rxusrclk)
rxdata_resync_buf <= ~wrap_rxreset_ ? 24'h0 : ~rxdata_resync_strobe ? {elastic_full, elastic_empty, rxdisperr_els_out, rxnotintable_els_out, rxcharisk_els_out, rxdata_els_out} : rxdata_resync_buf;
rxdata_resync_buf <= ~wrap_rxreset_ ? 26'h0 : ~rxdata_resync_strobe ? {rxcomwakedet_gtx_r, rxcominitdet_gtx_r, elastic_full, elastic_empty, rxdisperr_els_out, rxnotintable_els_out, rxcharisk_els_out, rxdata_els_out} : rxdata_resync_buf;
always @ (posedge rxusrclk2)
rxdata_resync_nempty_r <= rxdata_resync_nempty;
......@@ -378,10 +395,10 @@ else
if (DATA_BYTE_WIDTH == 2) begin
// no resync is needed => straightforward assignments
assign rxbyteisaligned = isaligned;
assign rxcomwakedet = rxcomwakedet_gtx;
assign rxcominitdet = rxcominitdet_gtx;
assign rxresetdone = rxresetdone_gtx;
assign txresetdone = txresetdone_gtx;
assign rxcomwakedet = rxcomwakedet_gtx_r;
assign rxcominitdet = rxcominitdet_gtx_r;
assign rxresetdone = rxresetdone_gtx_r;
assign txresetdone = txresetdone_gtx_r;
assign rxelsfull = elastic_full;
assign rxelsempty = elastic_empty;
assign rxdisperr[1:0] = rxdisperr_els_out;
......@@ -398,6 +415,22 @@ else begin
end
endgenerate
// latching gtx outputs, synchronous to RXUSRCLK2 = rxusrclk
always @ (posedge rxusrclk)
begin
rxcomwakedet_gtx_r <= rxcomwakedet_gtx;
rxcominitdet_gtx_r <= rxcominitdet_gtx;
rxresetdone_gtx_r <= rxresetdone_gtx;
txresetdone_gtx_r <= txresetdone_gtx;
end
wire txoutclk_gtx;
wire xclk_gtx;
wire xclk_mr;
BUFG bufg_txoutclk (.O(txoutclk),.I(txoutclk_gtx));
BUFR bufr_xclk (.O(xclk),.I(xclk_mr),.CE(1'b1),.CLR(1'b0));
BUFMR bufmr_xclk (.O(xclk_mr),.I(xclk_gtx));
gtxe2_channel_wrapper #(
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
......@@ -526,9 +559,9 @@ gtxe2_channel_wrapper #(
.PD_TRANS_TIME_TO_P2 (8'h64),
.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
.SATA_BURST_SEQ_LEN (4'b0110),
.SATA_BURST_VAL (3'b110),
.SATA_EIDLE_VAL (3'b110),
.SATA_BURST_SEQ_LEN (4'b0101),
.SATA_BURST_VAL (3'b100),
.SATA_EIDLE_VAL (3'b100),
.SATA_MAX_BURST (8),
.SATA_MAX_INIT (21),
.SATA_MAX_WAKE (7),
......@@ -631,8 +664,8 @@ gtxe2_channel_wrapper(
.DRPRDY (),
.DRPWE (1'b0),
.GTREFCLKMONITOR (),
.QPLLCLK (gtrefclk),
.QPLLREFCLK (gtrefclk),
.QPLLCLK (1'b0/*gtrefclk*/),
.QPLLREFCLK (1'b0/*gtrefclk*/),
.RXSYSCLKSEL (2'b00),
.TXSYSCLKSEL (2'b00),
.DMONITOROUT (),
......@@ -729,7 +762,7 @@ gtxe2_channel_wrapper(
.RXOSHOLD (1'b0),
.RXOSOVRDEN (1'b0),
.RXRATEDONE (),
.RXOUTCLK (xclk),
.RXOUTCLK (xclk_gtx),
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
.RXOUTCLKSEL (3'b010),
......@@ -806,7 +839,7 @@ gtxe2_channel_wrapper(
.TXDATA (txdata_gtx),
.GTXTXN (txn),
.GTXTXP (txp),
.TXOUTCLK (txoutclk),
.TXOUTCLK (txoutclk_gtx),
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
.TXOUTCLKSEL (3'b010),
......@@ -832,4 +865,7 @@ gtxe2_channel_wrapper(
.TXQPISENP ()
);
always @ (posedge gtrefclk)
debug <= ~rxelecidle | debug;
endmodule
host/link.v
View file @ 6dea1234
......@@ -100,6 +100,17 @@ module link #(
output wire [DATA_BYTE_WIDTH*8 - 1:0] phy_data_out,
output wire [DATA_BYTE_WIDTH - 1:0] phy_isk_out // charisk
);
// latching data-primitives stream from phy
reg [DATA_BYTE_WIDTH*8 - 1:0] phy_data_in_r;
reg [DATA_BYTE_WIDTH - 1:0] phy_isk_in_r; // charisk
reg [DATA_BYTE_WIDTH - 1:0] phy_err_in_r; // disperr | notintable
always @ (posedge clk)
begin
phy_data_in_r <= phy_data_in;
phy_isk_in_r <= phy_isk_in;
phy_err_in_r <= phy_err_in;
end
wire frame_done;
// scrambled data
wire [DATA_BYTE_WIDTH*8 - 1:0] scrambler_out;
......@@ -494,7 +505,7 @@ scrambler scrambler(
.val_in (select_prim[CODE_DATA] | inc_is_data),
.data_in (crc_dword & {DATA_BYTE_WIDTH*8{select_prim[CODE_CRC]}} |
data_in & {DATA_BYTE_WIDTH*8{select_prim[CODE_DATA]}} |
phy_data_in & {DATA_BYTE_WIDTH*8{inc_is_data}}),
phy_data_in_r & {DATA_BYTE_WIDTH*8{inc_is_data}}),
.data_out (scrambler_out)
);
......@@ -557,24 +568,24 @@ assign incom_invalidate = state_rcvr_eof & crc_bad & ~alignes_pair | state_rcvr
// shows that incoming primitive or data is ready to be processed // TODO somehow move alignes_pair into dword_val
assign dword_val = |rcvd_dword & phy_ready & ~rcvd_dword[CODE_ALIGNP];
// determine imcoming primitive type
assign rcvd_dword[CODE_DATA] = ~|phy_isk_in;
assign rcvd_dword[CODE_DATA] = ~|phy_isk_in_r;
assign rcvd_dword[CODE_CRC] = 1'b0;
assign rcvd_dword[CODE_SYNCP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_SYNCP ] == phy_data_in;
assign rcvd_dword[CODE_ALIGNP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_ALIGNP] == phy_data_in;
assign rcvd_dword[CODE_XRDYP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_XRDYP ] == phy_data_in;
assign rcvd_dword[CODE_SOFP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_SOFP ] == phy_data_in;
assign rcvd_dword[CODE_HOLDAP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_HOLDAP] == phy_data_in;
assign rcvd_dword[CODE_HOLDP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_HOLDP ] == phy_data_in;
assign rcvd_dword[CODE_EOFP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_EOFP ] == phy_data_in;
assign rcvd_dword[CODE_WTRMP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_WTRMP ] == phy_data_in;
assign rcvd_dword[CODE_RRDYP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_RRDYP ] == phy_data_in;
assign rcvd_dword[CODE_IPP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_IPP ] == phy_data_in;
assign rcvd_dword[CODE_DMATP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_DMATP ] == phy_data_in;
assign rcvd_dword[CODE_OKP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_OKP ] == phy_data_in;
assign rcvd_dword[CODE_ERRP] = phy_isk_in[0] == 1'b1 & ~|phy_isk_in[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_ERRP ] == phy_data_in;
assign rcvd_dword[CODE_SYNCP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_SYNCP ] == phy_data_in_r;
assign rcvd_dword[CODE_ALIGNP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_ALIGNP] == phy_data_in_r;
assign rcvd_dword[CODE_XRDYP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_XRDYP ] == phy_data_in_r;
assign rcvd_dword[CODE_SOFP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_SOFP ] == phy_data_in_r;
assign rcvd_dword[CODE_HOLDAP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_HOLDAP] == phy_data_in_r;
assign rcvd_dword[CODE_HOLDP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_HOLDP ] == phy_data_in_r;
assign rcvd_dword[CODE_EOFP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_EOFP ] == phy_data_in_r;
assign rcvd_dword[CODE_WTRMP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_WTRMP ] == phy_data_in_r;
assign rcvd_dword[CODE_RRDYP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_RRDYP ] == phy_data_in_r;
assign rcvd_dword[CODE_IPP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_IPP ] == phy_data_in_r;
assign rcvd_dword[CODE_DMATP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_DMATP ] == phy_data_in_r;
assign rcvd_dword[CODE_OKP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_OKP ] == phy_data_in_r;
assign rcvd_dword[CODE_ERRP] = phy_isk_in_r[0] == 1'b1 & ~|phy_isk_in_r[DATA_BYTE_WIDTH-1:1] & prim_data[CODE_ERRP ] == phy_data_in_r;
// phy level errors handling TODO
assign dec_err = |phy_err_in;
assign dec_err = |phy_err_in_r;
// form a response to transport layer
assign frame_done = frame_done_good | frame_done_bad;
......@@ -586,7 +597,7 @@ assign frame_done_bad = state_wait & dword_val & rcvd_dword[CODE_ERRP];
always @ (posedge clk)
if (~|rcvd_dword & phy_ready)
begin
$display("%m: invalid primitive recieved : %h, conrol : %h, err : %h", phy_data_in, phy_isk_in, phy_err_in);
$display("%m: invalid primitive recieved : %h, conrol : %h, err : %h", phy_data_in_r, phy_isk_in_r, phy_err_in_r);
$finish;
end
// States checker
......
host/oob.v
View file @ 6dea1234
......@@ -29,6 +29,7 @@ module oob #(
parameter CLK_SPEED_GRADE = 1 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
)
(
output reg [11:0] debug,
// sata clk = usrclk2
input wire clk,
// reset oob
......@@ -426,5 +427,20 @@ assign eidle_timer_done = eidle_timer == 64;
always @ (posedge clk)
eidle_timer <= rst | rxelecidle | ~state_wait_eidle ? 8'b0 : eidle_timer + CLK_TO_TIMER_CONTRIB[7:0];
always @ (posedge clk)
debug <= rst ? 12'h000 : {
state_idle,
state_wait_cominit,
state_wait_comwake,
state_recal_tx,
state_wait_eidle,
state_wait_rxrst,
state_wait_align,
state_wait_synp,
state_wait_linkup,
state_error,
oob_start,
oob_error} | debug;
endmodule
host/oob_ctrl.v
View file @ 6dea1234
......@@ -30,6 +30,7 @@ module oob_ctrl #(
input wire rst,
// gtx is ready = all resets are done
input wire gtx_ready,
output wire [11:0] debug,
// oob responces
input wire rxcominitdet_in,
input wire rxcomwakedet_in,
......@@ -118,6 +119,7 @@ oob #(
)
oob
(
.debug (debug),
// sata clk = usrclk2
.clk (clk),
// reset oob
......
host/sata_host.v
View file @ 6dea1234
......@@ -29,6 +29,10 @@ module sata_host(
output wire rst,
// sata clk
output wire clk,
// reliable clock to source drp and cpll lock det circuits
input wire reliable_clk,
// temporary
input wire [31:0] al_cmd_in, // == {cmd_type, cmd_port, cmd_val, cmd_done_bad, cmd_done_good; cmd_busy}
input wire al_cmd_val_in,
......@@ -194,6 +198,12 @@ wire [15:0] sh_tran_cnt; // Transfer Count
wire sh_notif;
wire sh_autoact;
// phy is ready - link is established
wire phy_ready;
// tmp TODO
wire gtx_ready;
wire [11:0] debug_cnt;
assign sh_data_val_out = sh_data_val;
assign sh_data_out = sh_data;
assign sh_control_out = sh_control;
......@@ -218,6 +228,10 @@ assign sh_autoact_out = sh_autoact;
command command(
.rst (rst),
.clk (clk),
// temporary inputs TODO
.gtx_ready (gtx_ready),
.phy_ready (phy_ready),
.debug_cnt (debug_cnt),
// tl cmd iface
.cmd_type (cl2tl_cmd_type),
......@@ -560,8 +574,6 @@ transport transport(
// oob sequence is reinitiated and link now is not established or rxelecidle
//wire link_reset; // use ~phy_ready instead
// phy is ready - link is established
wire phy_ready;
// data-primitives stream from phy
wire [DATA_BYTE_WIDTH*8 - 1:0] phy2ll_data;
......@@ -657,8 +669,13 @@ sata_phy phy(
// sata clk, generated in pll as usrclk2
.clk (clk),
// stable clock to source drp and cpll lock det circuits
.reliable_clk (reliable_clk),
// state
.phy_ready (phy_ready),
.gtx_ready (gtx_ready),
.debug_cnt (debug_cnt),
// top-level ifaces
// ref clk from an external source, shall be connected to pads
......
host/sata_phy.v
View file @ 6dea1234
......@@ -30,8 +30,14 @@ module sata_phy #(
output wire clk,
output wire rst,
// reliable clock to source drp and cpll lock det circuits
input wire reliable_clk,
// state
output wire phy_ready,
// tmp output TODO
output wire gtx_ready,
output wire [11:0] debug_cnt,
// top-level ifaces
// ref clk from an external source, shall be connected to pads
......@@ -90,9 +96,9 @@ wire rxreset_oob;
wire rxelsfull;
wire rxelsempty;
wire gtx_ready;
//wire gtx_ready;
wire dummy;
oob_ctrl oob_ctrl(
// sata clk = usrclk2
.clk (clk),
......@@ -100,6 +106,7 @@ oob_ctrl oob_ctrl(
.rst (rst),
// gtx is ready = all resets are done
.gtx_ready (gtx_ready),
.debug ({dummy,debug_cnt[10:0]}),
// oob responces
.rxcominitdet_in (rxcominitdet),
.rxcomwakedet_in (rxcomwakedet),
......@@ -181,9 +188,26 @@ always @ (posedge gtrefclk)
*/
wire usrpll_locked;
// make tx/rxreset synchronous to gtrefclk - gather singals from different domains: async, aclk, usrclk2, gtrefclk
reg rxreset_f;
reg txreset_f;
reg rxreset_f_r;
reg txreset_f_r;
reg rxreset_f_rr;
reg txreset_f_rr;
always @ (posedge gtrefclk)
begin
rxreset_f <= ~cplllock | cpllreset | rxreset_oob & gtx_configured;
txreset_f <= ~cplllock | cpllreset;
txreset_f_r <= txreset_f;
rxreset_f_r <= rxreset_f;
txreset_f_rr <= txreset_f_r;
rxreset_f_rr <= rxreset_f_r;
end
assign rxreset = rxreset_f_rr;
assign txreset = txreset_f_rr;
assign cpllreset = extrst;
assign rxreset = ~cplllock | cpllreset | rxreset_oob & gtx_configured;
assign txreset = ~cplllock | cpllreset;
assign rxuserrdy = usrpll_locked & cplllock & ~cpllreset & ~rxreset & rxeyereset_done & sata_reset_done;
assign txuserrdy = usrpll_locked & cplllock & ~cpllreset & ~txreset & txpmareset_done & sata_reset_done;
......@@ -239,9 +263,11 @@ wire usrpll_fb_clk;
wire usrclk;
wire usrclk2;
assign txusrclk = usrclk;
wire usrclk_global;
BUFG bufg_usrclk (.O(usrclk_global),.I(usrclk));
assign txusrclk = usrclk_global;
assign txusrclk2 = usrclk2;
assign rxusrclk = usrclk;
assign rxusrclk = usrclk_global;
assign rxusrclk2 = usrclk2;
PLLE2_ADV #(
......@@ -330,6 +356,7 @@ gtx_wrap #(
)
gtx_wrap
(
.debug (debug_cnt[11]),
.cplllock (cplllock),
.cplllockdetclk (cplllockdetclk),
.cpllreset (cpllreset),
......@@ -370,8 +397,8 @@ gtx_wrap
/*
* Interfaces
*/
assign cplllockdetclk = gtrefclk; //TODO
assign drpclk = gtrefclk;
assign cplllockdetclk = reliable_clk; //gtrefclk;
assign drpclk = reliable_clk; //gtrefclk;
//assign clk = usrclk2;
BUFG bufg_sclk (.O(clk),.I(usrclk2));
......
tb/tb_top.v
View file @ 6dea1234
......@@ -85,8 +85,8 @@ reg SIMUL_AXI_FULL; // some data available
wire SIMUL_AXI_EMPTY;
reg [31:0] registered_rdata; // here read data from task
//reg CLK;
wire CLK;
reg CLK;
//wire CLK;
reg RST;
reg AR_SET_CMD_r;
wire AR_READY;
......@@ -174,12 +174,12 @@ wire #(AXI_TASK_HOLD) AW_SET_CMD = AW_SET_CMD_r;
wire #(AXI_TASK_HOLD) W_SET_CMD = W_SET_CMD_r;
//always #(CLKIN_PERIOD/2) CLK = ~CLK;
assign CLK = dut.axi_aclk;
//assign CLK = dut.axi_aclk;
/*
* connect axi ports to the dut
*/
assign dut.ps7_i.FCLKCLK= {4{EXTCLK_P}};
assign dut.ps7_i.FCLKCLK= {4{CLK}};
assign dut.ps7_i.FCLKRESETN= {RST,~RST,RST,~RST};
// Read address
assign dut.ps7_i.MAXIGP1ARADDR= araddr;
......
tb/test_top.v
View file @ 6dea1234
......@@ -30,6 +30,12 @@ begin
EXTCLK_N = ~EXTCLK_N;
end
// MAXI clock
always #10
begin
CLK = ~CLK;
end
integer i;
integer status;
integer id;
......@@ -37,7 +43,7 @@ reg [31:0] data;
// write registers
initial
begin
// CLK =1'b0;
CLK =1'b0;
RST = 1'bx;
AR_SET_CMD_r = 1'b0;
AW_SET_CMD_r = 1'b0;
......
top.xdc
View file @ 6dea1234
......@@ -7,3 +7,8 @@ set_property PACKAGE_PIN AA5 [get_ports RXN]
set_property PACKAGE_PIN AA6 [get_ports RXP]
set_property PACKAGE_PIN AB3 [get_ports TXN]
set_property PACKAGE_PIN AB4 [get_ports TXP]
# manually placing usrpll in the same region where gtx is located : x0y0
startgroup
place_cell sata_top/sata_host/phy/usrclk_pll PLLE2_ADV_X0Y0/PLLE2_ADV
endgroup
\ No newline at end of file
top_timing.xdc
View file @ 6dea1234
......@@ -8,6 +8,19 @@ create_clock -name gtrefclk -period 6.666 -waveform {0.000 3.333} [get_nets sata
# after plls inside of GTX:
create_clock -name txoutclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/sata_host/phy/txoutclk]
# recovered sata parallel clock
create_clock -name xclk -period 6.666 -waveform {0.000 3.333} [get_nets sata_top/sata_host/phy/gtx_wrap/xclk]
# txoutclk -> userpll, which gives us 2 clocks: userclk and userclk2. The second one is sata host clk
create_generated_clock -name usrclk [get_nets sata_top/sata_host/phy/CLK]
create_generated_clock -name sclk [get_nets sata_top/sata_host/phy/clk]
#create_generated_clock -name sclk [get_nets sata_top/sata_host/phy/clk]
create_generated_clock -name sclk [get_nets sata_top_n_173]
set_clock_groups -name async_clocks -asynchronous \
-group {gtrefclk} \
-group {axi_aclk0} \
-group {xclk} \
-group {usrclk} \
-group {sclk} \
-group {clk_axihp_pre} \
-group {txoutclk}
wrapper/GTXE2_GPL.v
View file @ 6dea1234
......@@ -2685,6 +2685,9 @@ module GTXE2_GPL(
input QPLLCLK,
input QPLLREFCLK,
// dunno
input RXDFEVSEN,
// Diffpairs
input GTXRXP,
input GTXRXN,
......
wrapper/gtxe2_channel_wrapper.v
View file @ 6dea1234
......@@ -986,6 +986,8 @@ gtx_unisims(
.RXDFELFOVRDEN (RXDFELFOVRDEN),
.RXDFEUTHOLD (RXDFEUTHOLD),
.RXDFEUTOVRDEN (RXDFEUTOVRDEN),
// this signal shall be present only in GTH, but for some reason it's included in unisims gtxe2
.RXDFEVSEN (1'b0),
.RXDFEVPHOLD (RXDFEVPHOLD),
.RXDFEVPOVRDEN (RXDFEVPOVRDEN),
.RXDFETAP2HOLD (RXDFETAP2HOLD),
......
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