Synthesisable version with passed oob (6dea1234) · Commits · Elphel / x393_sata

.settings/com.elphel.vdt.FPGA_project.prefs

+3 −1

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		FPGA_project_0_SimulationTopFile=tb/tb_top.v
		FPGA_project_1_SimulationTopModule=tb
		FPGA_project_2_ImplementationTopFile=dma/top.v
		FPGA_project_3_ImplementationTopModule=top
		FPGA_project_4_part=xc7z030fbg484-1
		com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->
		FPGA_project_5_part=xc7z030fbg484-1
		com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_3_ImplementationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->
		eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoBitstream.prefs

+2 −1

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		VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
		VivadoBitstream_105_force=true
		com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->
		VivadoBitstream_125_force=true
		com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->
		eclipse.preferences.version=1

.settings/com.elphel.vdt.VivadoSynthesis.prefs

+2 −1

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		VivadoSynthesis_101_MaxMsg=10000
		VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
		VivadoSynthesis_115_flatten_hierarchy=none
		VivadoSynthesis_122_ConstraintsFiles=top_timing.xdc<-@\#\#@->top.xdc<-@\#\#@->
		VivadoSynthesis_127_verbose=true
		VivadoSynthesis_81_parser_mode=1
		VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
		VivadoSynthesis_95_ShowInfo=false
		com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
		com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->
		eclipse.preferences.version=1

dma/dma_regs.v

+1 −1

Original line number	Diff line number	Diff line
		@@ -166,7 +166,7 @@ begin
		reg04 <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf1) ? wdata : reg04;
		reg08 <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf2) ? wdata : reg08;
		reg0c <= rst ? 32'h0 : bram_wen & (bram_waddr[7:0] == 8'hf3) ? wdata : reg0c;
		reg10 <= rst ? 32'h0 : dma_start_aclk ? 32'h0 : dma_done_aclk ? 32'hffffffff : reg10; // status reg
		reg10 <= rst ? 32'h0 : dma_start_aclk ? 32'h0 : {31'h0, dma_done_aclk} ? 32'hffffffff : reg10; // status reg
		reg14 <= rst ? 32'h0 : dma_done_aclk ? reg00 : reg14;
		end

dma/sata_top.v

+17 −10

Original line number	Diff line number	Diff line
		@@ -32,6 +32,12 @@
		output wire sclk,
		output wire sata_rst,
		input wire extrst,

		// reliable clock to source drp and cpll lock det circuits
		input wire reliable_clk,

		input wire hclk,

		/*
		* Commands interface
		*/
		@@ -228,7 +234,7 @@ wire dma_type;
		wire dma_start;
		wire dma_done;
		// axi-hp clock
		wire hclk;
		//wire hclk;
		// dma_control <-> dma_adapter command iface
		wire adp_busy;
		wire [31:7] adp_addr;
		@@ -279,10 +285,9 @@ wire [63:0] buf_rdata;
		wire rdata_done; // = membridge.is_last_in_page & membridge.afi_rready;

		//assign rst = ARESETN;

		// TODO
		assign hclk = ACLK;

		reg hrst;
		always @ (posedge hclk)
		hrst <= sata_rst;

		axi_regs axi_regs(
		// axi iface
		@@ -333,7 +338,7 @@ axi_regs axi_regs(
		* Programmable sata controller registers
		*/
		dma_regs dma_regs(
		.rst (sata_rst),
		.rst (ARESETN),
		.ACLK (ACLK),
		.sclk (sclk),
		// control iface
		@@ -473,7 +478,7 @@ dma_control dma_control(

		dma_adapter dma_adapter(
		.clk (hclk),
		.rst (sata_rst),
		.rst (hrst),
		// command iface
		.cmd_type (adp_type),
		.cmd_val (adp_val),
		@@ -526,9 +531,9 @@ V .MEMBRIDGE_ADDR (),
		.FRAME_HEIGHT_BITS (),
		.FRAME_WIDTH_BITS ()
		)*/ membridge(
		.mrst (sata_rst), // input
		.hrst (ARESETN), // input
		.mclk (hclk), // input
		.mrst (hrst), // input
		.hrst (hrst), // input
		.mclk (sclk), // input
		.hclk (hclk), // input
		.cmd_ad (cmd_ad),
		.cmd_stb (cmd_stb),
		@@ -605,6 +610,8 @@ sata_host sata_host(
		.rst (sata_rst),
		// sata clk
		.clk (sclk),
		// reliable clock to source drp and cpll lock det circuits
		.reliable_clk (reliable_clk),
		// temporary
		.al_cmd_in (cmd_out), // == {cmd_type, cmd_port, cmd_val, cmd_done_bad, cmd_done_good; cmd_busy}
		.al_cmd_val_in (cmd_val_out),

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