fighting synthesis obstacles (4c204cc3) · Commits · Elphel / x393_sata

dma/dma_adapter.v

+63 −12

Original line number	Diff line number	Diff line
		@@ -123,7 +123,8 @@ always @ (posedge clk)
		reg [3:0] rdwr_state;

		// Get data from buffer
		localparam READ_IDLE = 0;
		localparam IDLE = 0;
		//localparam READ_IDLE = 0;
		localparam READ_WAIT_ADDR = 3;
		localparam READ_DATA = 4;
		wire rd_reset_page;
		@@ -143,7 +144,7 @@ assign rd_data = buf_rdata;
		assign rd_val_out = rd_en;
		assign rd_data_out = rd_data;

		always @ (posedge clk)
		/*always @ (posedge clk)
		if (rst)
		begin
		rdwr_state <= READ_IDLE;
		@@ -187,10 +188,10 @@ always @ (posedge clk)
		rd_en <= 1'b0;
		end
		endcase

		*/

		// Put data into buffer
		localparam WRITE_IDLE = 0;
		//localparam WRITE_IDLE = 0;
		localparam WRITE_DATA = 1;
		localparam WRITE_WAIT_ADDR = 2;
		reg wr_en;
		@@ -215,6 +216,11 @@ assign wr_ack_out = wr_val_in & rdwr_state == WRITE_DATA;
		always @ (posedge clk)
		if (rst)
		begin
		rdwr_state <= IDLE;
		rd_done <= 1'b0;
		rd_data_count <= 7'h0;
		rd_next_page <= 1'b0;
		rd_en <= 1'b0;
		wr_done <= 1'b0;
		wr_data_count <= 7'd0;
		wr_val <= 1'b0;
		@@ -223,12 +229,16 @@ always @ (posedge clk)
		wr_reset_page <= 1'b0;
		wr_en <= 1'b0;
		wr_page_ready <= 1'b0;
		rdwr_state <= WRITE_IDLE;
		end
		else
		case (rdwr_state)
		WRITE_IDLE:
		IDLE:
		begin
		rdwr_state <= rd_start ? READ_WAIT_ADDR : wr_start ? WRITE_DATA : IDLE;
		rd_done <= 1'b0;
		rd_data_count <= 7'h0;
		rd_next_page <= 1'b0;
		rd_en <= 1'b0;
		wr_data_count <= 7'd0;
		wr_done <= 1'b0;
		wr_data <= 64'h0;
		@@ -236,30 +246,67 @@ always @ (posedge clk)
		wr_reset_page <= wr_start ? 1'b1 : 1'b0;
		wr_en <= 1'b0;
		wr_page_ready <= 1'b0;
		rdwr_state <= wr_start ? WRITE_DATA : WRITE_IDLE;
		end
		WRITE_DATA:
		begin
		wr_done <= wr_stop & membr_state == WRITE_IDLE ? 1'b1 : 1'b0;
		wr_done <= wr_stop & membr_state == IDLE ? 1'b1 : 1'b0;
		wr_data_count <= wr_val_in ? wr_data_count + 1'b1 : wr_data_count;
		wr_data <= wr_data_in;
		wr_next_page <= wr_stop ? 1'b1 : 1'b0;
		wr_reset_page <= 1'b0;
		wr_en <= wr_val_in;
		wr_page_ready <= wr_stop ? 1'b1 : 1'b0;
		rdwr_state <= wr_stop & membr_state == WRITE_IDLE ? WRITE_IDLE :
		rdwr_state <= wr_stop & membr_state == IDLE ? IDLE :
		wr_stop ? WRITE_WAIT_ADDR : WRITE_DATA;
		rd_done <= 1'b0;
		rd_data_count <= 7'h0;
		rd_next_page <= 1'b0;
		rd_en <= 1'b0;
		end
		WRITE_WAIT_ADDR: // in case all data is written into a buffer, but address is still being issued on axi bus
		begin
		wr_done <= membr_state == WRITE_IDLE ? 1'b1 : 1'b0;
		wr_done <= membr_state == IDLE ? 1'b1 : 1'b0;
		wr_data_count <= 7'd0;
		wr_data <= 64'h0;
		wr_next_page <= 1'b0;
		wr_reset_page <= 1'b0;
		wr_en <= 1'b0;
		wr_page_ready <= 1'b0;
		rdwr_state <= membr_state == IDLE ? IDLE : WRITE_WAIT_ADDR;
		rd_done <= 1'b0;
		rd_data_count <= 7'h0;
		rd_next_page <= 1'b0;
		rd_en <= 1'b0;
		end
		READ_WAIT_ADDR: // wait until address information is sent to the bus and input buffer got data
		begin
		rdwr_state <= membr_state == IDLE & rdata_done ? READ_DATA : READ_WAIT_ADDR;
		rd_done <= 1'b0;
		rd_data_count <= 7'h0;
		rd_next_page <= 1'b0;
		rd_en <= 1'b0;
		wr_done <= 1'b0;
		wr_data_count <= 7'd0;
		wr_data <= 64'h0;
		wr_next_page <= 1'b0;
		wr_reset_page <= 1'b0;
		wr_en <= 1'b0;
		wr_page_ready <= 1'b0;
		end
		READ_DATA:
		begin
		rdwr_state <= rd_stop ? IDLE : READ_DATA;
		rd_done <= rd_stop ? 1'b1 : 1'b0;
		rd_data_count <= rd_ack_in ? rd_data_count + 1'b1 : rd_data_count;
		rd_next_page <= rd_stop ? 1'b1 : 1'b0;
		rd_en <= rd_ack_in ? 1'b1 : 1'b0;
		wr_done <= 1'b0;
		wr_data_count <= 7'd0;
		wr_data <= 64'h0;
		wr_next_page <= 1'b0;
		wr_reset_page <= 1'b0;
		wr_en <= 1'b0;
		wr_page_ready <= 1'b0;
		rdwr_state <= membr_state == WRITE_IDLE ? WRITE_IDLE : WRITE_WAIT_ADDR;
		end
		default: // read is executed
		begin
		@@ -270,7 +317,11 @@ always @ (posedge clk)
		wr_reset_page <= 1'b0;
		wr_en <= 1'b0;
		wr_page_ready <= 1'b0;
		rdwr_state <= rdwr_state;
		rdwr_state <= IDLE;
		rd_done <= 1'b0;
		rd_data_count <= 7'h0;
		rd_next_page <= 1'b0;
		rd_en <= 1'b0;
		end
		endcase

dma/top.v

+2 −1

Original line number	Diff line number	Diff line
		@@ -133,7 +133,8 @@ always @(posedge comb_rst or posedge axi_aclk0) begin
		else axi_rst_pre <= 1'b0;
		end

		BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(/fclk[0]/ sclk));
		//BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(/fclk[0]/ sclk));
		assign axi_aclk = sclk;
		BUFG bufg_axi_aclk0_i (.O(axi_aclk0),.I(fclk[0]));
		BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
		BUFG bufg_extrst_i (.O(extrst),.I(axi_rst_pre));

host/gtx_comma_align.v

+2 −2

Original line number	Diff line number	Diff line
		@@ -114,8 +114,8 @@ assign ored_subwindow[0] = {20{comma_match_prev[0]}} & subwindow[0];
		generate
		for (ii = 1; ii < 20; ii = ii + 1)
		begin: or_all_possible_windows
		assign ored_subwindow_comdet[ii] = {20{comma_match_p[ii]}} & comma_p \| {20{~comma_match_p[ii] & comma_match[ii]}} & comma_n \| ored_subwindow_comdet[ii-1];
		assign ored_subwindow[ii] = {20{comma_match_prev[ii]}} & subwindow[ii] \| ored_subwindow[ii-1];
		assign ored_subwindow_comdet[ii] = {20{comma_match_p[ii]}} & comma_p \| {20{~comma_match_p[ii] & comma_match[ii]}} & comma_n \| ored_subwindow_comdet[ii-1]; // SuppressThisWarning VEditor -warning would be fixed in future releases
		assign ored_subwindow[ii] = {20{comma_match_prev[ii]}} & subwindow[ii] \| ored_subwindow[ii-1]; // SuppressThisWarning VEditor -warning would be fixed in future releases
		end
		endgenerate

host/oob.v

+20 −16

Original line number	Diff line number	Diff line
		@@ -274,6 +274,10 @@ always @ (posedge clk)
		cominit_req_r <= (cominit_req_r \| cominit_req_set) & ~(cominit_allow & cominit_req) & ~rst;
		assign cominit_req = cominit_req_set \| cominit_req_r;

		// primitives
		wire [63:0] alignp = {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100, 8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100};
		wire [63:0] syncp = {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100, 8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100};

		// detect which primitives sends the device after comwake was done
		generate
		if (DATA_BYTE_WIDTH == 2)
		@@ -281,26 +285,26 @@ generate
		reg detected_alignp_f;
		always @ (posedge clk)
		detected_alignp_f <= rst \| ~state_wait_align ? 1'b0 :
		~\|(rxdata ^ {8'b01001010, 8'b10111100}) & ~\|(rxcharisk ^ 2'b01); // {D10.2, K28.5}
		assign detected_alignp = detected_alignp_f & ~\|(rxdata ^ {8'b01111011, 8'b01001010}) & ~\|(rxcharisk ^ 2'b00); // {D27.3, D10.2}
		~\|(rxdata[15:0] ^ alignp[15:0]) & ~\|(rxcharisk[1:0] ^ 2'b01); // {D10.2, K28.5}
		assign detected_alignp = detected_alignp_f & ~\|(rxdata[15:0] ^ alignp[31:16]) & ~\|(rxcharisk[1:0] ^ 2'b00); // {D27.3, D10.2} // SuppressThisWarning VEditor -warning would be fixed in future releases

		reg detected_syncp_f;
		always @ (posedge clk)
		detected_syncp_f <= rst \| ~state_wait_synp ? 1'b0 :
		~\|(rxdata ^ {8'b10010101, 8'b01111100}) & ~\|(rxcharisk ^ 2'b01); // {D21.4, K28.3}
		assign detected_syncp = detected_syncp_f & ~\|(rxdata ^ {8'b10110101, 8'b10110101}) & ~\|(rxcharisk ^ 2'b00); // {D21.5, D21.5}
		~\|(rxdata[15:0] ^ syncp[15:0]) & ~\|(rxcharisk[1:0] ^ 2'b01); // {D21.4, K28.3}
		assign detected_syncp = detected_syncp_f & ~\|(rxdata[15:0] ^ syncp[31:16]) & ~\|(rxcharisk[1:0] ^ 2'b00); // {D21.5, D21.5} // SuppressThisWarning VEditor -warning would be fixed in future releases
		end
		else
		if (DATA_BYTE_WIDTH == 4)
		begin
		assign detected_alignp = ~\|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~\|(rxcharisk ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5}
		assign detected_syncp = ~\|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~\|(rxcharisk ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3}
		assign detected_alignp = ~\|(rxdata[31:0] ^ alignp[31:0]) & ~\|(rxcharisk[3:0] ^ 4'h1); // {D27.3, D10.2, D10.2, K28.5} // SuppressThisWarning VEditor -warning would be fixed in future releases
		assign detected_syncp = ~\|(rxdata[31:0] ^ syncp[31:0]) & ~\|(rxcharisk[3:0] ^ 4'h1); // {D21.5, D21.5, D21.4, K28.3} // SuppressThisWarning VEditor -warning would be fixed in future releases
		end
		else
		if (DATA_BYTE_WIDTH == 8)
		begin
		assign detected_alignp = ~\|(rxdata ^ {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100, 8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}) & ~\|(rxcharisk ^ 8'h11); // {D27.3, D10.2, D10.2, K28.5}
		assign detected_syncp = ~\|(rxdata ^ {8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100, 8'b10110101, 8'b10110101, 8'b10010101, 8'b01111100}) & ~\|(rxcharisk ^ 8'h11); // {D21.5, D21.5, D21.4, K28.3}
		assign detected_alignp = ~\|(rxdata[63:0] ^ alignp[63:0]) & ~\|(rxcharisk[7:0] ^ 8'h11); // {D27.3, D10.2, D10.2, K28.5} // SuppressThisWarning VEditor -warning would be fixed in future releases
		assign detected_syncp = ~\|(rxdata[63:0] ^ syncp[63:0]) & ~\|(rxcharisk[7:0] ^ 8'h11); // {D21.5, D21.5, D21.4, K28.3} // SuppressThisWarning VEditor -warning would be fixed in future releases
		end
		else
		begin
		@@ -357,7 +361,7 @@ end

		// Continious D10.2 primitive
		assign txcharisk_d102 = {DATA_BYTE_WIDTH{1'b0}};
		assign txdata_d102 = {DATA_BYTE_WIDTH{8'b01001010}};
		assign txdata_d102 = {DATA_BYTE_WIDTH{8'b01001010}}; // SuppressThisWarning VEditor -warning would be fixed in future releases

		// Align primitive: K28.5 + D10.2 + D10.2 + D27.3
		generate
		@@ -367,21 +371,21 @@ generate
		always @ (posedge clk)
		align_odd <= rst \| ~state_wait_synp ? 1'b0 : ~align_odd;

		assign txcharisk_align = align_odd ? 2'b01 : 2'b00;
		assign txdata_align = align_odd ? {8'b01001010, 8'b10111100} : // {D10.2, K28.5}
		{8'b01111011, 8'b01001010}; // {D27.3, D10.2}
		assign txcharisk_align[DATA_BYTE_WIDTH - 1:0] = align_odd ? 2'b01 : 2'b00; // SuppressThisWarning VEditor -warning would be fixed in future releases
		assign txdata_align[DATA_BYTE_WIDTH*8 - 1:0] = align_odd ? alignp[15:0] : // {D10.2, K28.5} // SuppressThisWarning VEditor -warning would be fixed in future releases
		alignp[31:16]; // {D27.3, D10.2} // SuppressThisWarning VEditor -warning would be fixed in future releases
		end
		else
		if (DATA_BYTE_WIDTH == 4)
		begin
		assign txcharisk_align = 4'h1;
		assign txdata_align = {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}; // {D27.3, D10.2, D10.2, K28.5}
		assign txcharisk_align[DATA_BYTE_WIDTH - 1:0] = 4'h1;
		assign txdata_align[DATA_BYTE_WIDTH8 - 1:0] = alignp[DATA_BYTE_WIDTH8 - 1:0]; // {D27.3, D10.2, D10.2, K28.5}
		end
		else
		if (DATA_BYTE_WIDTH == 8)
		begin
		assign txcharisk_align = 8'h11;
		assign txdata_align = {8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100, 8'b01111011, 8'b01001010, 8'b01001010, 8'b10111100}; // 2x{D27.3, D10.2, D10.2, K28.5}
		assign txcharisk_align[DATA_BYTE_WIDTH - 1:0] = 8'h11; // SuppressThisWarning VEditor -warning would be fixed in future releases
		assign txdata_align[DATA_BYTE_WIDTH8 - 1:0] = alignp[DATA_BYTE_WIDTH8 - 1:0]; // 2x{D27.3, D10.2, D10.2, K28.5}
		end
		else
		always @ (posedge clk)

host/sata_phy.v

+2 −1

Original line number	Diff line number	Diff line
		@@ -373,7 +373,8 @@ gtx_wrap
		assign cplllockdetclk = gtrefclk; //TODO
		assign drpclk = gtrefclk;

		assign clk = usrclk2;
		//assign clk = usrclk2;
		BUFG bufg_sclk (.O(clk),.I(usrclk2));
		assign rxn = rxn_in;
		assign rxp = rxp_in;
		assign txn_out = txn;

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