started hardware testing (57b218aa) · Commits · Elphel / x393_sata

.project

+17 −17

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	@@ -52,87 +52,87 @@
	<link>		<link>
	<name>vivado_logs/VivadoBitstream.log</name>		<name>vivado_logs/VivadoBitstream.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160130001427345.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160201011135425.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOpt.log</name>		<name>vivado_logs/VivadoOpt.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160130001427345.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160201011135425.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPhys.log</name>		<name>vivado_logs/VivadoOptPhys.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160130001427345.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160201011135425.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPower.log</name>		<name>vivado_logs/VivadoOptPower.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160130001427345.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160201011135425.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoPlace.log</name>		<name>vivado_logs/VivadoPlace.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160130001427345.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160201011135425.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoRoute.log</name>		<name>vivado_logs/VivadoRoute.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160130001427345.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160201011135425.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoSynthesis.log</name>		<name>vivado_logs/VivadoSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160130150815853.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160201011135425.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160130001427345.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160201011135425.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160130150815853.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160201011135425.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportImplemented.log</name>		<name>vivado_logs/VivadoTimingReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160130001427345.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160201011135425.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportSynthesis.log</name>		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160130150815853.log</location>		<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160201011135425.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt-phys.dcp</name>		<name>vivado_state/x393_sata-opt-phys.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160130001427345.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160201011135425.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt-power.dcp</name>		<name>vivado_state/x393_sata-opt-power.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160130001427345.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160201011135425.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-opt.dcp</name>		<name>vivado_state/x393_sata-opt.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160130001427345.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160201011135425.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-place.dcp</name>		<name>vivado_state/x393_sata-place.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160130001427345.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160201011135425.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-route.dcp</name>		<name>vivado_state/x393_sata-route.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160130001427345.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160201011135425.dcp</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393_sata-synth.dcp</name>		<name>vivado_state/x393_sata-synth.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160130150815853.dcp</location>		<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160201011135425.dcp</location>
	</link>		</link>
	</linkedResources>		</linkedResources>
	</projectDescription>		</projectDescription>

.pydevproject

0 → 100644

+5 −0

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			<?xml version="1.0" encoding="UTF-8" standalone="no"?>
			<?eclipse-pydev version="1.0"?><pydev_project>
			<pydev_property name="org.python.pydev.PYTHON_PROJECT_INTERPRETER">Default</pydev_property>
			<pydev_property name="org.python.pydev.PYTHON_PROJECT_VERSION">python 2.7</pydev_property>
			</pydev_project>

.settings/com.elphel.vdt.VivadoBitstream.prefs

+2 −1

Original line number	Original line	Diff line number	Diff line
	VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->		VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
	VivadoBitstream_105_force=true		VivadoBitstream_105_force=true
			VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
	VivadoBitstream_124_force=true		VivadoBitstream_124_force=true
	VivadoBitstream_125_force=true		VivadoBitstream_125_force=true
	com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->		com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->
	eclipse.preferences.version=1		eclipse.preferences.version=1

ahci/ahci_fsm.v

+4 −1

ahci/ahci_sata_layers.v

+15 −5

Original line number	Original line	Diff line number	Diff line
	@@ -90,7 +90,10 @@ module ahci_sata_layers #(
	output wire txp_out,		output wire txp_out,
	output wire txn_out,		output wire txn_out,
	input wire rxp_in,		input wire rxp_in,
	input wire rxn_in		input wire rxn_in,

			output [31:0] debug_sata

	);		);
	localparam PHY_SPEED = 2; // SATA2		localparam PHY_SPEED = 2; // SATA2
	localparam FIFO_ADDR_WIDTH = 9;		localparam FIFO_ADDR_WIDTH = 9;
	@@ -183,9 +186,9 @@ module ahci_sata_layers #(
	assign serr_DH = phy_ready && (xmit_err);		assign serr_DH = phy_ready && (xmit_err);

	// not yet assigned errors		// not yet assigned errors
	assign serr_DT = phy_ready && (0); // RWC: Transport state transition error		assign serr_DT = phy_ready && (comreset_send); // RWC: Transport state transition error
	assign serr_DS = phy_ready && (0); // RWC: Link sequence error		assign serr_DS = phy_ready && (cominit_got); // RWC: Link sequence error
	assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer		assign serr_DC = phy_ready && (serr_DW); // RWC: CRC error in Link layer
	// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error		// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
	assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error		assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error
	assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected		assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected
	@@ -194,6 +197,9 @@ module ahci_sata_layers #(
	assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established		assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established
	assign serr_EI = phy_ready && (0); // RWC: Recovered Data integrity Error		assign serr_EI = phy_ready && (0); // RWC: Recovered Data integrity Error

			// .comreset_send (comreset_send), // input
			// .cominit_got (cominit_got), // output wire
			// .comwake_got (serr_DW), // output wire



	@@ -295,7 +301,11 @@ module ahci_sata_layers #(
	.set_offline (set_offline), // input		.set_offline (set_offline), // input
	.comreset_send (comreset_send), // input		.comreset_send (comreset_send), // input
	.cominit_got (cominit_got), // output wire		.cominit_got (cominit_got), // output wire
	.comwake_got (serr_DW) // output wire		.comwake_got (serr_DW), // output wire
			.cplllock_debug (),
			.usrpll_locked_debug(),
			.debug_sata (debug_sata)


	);		);

Original line number	Original line	Diff line number	Diff line
	@@ -233,7 +233,8 @@ module ahci_fsm
	input ch_r, // reset - may need to send SYNC escape before this command		input ch_r, // reset - may need to send SYNC escape before this command
	input ch_p, // prefetchable - only used with non-zero PRDTL or ATAPI bit set		input ch_p, // prefetchable - only used with non-zero PRDTL or ATAPI bit set
	input ch_w, // Write: system memory -> device		input ch_w, // Write: system memory -> device
	input ch_a // ATAPI: 1 means device should send PIO setup FIS for ATAPI command		input ch_a, // ATAPI: 1 means device should send PIO setup FIS for ATAPI command
			output reg [ 9:0] last_jump_addr // debug feature
	/// input [4:0] ch_cfl, // length of the command FIS in DW, 0 means none. 0 and 1 - illegal,		/// input [4:0] ch_cfl, // length of the command FIS in DW, 0 means none. 0 and 1 - illegal,
	// maximal is 16 (0x10)		// maximal is 16 (0x10)
	/// input [11:0] dwords_sent // number of DWORDs transmitted (up to 2048)		/// input [11:0] dwords_sent // number of DWORDs transmitted (up to 2048)
	@@ -330,6 +331,8 @@ module ahci_fsm
	if (fsm_jump[0]) pgm_addr <= pgm_jump_addr;		if (fsm_jump[0]) pgm_addr <= pgm_jump_addr;
	else if (fsm_next) pgm_addr <= pgm_addr + 1;		else if (fsm_next) pgm_addr <= pgm_addr + 1;

			if (fsm_jump[0]) last_jump_addr <= pgm_jump_addr; // debug feature

	// if (hba_rst) conditions <= 0;		// if (hba_rst) conditions <= 0;
	// if (fsm_transitions[0]) conditions <= precond_w;		// if (fsm_transitions[0]) conditions <= precond_w;

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