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Elphel
x393_sata
Commits
57b218aa
Commit
57b218aa
authored
Feb 01, 2016
by
Andrey Filippov
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started hardware testing
parent
f1b706b5
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1212 additions
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83 deletions
+1212
-83
.project
.project
+17
-17
.pydevproject
.pydevproject
+5
-0
com.elphel.vdt.VivadoBitstream.prefs
.settings/com.elphel.vdt.VivadoBitstream.prefs
+2
-1
ahci_fsm.v
ahci/ahci_fsm.v
+4
-1
ahci_sata_layers.v
ahci/ahci_sata_layers.v
+15
-5
ahci_top.v
ahci/ahci_top.v
+9
-6
axi_ahci_regs.v
ahci/axi_ahci_regs.v
+14
-7
sata_ahci_top.v
ahci/sata_ahci_top.v
+6
-2
create_ahci_registers.py
helpers/create_ahci_registers.py
+4
-3
sata_phy.v
host/sata_phy.v
+52
-6
ahci_defaults.vh
includes/ahci_defaults.vh
+1
-1
ahci_localparams.vh
includes/ahci_localparams.vh
+3
-3
ahci_types.vh
includes/ahci_types.vh
+1
-1
identify.dat
input_data/identify.dat
+32
-0
identify_hdd.dat
input_data/identify_hdd.dat
+32
-0
.project
py393sata/.project
+17
-0
.pydevproject
py393sata/.pydevproject
+8
-0
x393_mem.py
py393sata/x393_mem.py
+317
-0
x393_vsc3304.py
py393sata/x393_vsc3304.py
+183
-0
x393sata.py
py393sata/x393sata.py
+281
-0
tb_ahci.tf
tb/tb_ahci.tf
+12
-2
tb_ahci_01.sav
tb_ahci_01.sav
+185
-19
GTXE2_GPL.v
wrapper/GTXE2_GPL.v
+12
-9
No files found.
.project
View file @
57b218aa
...
@@ -52,87 +52,87 @@
...
@@ -52,87 +52,87 @@
<link>
<link>
<name>
vivado_logs/VivadoBitstream.log
</name>
<name>
vivado_logs/VivadoBitstream.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160
13000142734
5.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160
20101113542
5.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoOpt.log
</name>
<name>
vivado_logs/VivadoOpt.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160
13000142734
5.log
</location>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160
20101113542
5.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_logs/VivadoOptPhys.log
</name>
<name>
vivado_logs/VivadoOptPhys.log
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160
13000142734
5.log
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/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160
20101113542
5.log
</location>
</link>
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<link>
<link>
<name>
vivado_logs/VivadoOptPower.log
</name>
<name>
vivado_logs/VivadoOptPower.log
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1
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13000142734
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/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160
20101113542
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<link>
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13000142734
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20101113542
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<link>
<link>
<name>
vivado_logs/VivadoRoute.log
</name>
<name>
vivado_logs/VivadoRoute.log
</name>
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1
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/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160
13000142734
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20101113542
5.log
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<link>
<name>
vivado_logs/VivadoSynthesis.log
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<name>
vivado_logs/VivadoSynthesis.log
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/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160
130150815853
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201011135425
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13000142734
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130150815853
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201011135425
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vivado_logs/VivadoTimingReportImplemented.log
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13000142734
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20101113542
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130150815853
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/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160
201011135425
.log
</location>
</link>
</link>
<link>
<link>
<name>
vivado_state/x393_sata-opt-phys.dcp
</name>
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vivado_state/x393_sata-opt-phys.dcp
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/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160
13000142734
5.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160
20101113542
5.dcp
</location>
</link>
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<link>
<link>
<name>
vivado_state/x393_sata-opt-power.dcp
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vivado_state/x393_sata-opt-power.dcp
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/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160
13000142734
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<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160
20101113542
5.dcp
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vivado_state/x393_sata-opt.dcp
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vivado_state/x393_sata-opt.dcp
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/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160
13000142734
5.dcp
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<location>
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20101113542
5.dcp
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</link>
</link>
<link>
<link>
<name>
vivado_state/x393_sata-place.dcp
</name>
<name>
vivado_state/x393_sata-place.dcp
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<type>
1
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1
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<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160
13000142734
5.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160
20101113542
5.dcp
</location>
</link>
</link>
<link>
<link>
<name>
vivado_state/x393_sata-route.dcp
</name>
<name>
vivado_state/x393_sata-route.dcp
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160
13000142734
5.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160
20101113542
5.dcp
</location>
</link>
</link>
<link>
<link>
<name>
vivado_state/x393_sata-synth.dcp
</name>
<name>
vivado_state/x393_sata-synth.dcp
</name>
<type>
1
</type>
<type>
1
</type>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160
130150815853
.dcp
</location>
<location>
/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160
201011135425
.dcp
</location>
</link>
</link>
</linkedResources>
</linkedResources>
</projectDescription>
</projectDescription>
.pydevproject
0 → 100644
View file @
57b218aa
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?eclipse-pydev version="1.0"?>
<pydev_project>
<pydev_property
name=
"org.python.pydev.PYTHON_PROJECT_INTERPRETER"
>
Default
</pydev_property>
<pydev_property
name=
"org.python.pydev.PYTHON_PROJECT_VERSION"
>
python 2.7
</pydev_property>
</pydev_project>
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @
57b218aa
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
VivadoBitstream_105_force=true
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true
VivadoBitstream_124_force=true
VivadoBitstream_125_force=true
VivadoBitstream_125_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->
VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->
eclipse.preferences.version=1
eclipse.preferences.version=1
ahci/ahci_fsm.v
View file @
57b218aa
...
@@ -233,7 +233,8 @@ module ahci_fsm
...
@@ -233,7 +233,8 @@ module ahci_fsm
input
ch_r
,
// reset - may need to send SYNC escape before this command
input
ch_r
,
// reset - may need to send SYNC escape before this command
input
ch_p
,
// prefetchable - only used with non-zero PRDTL or ATAPI bit set
input
ch_p
,
// prefetchable - only used with non-zero PRDTL or ATAPI bit set
input
ch_w
,
// Write: system memory -> device
input
ch_w
,
// Write: system memory -> device
input
ch_a
// ATAPI: 1 means device should send PIO setup FIS for ATAPI command
input
ch_a
,
// ATAPI: 1 means device should send PIO setup FIS for ATAPI command
output
reg
[
9
:
0
]
last_jump_addr
// debug feature
/// input [4:0] ch_cfl, // length of the command FIS in DW, 0 means none. 0 and 1 - illegal,
/// input [4:0] ch_cfl, // length of the command FIS in DW, 0 means none. 0 and 1 - illegal,
// maximal is 16 (0x10)
// maximal is 16 (0x10)
/// input [11:0] dwords_sent // number of DWORDs transmitted (up to 2048)
/// input [11:0] dwords_sent // number of DWORDs transmitted (up to 2048)
...
@@ -330,6 +331,8 @@ module ahci_fsm
...
@@ -330,6 +331,8 @@ module ahci_fsm
if
(
fsm_jump
[
0
])
pgm_addr
<=
pgm_jump_addr
;
if
(
fsm_jump
[
0
])
pgm_addr
<=
pgm_jump_addr
;
else
if
(
fsm_next
)
pgm_addr
<=
pgm_addr
+
1
;
else
if
(
fsm_next
)
pgm_addr
<=
pgm_addr
+
1
;
if
(
fsm_jump
[
0
])
last_jump_addr
<=
pgm_jump_addr
;
// debug feature
// if (hba_rst) conditions <= 0;
// if (hba_rst) conditions <= 0;
// if (fsm_transitions[0]) conditions <= precond_w;
// if (fsm_transitions[0]) conditions <= precond_w;
...
...
ahci/ahci_sata_layers.v
View file @
57b218aa
...
@@ -90,7 +90,10 @@ module ahci_sata_layers #(
...
@@ -90,7 +90,10 @@ module ahci_sata_layers #(
output
wire
txp_out
,
output
wire
txp_out
,
output
wire
txn_out
,
output
wire
txn_out
,
input
wire
rxp_in
,
input
wire
rxp_in
,
input
wire
rxn_in
input
wire
rxn_in
,
output
[
31
:
0
]
debug_sata
)
;
)
;
localparam
PHY_SPEED
=
2
;
// SATA2
localparam
PHY_SPEED
=
2
;
// SATA2
localparam
FIFO_ADDR_WIDTH
=
9
;
localparam
FIFO_ADDR_WIDTH
=
9
;
...
@@ -183,9 +186,9 @@ module ahci_sata_layers #(
...
@@ -183,9 +186,9 @@ module ahci_sata_layers #(
assign
serr_DH
=
phy_ready
&&
(
xmit_err
)
;
assign
serr_DH
=
phy_ready
&&
(
xmit_err
)
;
// not yet assigned errors
// not yet assigned errors
assign
serr_DT
=
phy_ready
&&
(
0
)
;
// RWC: Transport state transition error
assign
serr_DT
=
phy_ready
&&
(
comreset_send
)
;
// RWC: Transport state transition error
assign
serr_DS
=
phy_ready
&&
(
0
)
;
// RWC: Link sequence error
assign
serr_DS
=
phy_ready
&&
(
cominit_got
)
;
// RWC: Link sequence error
assign
serr_DC
=
phy_ready
&&
(
0
)
;
// RWC: CRC error in Link layer
assign
serr_DC
=
phy_ready
&&
(
serr_DW
)
;
// RWC: CRC error in Link layer
// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
assign
serr_DI
=
phy_ready
&&
(
0
)
;
// RWC: PHY Internal Error
assign
serr_DI
=
phy_ready
&&
(
0
)
;
// RWC: PHY Internal Error
assign
serr_EP
=
phy_ready
&&
(
0
)
;
// RWC: Protocol Error - a violation of SATA protocol detected
assign
serr_EP
=
phy_ready
&&
(
0
)
;
// RWC: Protocol Error - a violation of SATA protocol detected
...
@@ -194,6 +197,9 @@ module ahci_sata_layers #(
...
@@ -194,6 +197,9 @@ module ahci_sata_layers #(
assign
serr_EM
=
phy_ready
&&
(
0
)
;
// RWC: Communication between the device and host was lost but re-established
assign
serr_EM
=
phy_ready
&&
(
0
)
;
// RWC: Communication between the device and host was lost but re-established
assign
serr_EI
=
phy_ready
&&
(
0
)
;
// RWC: Recovered Data integrity Error
assign
serr_EI
=
phy_ready
&&
(
0
)
;
// RWC: Recovered Data integrity Error
// .comreset_send (comreset_send), // input
// .cominit_got (cominit_got), // output wire
// .comwake_got (serr_DW), // output wire
...
@@ -295,7 +301,11 @@ module ahci_sata_layers #(
...
@@ -295,7 +301,11 @@ module ahci_sata_layers #(
.
set_offline
(
set_offline
)
,
// input
.
set_offline
(
set_offline
)
,
// input
.
comreset_send
(
comreset_send
)
,
// input
.
comreset_send
(
comreset_send
)
,
// input
.
cominit_got
(
cominit_got
)
,
// output wire
.
cominit_got
(
cominit_got
)
,
// output wire
.
comwake_got
(
serr_DW
)
// output wire
.
comwake_got
(
serr_DW
)
,
// output wire
.
cplllock_debug
()
,
.
usrpll_locked_debug
()
,
.
debug_sata
(
debug_sata
)
)
;
)
;
...
...
ahci/ahci_top.v
View file @
57b218aa
...
@@ -181,7 +181,10 @@ module ahci_top#(
...
@@ -181,7 +181,10 @@ module ahci_top#(
output
irq
// CPU interrupt request
output
irq
,
// CPU interrupt request
input
[
31
:
0
]
debug_in
)
;
)
;
// axi_ahci_regs signals:
// axi_ahci_regs signals:
...
@@ -436,6 +439,7 @@ module ahci_top#(
...
@@ -436,6 +439,7 @@ module ahci_top#(
wire
pxci0_clear
;
// PxCI clear
wire
pxci0_clear
;
// PxCI clear
wire
pxci0
;
// pxCI current value
wire
pxci0
;
// pxCI current value
wire
[
9
:
0
]
last_jump_addr
;
// Async FF
// Async FF
always
@
(
posedge
mrst
or
posedge
mclk
)
begin
always
@
(
posedge
mrst
or
posedge
mclk
)
begin
if
(
mrst
)
en_port
<=
0
;
if
(
mrst
)
en_port
<=
0
;
...
@@ -620,9 +624,10 @@ module ahci_top#(
...
@@ -620,9 +624,10 @@ module ahci_top#(
.
ch_r
(
fsnd_ch_r
)
,
// input
.
ch_r
(
fsnd_ch_r
)
,
// input
.
ch_p
(
fsnd_ch_p
)
,
// input
.
ch_p
(
fsnd_ch_p
)
,
// input
.
ch_w
(
fsnd_ch_w
)
,
// input
.
ch_w
(
fsnd_ch_w
)
,
// input
.
ch_a
(
fsnd_ch_a
)
// input
.
ch_a
(
fsnd_ch_a
)
,
// input
/// .ch_cfl (fsnd_ch_cfl), // input[4:0]
/// .ch_cfl (fsnd_ch_cfl), // input[4:0]
/// .dwords_sent (data_out_dwords) // input[11:0] ????
/// .dwords_sent (data_out_dwords) // input[11:0] ????
.
last_jump_addr
(
last_jump_addr
)
)
;
)
;
...
@@ -684,11 +689,9 @@ module ahci_top#(
...
@@ -684,11 +689,9 @@ module ahci_top#(
.
afi_rcache
(
axi_rd_cache_mode
)
,
// output[3:0] reg
.
afi_rcache
(
axi_rd_cache_mode
)
,
// output[3:0] reg
.
afi_cache_set
(
set_axi_cache_mode
)
,
// output
.
afi_cache_set
(
set_axi_cache_mode
)
,
// output
.
was_hba_rst
(
was_hba_rst
)
,
// output
.
was_hba_rst
(
was_hba_rst
)
,
// output
.
was_port_rst
(
was_port_rst
)
// output
.
was_port_rst
(
was_port_rst
)
,
// output
.
debug_in
(
{
2'b0
,
last_jump_addr
[
9
:
0
]
,
debug_in
[
19
:
0
]
}
)
)
;
)
;
ahci_ctrl_stat
#(
ahci_ctrl_stat
#(
.
ADDRESS_BITS
(
ADDRESS_BITS
)
.
ADDRESS_BITS
(
ADDRESS_BITS
)
)
ahci_ctrl_stat_i
(
)
ahci_ctrl_stat_i
(
...
...
ahci/axi_ahci_regs.v
View file @
57b218aa
...
@@ -90,7 +90,7 @@ module axi_ahci_regs#(
...
@@ -90,7 +90,7 @@ module axi_ahci_regs#(
// Apply next 2 resets and arst OR-ed to SATA.extrst
// Apply next 2 resets and arst OR-ed to SATA.extrst
output
hba_arst
,
// hba async reset (currently does ~ the same as port reset)
output
hba_arst
,
// hba async reset (currently does ~ the same as port reset)
output
port_arst
,
// port0 async reset by software
output
port_arst
,
// port0 async reset by software
output
port_arst_any
,
// port0 async reset by POR or software
output
port_arst_any
,
// port0 async reset by POR or software
// 2. HBA R/W registers, use hba clock
// 2. HBA R/W registers, use hba clock
input
hba_clk
,
// SATA clock, now 75MHz
input
hba_clk
,
// SATA clock, now 75MHz
...
@@ -114,7 +114,8 @@ module axi_ahci_regs#(
...
@@ -114,7 +114,8 @@ module axi_ahci_regs#(
output
reg
[
3
:
0
]
afi_rcache
,
output
reg
[
3
:
0
]
afi_rcache
,
output
afi_cache_set
,
output
afi_cache_set
,
output
was_hba_rst
,
// last reset was hba reset (not counting system reset)
output
was_hba_rst
,
// last reset was hba reset (not counting system reset)
output
was_port_rst
// last reset was port reset
output
was_port_rst
,
// last reset was port reset
input
[
31
:
0
]
debug_in
)
;
)
;
`include
"includes/ahci_localparams.vh"
// @SuppressThisWarning VEditor : Unused localparams
`include
"includes/ahci_localparams.vh"
// @SuppressThisWarning VEditor : Unused localparams
...
@@ -175,8 +176,9 @@ module axi_ahci_regs#(
...
@@ -175,8 +176,9 @@ module axi_ahci_regs#(
wire
pgm_fsm_and_w
=
|
(
ahci_regs_di
&
HBA_PORT__PGM_AHCI_SM__AnD__MASK
)
;
wire
pgm_fsm_and_w
=
|
(
ahci_regs_di
&
HBA_PORT__PGM_AHCI_SM__AnD__MASK
)
;
wire
set_hba_rst
=
bram_wen_r
&&
!
high_sel
&&
(
bram_addr
==
GHC__GHC__HR__ADDR
)
&&
(
ahci_regs_di
&
GHC__GHC__HR__MASK
)
;
wire
set_hba_rst
=
bram_wen_r
&&
!
high_sel
&&
(
bram_addr
==
GHC__GHC__HR__ADDR
)
&&
(
ahci_regs_di
&
GHC__GHC__HR__MASK
)
;
localparam
HBA_PORT__PxSCTL__DET__MASK01
=
HBA_PORT__PxSCTL__DET__MASK
&
~
1
;
// == 'he
wire
set_port_rst
=
bram_wen_r
&&
!
high_sel
&&
(
bram_addr
==
HBA_PORT__PxSCTL__DET__ADDR
)
&&
wire
set_port_rst
=
bram_wen_r
&&
!
high_sel
&&
(
bram_addr
==
HBA_PORT__PxSCTL__DET__ADDR
)
&&
((
ahci_regs_di
&
HBA_PORT__PxSCTL__DET__MASK
|
1
)
==
HBA_PORT__PxSCTL__DET__MASK
)
;
// writing only 0/1
((
ahci_regs_di
&
HBA_PORT__PxSCTL__DET__MASK
01
)
==
0
)
;
// writing only 0/1
// in lower 4 bits
// in lower 4 bits
wire
port_rst_on
=
set_port_rst
&&
ahci_regs_di
[
0
]
;
wire
port_rst_on
=
set_port_rst
&&
ahci_regs_di
[
0
]
;
...
@@ -187,6 +189,8 @@ module axi_ahci_regs#(
...
@@ -187,6 +189,8 @@ module axi_ahci_regs#(
reg
[
2
:
0
]
arst_r
=
~
0
;
// previous state of arst
reg
[
2
:
0
]
arst_r
=
~
0
;
// previous state of arst
reg
wait_first_access
=
RESET_TO_FIRST_ACCESS
;
// keep port reset until first access
reg
wait_first_access
=
RESET_TO_FIRST_ACCESS
;
// keep port reset until first access
wire
any_access
=
bram_wen_r
||
bram_ren
[
0
]
;
wire
any_access
=
bram_wen_r
||
bram_ren
[
0
]
;
reg
debug_rd_r
;
assign
bram_addr
=
bram_ren
[
0
]
?
bram_raddr
:
(
bram_wen_r
?
bram_waddr_r
:
bram_waddr
)
;
assign
bram_addr
=
bram_ren
[
0
]
?
bram_raddr
:
(
bram_wen_r
?
bram_waddr_r
:
bram_waddr
)
;
...
@@ -198,7 +202,6 @@ module axi_ahci_regs#(
...
@@ -198,7 +202,6 @@ module axi_ahci_regs#(
always
@
(
posedge
aclk
)
begin
always
@
(
posedge
aclk
)
begin
/// bram_ren0_r <= bram_ren_w[0];
if
(
arst
)
write_busy_r
<=
0
;
if
(
arst
)
write_busy_r
<=
0
;
else
if
(
write_start_burst
)
write_busy_r
<=
1
;
else
if
(
write_start_burst
)
write_busy_r
<=
1
;
...
@@ -206,8 +209,7 @@ module axi_ahci_regs#(
...
@@ -206,8 +209,7 @@ module axi_ahci_regs#(
if
(
bram_wen
)
bram_wdata_r
<=
bram_wdata
;
if
(
bram_wen
)
bram_wdata_r
<=
bram_wdata
;
/// if (bram_ren_w[1]) bram_rdata_r <= bram_rdata;
if
(
bram_ren
[
1
])
bram_rdata_r
<=
debug_rd_r
?
debug_in
:
bram_rdata
;
if
(
bram_ren
[
1
])
bram_rdata_r
<=
bram_rdata
;
bram_wstb_r
<=
{
4
{
bram_wen
}}
&
bram_wstb
;
bram_wstb_r
<=
{
4
{
bram_wen
}}
&
bram_wstb
;
...
@@ -279,7 +281,12 @@ module axi_ahci_regs#(
...
@@ -279,7 +281,12 @@ module axi_ahci_regs#(
else
{
pgm_wa
,
pgm_wd
}
<=
{
2
{
pgm_fsm_set_w
}}
&
{
pgm_fsm_and_w
,
~
pgm_fsm_and_w
};
else
{
pgm_wa
,
pgm_wd
}
<=
{
2
{
pgm_fsm_set_w
}}
&
{
pgm_fsm_and_w
,
~
pgm_fsm_and_w
};
if
(
pgm_fsm_set_w
)
pgm_ad
<=
ahci_regs_di
[
17
:
0
]
;
if
(
pgm_fsm_set_w
)
pgm_ad
<=
ahci_regs_di
[
17
:
0
]
;
end
end
always
@
(
posedge
aclk
)
begin
if
(
bram_ren
[
0
])
debug_rd_r
<=
&
bram_raddr
[
ADDRESS_BITS
-
1
:
4
]
;
// last 16 DWORDs
end
//debug_rd_r
/*
/*
...
...
ahci/sata_ahci_top.v
View file @
57b218aa
...
@@ -224,6 +224,8 @@
...
@@ -224,6 +224,8 @@
reg
[
2
:
0
]
nhrst_r
;
reg
[
2
:
0
]
nhrst_r
;
wire
hrst
=
!
nhrst_r
[
2
]
;
wire
hrst
=
!
nhrst_r
[
2
]
;
wire
[
31
:
0
]
debug_sata
;
always
@
(
posedge
hclk
or
posedge
arst
)
begin
always
@
(
posedge
hclk
or
posedge
arst
)
begin
if
(
arst
)
nhrst_r
<=
0
;
if
(
arst
)
nhrst_r
<=
0
;
else
nhrst_r
<=
(
nhrst_r
<<
1
)
|
1
;
else
nhrst_r
<=
(
nhrst_r
<<
1
)
|
1
;
...
@@ -362,7 +364,8 @@
...
@@ -362,7 +364,8 @@
.
serr_EI
(
serr_EI
)
,
// input
.
serr_EI
(
serr_EI
)
,
// input
.
sctl_ipm
(
sctl_ipm
)
,
// output[3:0]
.
sctl_ipm
(
sctl_ipm
)
,
// output[3:0]
.
sctl_spd
(
sctl_spd
)
,
// output[3:0]
.
sctl_spd
(
sctl_spd
)
,
// output[3:0]
.
irq
(
irq
)
// output
.
irq
(
irq
)
,
// output
.
debug_in
(
debug_sata
)
// input[31:0]
)
;
)
;
ahci_sata_layers
#(
ahci_sata_layers
#(
...
@@ -420,7 +423,8 @@
...
@@ -420,7 +423,8 @@
.
txp_out
(
TXP
)
,
// output wire
.
txp_out
(
TXP
)
,
// output wire
.
txn_out
(
TXN
)
,
// output wire
.
txn_out
(
TXN
)
,
// output wire
.
rxp_in
(
RXP
)
,
// input wire
.
rxp_in
(
RXP
)
,
// input wire
.
rxn_in
(
RXN
)
// input wire
.
rxn_in
(
RXN
)
,
// input wire
.
debug_sata
(
debug_sata
)
// output[31:0]
)
;
)
;
...
...
helpers/create_ahci_registers.py
View file @
57b218aa
...
@@ -27,6 +27,7 @@ __status__ = "Development"
...
@@ -27,6 +27,7 @@ __status__ = "Development"
import
sys
import
sys
# All unspecified ranges/fields default to fT:RO, fC:0 (readonly, reset value = 0)
# All unspecified ranges/fields default to fT:RO, fC:0 (readonly, reset value = 0)
RID
=
0x02
# Revision ID (use for bitstream version)
VID
=
0xfffe
# What to use for non-PCI "vendorID"?
VID
=
0xfffe
# What to use for non-PCI "vendorID"?
DID
=
0x0001
DID
=
0x0001
SSVID
=
0xfffe
SSVID
=
0xfffe
...
@@ -112,7 +113,7 @@ src=[{gN:"PCI_Header", gS: PCIHEAD, gE:PCIHEAD+0x3f, gD:" PCI header emulation w
...
@@ -112,7 +113,7 @@ src=[{gN:"PCI_Header", gS: PCIHEAD, gE:PCIHEAD+0x3f, gD:" PCI header emulation w
{
fN
:
"IS"
,
fS
:
3
,
fT
:
RO
,
fC
:
0
,
fD
:
"Interrupt Status (1 - asserted)"
},
{
fN
:
"IS"
,
fS
:
3
,
fT
:
RO
,
fC
:
0
,
fD
:
"Interrupt Status (1 - asserted)"
},
{
fS
:
0
,
fE
:
2
,
fT
:
RO
,
fC
:
0
,
fD
:
"Reserved"
}]},
{
fS
:
0
,
fE
:
2
,
fT
:
RO
,
fC
:
0
,
fD
:
"Reserved"
}]},
{
rN
:
"RID"
,
rS
:
0x08
,
rD
:
"HBA Revision ID"
,
rC
:
{
rN
:
"RID"
,
rS
:
0x08
,
rD
:
"HBA Revision ID"
,
rC
:
[{
fN
:
"RID"
,
fT
:
RO
,
fC
:
1
,
fD
:
"HBA Revision ID"
}]},
[{
fN
:
"RID"
,
fT
:
RO
,
fC
:
RID
,
fD
:
"HBA Revision ID"
}]},
{
rN
:
"CC"
,
rS
:
0x09
,
rE
:
0x0b
,
rD
:
"Class Code"
,
rC
:
{
rN
:
"CC"
,
rS
:
0x09
,
rE
:
0x0b
,
rD
:
"Class Code"
,
rC
:
[{
fN
:
"BCC"
,
fS
:
16
,
fE
:
23
,
fT
:
RO
,
fC
:
1
,
fD
:
"Base Class Code: 1 - Mass Storage Device"
},
[{
fN
:
"BCC"
,
fS
:
16
,
fE
:
23
,
fT
:
RO
,
fC
:
1
,
fD
:
"Base Class Code: 1 - Mass Storage Device"
},
{
fN
:
"SCC"
,
fS
:
8
,
fE
:
15
,
fT
:
RO
,
fC
:
6
,
fD
:
"Sub Class Code: 0x06 - SATA Device"
},
{
fN
:
"SCC"
,
fS
:
8
,
fE
:
15
,
fT
:
RO
,
fC
:
6
,
fD
:
"Sub Class Code: 0x06 - SATA Device"
},
...
@@ -362,12 +363,12 @@ src=[{gN:"PCI_Header", gS: PCIHEAD, gE:PCIHEAD+0x3f, gD:" PCI header emulation w
...
@@ -362,12 +363,12 @@ src=[{gN:"PCI_Header", gS: PCIHEAD, gE:PCIHEAD+0x3f, gD:" PCI header emulation w
# 2 - Transitions to Slumber are disabled
# 2 - Transitions to Slumber are disabled
# 4 - Transitions to DevSleep are disabled
# 4 - Transitions to DevSleep are disabled
# Other bit-ORed values are possible
# Other bit-ORed values are possible
{
fN
:
"SPD"
,
fS
:
4
,
fE
:
7
,
fT
:
R
O
,
fC
:
0
,
fD
:
"Interface Highest Speed"
},
{
fN
:
"SPD"
,
fS
:
4
,
fE
:
7
,
fT
:
R
W
,
fC
:
0
,
fD
:
"Interface Highest Speed"
},
# 0 - No Speed Limit
# 0 - No Speed Limit
# 1 - Gen 1 speed only
# 1 - Gen 1 speed only
# 2 - Gen 2 speed or less
# 2 - Gen 2 speed or less
# 3 - Gen 3 speed or less
# 3 - Gen 3 speed or less
{
fN
:
"DET"
,
fS
:
0
,
fE
:
3
,
fT
:
R
O
,
fC
:
0
,
fD
:
"Device Detection Initialization"
},
{
fN
:
"DET"
,
fS
:
0
,
fE
:
3
,
fT
:
R
W
,
fC
:
0
,
fD
:
"Device Detection Initialization"
},
# 0 - no device detection/initialization requested
# 0 - no device detection/initialization requested
# 1 - Perform interface initialization (same as hard reset)
# 1 - Perform interface initialization (same as hard reset)
# 4 - Disable SATA and put PHY in offline mode
# 4 - Disable SATA and put PHY in offline mode
...
...
host/sata_phy.v
View file @
57b218aa
...
@@ -74,8 +74,10 @@ module sata_phy #(
...
@@ -74,8 +74,10 @@ module sata_phy #(
input
set_offline
,
// electrically idle
input
set_offline
,
// electrically idle
input
comreset_send
,
// Not possible yet?
input
comreset_send
,
// Not possible yet?
output
wire
cominit_got
,
output
wire
cominit_got
,
output
wire
comwake_got
output
wire
comwake_got
,
output
cplllock_debug
,
output
usrpll_locked_debug
,
output
[
31
:
0
]
debug_sata
)
;
)
;
wire
[
DATA_BYTE_WIDTH
*
8
-
1
:
0
]
txdata
;
wire
[
DATA_BYTE_WIDTH
*
8
-
1
:
0
]
txdata
;
...
@@ -119,6 +121,9 @@ wire rxelsempty;
...
@@ -119,6 +121,9 @@ wire rxelsempty;
assign
cominit_got
=
rxcominitdet
;
// For AHCI
assign
cominit_got
=
rxcominitdet
;
// For AHCI
assign
comwake_got
=
rxcomwakedet
;
// For AHCI
assign
comwake_got
=
rxcomwakedet
;
// For AHCI
wire
dummy
;
wire
dummy
;
oob_ctrl
oob_ctrl
(
oob_ctrl
oob_ctrl
(
// sata clk = usrclk2
// sata clk = usrclk2
.
clk
(
clk
)
,
.
clk
(
clk
)
,
...
@@ -231,6 +236,9 @@ assign rst = !sata_reset_done_r;
...
@@ -231,6 +236,9 @@ assign rst = !sata_reset_done_r;
assign
sata_reset_done
=
sata_reset_done_r
[
1
]
;
assign
sata_reset_done
=
sata_reset_done_r
[
1
]
;
assign
cplllock_debug
=
cplllock
;
assign
usrpll_locked_debug
=
usrpll_locked
;
// generate internal reset after a clock is established
// generate internal reset after a clock is established
// !!!ATTENTION!!!
// !!!ATTENTION!!!
// async rst block
// async rst block
...
@@ -257,11 +265,11 @@ end
...
@@ -257,11 +265,11 @@ end
always
@
(
posedge
gtrefclk
)
begin
always
@
(
posedge
gtrefclk
)
begin
//
rxreset_f <= ~cplllock | cpllreset | rxreset_oob & gtx_configured;
rxreset_f
<=
~
cplllock
|
cpllreset
|
rxreset_oob
&
gtx_configured
;
//
txreset_f <= ~cplllock | cpllreset;
txreset_f
<=
~
cplllock
|
cpllreset
;
rxreset_f
<=
~
cplllock
|
cpllreset
|
~
usrpll_locked
|
~
sata_reset_done
|
rxreset_oob
&
gtx_configured
;
///
rxreset_f <= ~cplllock | cpllreset | ~usrpll_locked | ~sata_reset_done | rxreset_oob & gtx_configured;
txreset_f
<=
~
cplllock
|
cpllreset
|
~
usrpll_locked
;
///
txreset_f <= ~cplllock | cpllreset | ~usrpll_locked;
txreset_f_r
<=
txreset_f
;
txreset_f_r
<=
txreset_f
;
rxreset_f_r
<=
rxreset_f
;
rxreset_f_r
<=
rxreset_f
;
...
@@ -479,4 +487,42 @@ assign ll_charisk_out = rxcharisk_out;
...
@@ -479,4 +487,42 @@ assign ll_charisk_out = rxcharisk_out;
assign
txdata_in
=
ll_data_in
;
assign
txdata_in
=
ll_data_in
;
assign
txcharisk_in
=
ll_charisk_in
;
assign
txcharisk_in
=
ll_charisk_in
;
reg
[
3
:
0
]
debug_cntr1
;
reg
[
3
:
0
]
debug_cntr2
;
reg
[
3
:
0
]
debug_cntr3
;
reg
[
3
:
0
]
debug_cntr4
;
//txoutclk
always
@
(
posedge
gtrefclk
)
begin
if
(
extrst
)
debug_cntr1
<=
0
;
else
debug_cntr1
<=
debug_cntr1
+
1
;
end
always
@
(
posedge
clk
)
begin
if
(
rst
)
debug_cntr2
<=
0
;
else
debug_cntr2
<=
debug_cntr2
+
1
;
end
always
@
(
posedge
reliable_clk
)
begin
if
(
extrst
)
debug_cntr3
<=
0
;
else
debug_cntr3
<=
debug_cntr3
+
1
;
end
always
@
(
posedge
txoutclk
)
begin
if
(
extrst
)
debug_cntr4
<=
0
;
else
debug_cntr4
<=
debug_cntr4
+
1
;
end
assign
debug_sata
[
3
:
0
]
=
debug_cntr1
;
assign
debug_sata
[
7
:
4
]
=
debug_cntr2
;
assign
debug_sata
[
11
:
8
]
=
debug_cntr3
;
assign
debug_sata
[
12
]
=
debug_cnt
[
11
]
;
assign
debug_sata
[
13
]
=
cplllock
;
assign
debug_sata
[
14
]
=
cpllreset
;
assign
debug_sata
[
15
]
=
rxelecidle
;
assign
debug_sata
[
16
]
=
usrpll_locked
;
assign
debug_sata
[
17
]
=
txreset
;
assign
debug_sata
[
18
]
=
txpcsreset
;
assign
debug_sata
[
19
]
=
txelecidle
;
assign
debug_sata
[
23
:
20
]
=
debug_cntr4
;
endmodule
endmodule
includes/ahci_defaults.vh
View file @
57b218aa
...
@@ -2,6 +2,6 @@
...
@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000030000003300000000000000000000000000000000)
, .INIT_0B (256'h0000000000000000000000030000003300000000000000000000000000000000)
, .INIT_0C (256'h00000000000000000000000000000000000000000101000
1
001000000001FFFE)
, .INIT_0C (256'h00000000000000000000000000000000000000000101000
2
001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
includes/ahci_localparams.vh
View file @
57b218aa
...
@@ -97,7 +97,7 @@
...
@@ -97,7 +97,7 @@
// RO: HBA Revision ID
// RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'h
1
;
localparam PCI_Header__RID__RID__DFLT = 'h
2
;
// RO: Base Class Code: 1 - Mass Storage Device
// RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
...
@@ -642,11 +642,11 @@
...
@@ -642,11 +642,11 @@
localparam HBA_PORT__PxSCTL__IPM__ADDR = 'h4b;
localparam HBA_PORT__PxSCTL__IPM__ADDR = 'h4b;
localparam HBA_PORT__PxSCTL__IPM__MASK = 'hf00;
localparam HBA_PORT__PxSCTL__IPM__MASK = 'hf00;
localparam HBA_PORT__PxSCTL__IPM__DFLT = 'h0;
localparam HBA_PORT__PxSCTL__IPM__DFLT = 'h0;
// R
O
: Interface Highest Speed
// R
W
: Interface Highest Speed
localparam HBA_PORT__PxSCTL__SPD__ADDR = 'h4b;
localparam HBA_PORT__PxSCTL__SPD__ADDR = 'h4b;
localparam HBA_PORT__PxSCTL__SPD__MASK = 'hf0;
localparam HBA_PORT__PxSCTL__SPD__MASK = 'hf0;
localparam HBA_PORT__PxSCTL__SPD__DFLT = 'h0;
localparam HBA_PORT__PxSCTL__SPD__DFLT = 'h0;
// R
O
: Device Detection Initialization
// R
W
: Device Detection Initialization
localparam HBA_PORT__PxSCTL__DET__ADDR = 'h4b;
localparam HBA_PORT__PxSCTL__DET__ADDR = 'h4b;
localparam HBA_PORT__PxSCTL__DET__MASK = 'hf;
localparam HBA_PORT__PxSCTL__DET__MASK = 'hf;
localparam HBA_PORT__PxSCTL__DET__DFLT = 'h0;
localparam HBA_PORT__PxSCTL__DET__DFLT = 'h0;
...
...
includes/ahci_types.vh
View file @
57b218aa
, .INIT_00 (256'h0000000000000000AAAAAAAAAAAAAAAA00000000000000070000000000000000)
, .INIT_00 (256'h0000000000000000AAAAAAAAAAAAAAAA00000000000000070000000000000000)
, .INIT_10 (256'h0000000000000000555555555555000000000000000000005555555555500000)
, .INIT_10 (256'h0000000000000000555555555555000000000000000000005555555555500000)
, .INIT_11 (256'h000000000000000055054004000001C15551500000001555AAA28000000008AA)
, .INIT_11 (256'h000000000000000055054004000001C15551500000001555AAA28000000008AA)
, .INIT_12 (256'h000000000055
0000
000000000000000000000000000000000000000000000000)
, .INIT_12 (256'h000000000055
5555
000000000000000000000000000000000000000000000000)
, .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000A)
, .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000A)
, .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D)
, .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D)
, .INIT_17 (256'h5555555555555555555555555555555500010005555555550000000000005555)
, .INIT_17 (256'h5555555555555555555555555555555500010005555555550000000000005555)
...
...
input_data/identify.dat
0 → 100644
View file @
57b218aa
0040 3fff c837 0010 0000 0000 003f 0000
0000 0000 3133 3339 3535 3430 3030 3335
2020 2020 2020 2020 0000 0000 0000 5832
3331 3230 3020 5361 6e44 6973 6b20 5344
3653 4631 4d31 3238 4720 2020 2020 2020
2020 2020 2020 2020 2020 2020 2020 8001
4000 2f00 4000 0200 0000 0007 3fff 0010
003f fc10 00fb 0101 c2b0 0ee7 0000 0007
0003 0078 0078 0078 0078 4020 0000 0000
0000 0000 0000 001f 870e 0084 014c 0044
01f0 0028 346b 7d09 4123 3469 bc09 4123
407f 0001 0006 00fe fffe 0000 0000 0000
0000 0000 0000 0000 c2b0 0ee7 0000 0000
0000 0010 4000 0000 5001 b44a 3bf2 2d63
0000 0000 0000 0000 0000 0000 0000 401c
401c 0000 0000 0000 0000 0000 0000 0000
0021 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
000b 0001 0000 0000 0000 0000 0000 0000
2020 2020 2020 2020 2020 2020 2020 2020
2020 2020 2020 2020 2020 2020 2020 2020
2020 2020 2020 2020 2020 2020 2020 2020
2020 2020 2020 2020 2020 2020 0000 0000
0000 4000 0000 0000 0000 0000 0000 0000
0000 0001 0000 0000 0000 0000 103f 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0001 0080 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 aba5
input_data/identify_hdd.dat
0 → 100644
View file @
57b218aa
427a 3fff c837 0010 0000 0000 003f 0000
0000 0000 2020 2020 2057 442d 574d 4334
4e31 3734 3733 3937 0000 0000 0000 3830
2e30 3041 3830 5744 4320 5744 3330 4546
5258 2d36 3845 555a 4e30 2020 2020 2020
2020 2020 2020 2020 2020 2020 2020 8010