Commit 57b218aa authored by Andrey Filippov's avatar Andrey Filippov

started hardware testing

parent f1b706b5
......@@ -52,87 +52,87 @@
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</projectDescription>
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?eclipse-pydev version="1.0"?><pydev_project>
<pydev_property name="org.python.pydev.PYTHON_PROJECT_INTERPRETER">Default</pydev_property>
<pydev_property name="org.python.pydev.PYTHON_PROJECT_VERSION">python 2.7</pydev_property>
</pydev_project>
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@->
VivadoBitstream_124_force=true
VivadoBitstream_125_force=true
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_125_force<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->
eclipse.preferences.version=1
......@@ -233,7 +233,8 @@ module ahci_fsm
input ch_r, // reset - may need to send SYNC escape before this command
input ch_p, // prefetchable - only used with non-zero PRDTL or ATAPI bit set
input ch_w, // Write: system memory -> device
input ch_a // ATAPI: 1 means device should send PIO setup FIS for ATAPI command
input ch_a, // ATAPI: 1 means device should send PIO setup FIS for ATAPI command
output reg [ 9:0] last_jump_addr // debug feature
/// input [4:0] ch_cfl, // length of the command FIS in DW, 0 means none. 0 and 1 - illegal,
// maximal is 16 (0x10)
/// input [11:0] dwords_sent // number of DWORDs transmitted (up to 2048)
......@@ -330,6 +331,8 @@ module ahci_fsm
if (fsm_jump[0]) pgm_addr <= pgm_jump_addr;
else if (fsm_next) pgm_addr <= pgm_addr + 1;
if (fsm_jump[0]) last_jump_addr <= pgm_jump_addr; // debug feature
// if (hba_rst) conditions <= 0;
// if (fsm_transitions[0]) conditions <= precond_w;
......
......@@ -90,7 +90,10 @@ module ahci_sata_layers #(
output wire txp_out,
output wire txn_out,
input wire rxp_in,
input wire rxn_in
input wire rxn_in,
output [31:0] debug_sata
);
localparam PHY_SPEED = 2; // SATA2
localparam FIFO_ADDR_WIDTH = 9;
......@@ -183,9 +186,9 @@ module ahci_sata_layers #(
assign serr_DH = phy_ready && (xmit_err);
// not yet assigned errors
assign serr_DT = phy_ready && (0); // RWC: Transport state transition error
assign serr_DS = phy_ready && (0); // RWC: Link sequence error
assign serr_DC = phy_ready && (0); // RWC: CRC error in Link layer
assign serr_DT = phy_ready && (comreset_send); // RWC: Transport state transition error
assign serr_DS = phy_ready && (cominit_got); // RWC: Link sequence error
assign serr_DC = phy_ready && (serr_DW); // RWC: CRC error in Link layer
// assign serr_DB = phy_ready && (0); // RWC: 10B to 8B decode error
assign serr_DI = phy_ready && (0); // RWC: PHY Internal Error
assign serr_EP = phy_ready && (0); // RWC: Protocol Error - a violation of SATA protocol detected
......@@ -194,6 +197,9 @@ module ahci_sata_layers #(
assign serr_EM = phy_ready && (0); // RWC: Communication between the device and host was lost but re-established
assign serr_EI = phy_ready && (0); // RWC: Recovered Data integrity Error
// .comreset_send (comreset_send), // input
// .cominit_got (cominit_got), // output wire
// .comwake_got (serr_DW), // output wire
......@@ -295,7 +301,11 @@ module ahci_sata_layers #(
.set_offline (set_offline), // input
.comreset_send (comreset_send), // input
.cominit_got (cominit_got), // output wire
.comwake_got (serr_DW) // output wire
.comwake_got (serr_DW), // output wire
.cplllock_debug (),
.usrpll_locked_debug(),
.debug_sata (debug_sata)
);
......
......@@ -181,7 +181,10 @@ module ahci_top#(
output irq // CPU interrupt request
output irq, // CPU interrupt request
input [31:0] debug_in
);
// axi_ahci_regs signals:
......@@ -436,6 +439,7 @@ module ahci_top#(
wire pxci0_clear; // PxCI clear
wire pxci0; // pxCI current value
wire [9:0] last_jump_addr;
// Async FF
always @ (posedge mrst or posedge mclk) begin
if (mrst) en_port <= 0;
......@@ -620,9 +624,10 @@ module ahci_top#(
.ch_r (fsnd_ch_r), // input
.ch_p (fsnd_ch_p), // input
.ch_w (fsnd_ch_w), // input
.ch_a (fsnd_ch_a) // input
.ch_a (fsnd_ch_a), // input
/// .ch_cfl (fsnd_ch_cfl), // input[4:0]
/// .dwords_sent (data_out_dwords) // input[11:0] ????
.last_jump_addr (last_jump_addr)
);
......@@ -684,11 +689,9 @@ module ahci_top#(
.afi_rcache (axi_rd_cache_mode),// output[3:0] reg
.afi_cache_set (set_axi_cache_mode), // output
.was_hba_rst (was_hba_rst), // output
.was_port_rst (was_port_rst) // output
.was_port_rst (was_port_rst), // output
.debug_in ({2'b0, last_jump_addr[9:0], debug_in[19:0]})
);
ahci_ctrl_stat #(
.ADDRESS_BITS (ADDRESS_BITS)
) ahci_ctrl_stat_i (
......
......@@ -90,7 +90,7 @@ module axi_ahci_regs#(
// Apply next 2 resets and arst OR-ed to SATA.extrst
output hba_arst, // hba async reset (currently does ~ the same as port reset)
output port_arst, // port0 async reset by software
output port_arst_any, // port0 async reset by POR or software
output port_arst_any, // port0 async reset by POR or software
// 2. HBA R/W registers, use hba clock
input hba_clk, // SATA clock, now 75MHz
......@@ -114,7 +114,8 @@ module axi_ahci_regs#(
output reg [ 3:0] afi_rcache,
output afi_cache_set,
output was_hba_rst, // last reset was hba reset (not counting system reset)
output was_port_rst // last reset was port reset
output was_port_rst, // last reset was port reset
input [31:0] debug_in
);
`include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams
......@@ -175,8 +176,9 @@ module axi_ahci_regs#(
wire pgm_fsm_and_w = |(ahci_regs_di & HBA_PORT__PGM_AHCI_SM__AnD__MASK);
wire set_hba_rst = bram_wen_r && !high_sel && (bram_addr == GHC__GHC__HR__ADDR) && (ahci_regs_di & GHC__GHC__HR__MASK);
localparam HBA_PORT__PxSCTL__DET__MASK01 = HBA_PORT__PxSCTL__DET__MASK & ~1; // == 'he
wire set_port_rst = bram_wen_r && !high_sel && (bram_addr == HBA_PORT__PxSCTL__DET__ADDR) &&
((ahci_regs_di & HBA_PORT__PxSCTL__DET__MASK | 1) == HBA_PORT__PxSCTL__DET__MASK); // writing only 0/1
((ahci_regs_di & HBA_PORT__PxSCTL__DET__MASK01) == 0); // writing only 0/1
// in lower 4 bits
wire port_rst_on = set_port_rst && ahci_regs_di[0];
......@@ -187,6 +189,8 @@ module axi_ahci_regs#(
reg [2:0] arst_r = ~0; // previous state of arst
reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
wire any_access = bram_wen_r || bram_ren[0];
reg debug_rd_r;
assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
......@@ -198,7 +202,6 @@ module axi_ahci_regs#(
always @(posedge aclk) begin
/// bram_ren0_r <= bram_ren_w[0];
if (arst) write_busy_r <= 0;
else if (write_start_burst) write_busy_r <= 1;
......@@ -206,8 +209,7 @@ module axi_ahci_regs#(
if (bram_wen) bram_wdata_r <= bram_wdata;
/// if (bram_ren_w[1]) bram_rdata_r <= bram_rdata;
if (bram_ren[1]) bram_rdata_r <= bram_rdata;
if (bram_ren[1]) bram_rdata_r <= debug_rd_r? debug_in : bram_rdata;
bram_wstb_r <= {4{bram_wen}} & bram_wstb;
......@@ -279,7 +281,12 @@ module axi_ahci_regs#(
else {pgm_wa,pgm_wd} <= {2{pgm_fsm_set_w}} & {pgm_fsm_and_w, ~pgm_fsm_and_w};
if (pgm_fsm_set_w) pgm_ad <= ahci_regs_di[17:0];
end
end
always @(posedge aclk) begin
if (bram_ren[0]) debug_rd_r <= &bram_raddr[ADDRESS_BITS-1:4]; // last 16 DWORDs
end
//debug_rd_r
/*
......
......@@ -224,6 +224,8 @@
reg [2:0] nhrst_r;
wire hrst = !nhrst_r[2];
wire [31:0] debug_sata;
always @ (posedge hclk or posedge arst) begin
if (arst) nhrst_r <= 0;
else nhrst_r <= (nhrst_r << 1) | 1;
......@@ -362,7 +364,8 @@
.serr_EI (serr_EI), // input
.sctl_ipm (sctl_ipm), // output[3:0]
.sctl_spd (sctl_spd), // output[3:0]
.irq (irq) // output
.irq (irq), // output
.debug_in (debug_sata) // input[31:0]
);
ahci_sata_layers #(
......@@ -420,7 +423,8 @@
.txp_out (TXP), // output wire
.txn_out (TXN), // output wire
.rxp_in (RXP), // input wire
.rxn_in (RXN) // input wire
.rxn_in (RXN), // input wire
.debug_sata (debug_sata) // output[31:0]
);
......
......@@ -27,6 +27,7 @@ __status__ = "Development"
import sys
# All unspecified ranges/fields default to fT:RO, fC:0 (readonly, reset value = 0)
RID = 0x02 # Revision ID (use for bitstream version)
VID = 0xfffe # What to use for non-PCI "vendorID"?
DID = 0x0001
SSVID = 0xfffe
......@@ -112,7 +113,7 @@ src=[{gN:"PCI_Header", gS: PCIHEAD, gE:PCIHEAD+0x3f, gD:" PCI header emulation w
{fN:"IS", fS: 3, fT:RO, fC:0, fD:"Interrupt Status (1 - asserted)"},
{ fS: 0, fE:2, fT:RO, fC:0, fD:"Reserved"}]},
{rN:"RID", rS:0x08, rD:"HBA Revision ID", rC:
[{fN:"RID", fT:RO, fC:1, fD:"HBA Revision ID"}]},
[{fN:"RID", fT:RO, fC:RID, fD:"HBA Revision ID"}]},
{rN:"CC", rS:0x09, rE:0x0b, rD:"Class Code", rC:
[{fN:"BCC", fS:16, fE:23, fT:RO, fC:1, fD:"Base Class Code: 1 - Mass Storage Device"},
{fN:"SCC", fS: 8, fE:15, fT:RO, fC:6, fD:"Sub Class Code: 0x06 - SATA Device"},
......@@ -362,12 +363,12 @@ src=[{gN:"PCI_Header", gS: PCIHEAD, gE:PCIHEAD+0x3f, gD:" PCI header emulation w
# 2 - Transitions to Slumber are disabled
# 4 - Transitions to DevSleep are disabled
# Other bit-ORed values are possible
{fN:"SPD", fS: 4, fE: 7, fT:RO, fC:0, fD:"Interface Highest Speed"},
{fN:"SPD", fS: 4, fE: 7, fT:RW, fC:0, fD:"Interface Highest Speed"},
# 0 - No Speed Limit
# 1 - Gen 1 speed only
# 2 - Gen 2 speed or less
# 3 - Gen 3 speed or less
{fN:"DET", fS: 0, fE: 3, fT:RO, fC:0, fD:"Device Detection Initialization"},
{fN:"DET", fS: 0, fE: 3, fT:RW, fC:0, fD:"Device Detection Initialization"},
# 0 - no device detection/initialization requested
# 1 - Perform interface initialization (same as hard reset)
# 4 - Disable SATA and put PHY in offline mode
......
......@@ -74,8 +74,10 @@ module sata_phy #(
input set_offline, // electrically idle
input comreset_send, // Not possible yet?
output wire cominit_got,
output wire comwake_got
output wire comwake_got,
output cplllock_debug,
output usrpll_locked_debug,
output [31:0] debug_sata
);
wire [DATA_BYTE_WIDTH * 8 - 1:0] txdata;
......@@ -119,6 +121,9 @@ wire rxelsempty;
assign cominit_got = rxcominitdet; // For AHCI
assign comwake_got = rxcomwakedet; // For AHCI
wire dummy;
oob_ctrl oob_ctrl(
// sata clk = usrclk2
.clk (clk),
......@@ -231,6 +236,9 @@ assign rst = !sata_reset_done_r;
assign sata_reset_done = sata_reset_done_r[1];
assign cplllock_debug = cplllock;
assign usrpll_locked_debug = usrpll_locked;
// generate internal reset after a clock is established
// !!!ATTENTION!!!
// async rst block
......@@ -257,11 +265,11 @@ end
always @ (posedge gtrefclk) begin
// rxreset_f <= ~cplllock | cpllreset | rxreset_oob & gtx_configured;
// txreset_f <= ~cplllock | cpllreset;
rxreset_f <= ~cplllock | cpllreset | rxreset_oob & gtx_configured;
txreset_f <= ~cplllock | cpllreset;
rxreset_f <= ~cplllock | cpllreset | ~usrpll_locked | ~sata_reset_done | rxreset_oob & gtx_configured;
txreset_f <= ~cplllock | cpllreset | ~usrpll_locked;
/// rxreset_f <= ~cplllock | cpllreset | ~usrpll_locked | ~sata_reset_done | rxreset_oob & gtx_configured;
/// txreset_f <= ~cplllock | cpllreset | ~usrpll_locked;
txreset_f_r <= txreset_f;
rxreset_f_r <= rxreset_f;
......@@ -479,4 +487,42 @@ assign ll_charisk_out = rxcharisk_out;
assign txdata_in = ll_data_in;
assign txcharisk_in = ll_charisk_in;
reg [3:0] debug_cntr1;
reg [3:0] debug_cntr2;
reg [3:0] debug_cntr3;
reg [3:0] debug_cntr4;
//txoutclk
always @ (posedge gtrefclk) begin
if (extrst) debug_cntr1 <= 0;
else debug_cntr1 <= debug_cntr1 + 1;
end
always @ (posedge clk) begin
if (rst) debug_cntr2 <= 0;
else debug_cntr2 <= debug_cntr2 + 1;
end
always @ (posedge reliable_clk) begin
if (extrst) debug_cntr3 <= 0;
else debug_cntr3 <= debug_cntr3 + 1;
end
always @ (posedge txoutclk) begin
if (extrst) debug_cntr4 <= 0;
else debug_cntr4 <= debug_cntr4 + 1;
end
assign debug_sata[ 3: 0] = debug_cntr1;
assign debug_sata[ 7: 4] = debug_cntr2;
assign debug_sata[11: 8] = debug_cntr3;
assign debug_sata[12] = debug_cnt[11];
assign debug_sata[13] = cplllock;
assign debug_sata[14] = cpllreset;
assign debug_sata[15] = rxelecidle;
assign debug_sata[16] = usrpll_locked;
assign debug_sata[17] = txreset;
assign debug_sata[18] = txpcsreset;
assign debug_sata[19] = txelecidle;
assign debug_sata[23:20] = debug_cntr4;
endmodule
......@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000030000003300000000000000000000000000000000)
, .INIT_0C (256'h000000000000000000000000000000000000000001010001001000000001FFFE)
, .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
......@@ -97,7 +97,7 @@
// RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'h1;
localparam PCI_Header__RID__RID__DFLT = 'h2;
// RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
......@@ -642,11 +642,11 @@
localparam HBA_PORT__PxSCTL__IPM__ADDR = 'h4b;
localparam HBA_PORT__PxSCTL__IPM__MASK = 'hf00;
localparam HBA_PORT__PxSCTL__IPM__DFLT = 'h0;
// RO: Interface Highest Speed
// RW: Interface Highest Speed
localparam HBA_PORT__PxSCTL__SPD__ADDR = 'h4b;
localparam HBA_PORT__PxSCTL__SPD__MASK = 'hf0;
localparam HBA_PORT__PxSCTL__SPD__DFLT = 'h0;
// RO: Device Detection Initialization
// RW: Device Detection Initialization
localparam HBA_PORT__PxSCTL__DET__ADDR = 'h4b;
localparam HBA_PORT__PxSCTL__DET__MASK = 'hf;
localparam HBA_PORT__PxSCTL__DET__DFLT = 'h0;
......
, .INIT_00 (256'h0000000000000000AAAAAAAAAAAAAAAA00000000000000070000000000000000)
, .INIT_10 (256'h0000000000000000555555555555000000000000000000005555555555500000)
, .INIT_11 (256'h000000000000000055054004000001C15551500000001555AAA28000000008AA)
, .INIT_12 (256'h0000000000550000000000000000000000000000000000000000000000000000)
, .INIT_12 (256'h0000000000555555000000000000000000000000000000000000000000000000)
, .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000A)
, .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D)
, .INIT_17 (256'h5555555555555555555555555555555500010005555555550000000000005555)
......
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>py393sata</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.python.pydev.PyDevBuilder</name>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.python.pydev.pythonNature</nature>
</natures>
</projectDescription>
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?eclipse-pydev version="1.0"?><pydev_project>
<pydev_pathproperty name="org.python.pydev.PROJECT_SOURCE_PATH">
<path>/${PROJECT_DIR_NAME}</path>
</pydev_pathproperty>
<pydev_property name="org.python.pydev.PYTHON_PROJECT_VERSION">python 2.7</pydev_property>
<pydev_property name="org.python.pydev.PYTHON_PROJECT_INTERPRETER">Default</pydev_property>
</pydev_project>
from __future__ import print_function
'''
# Copyright (C) 2015, Elphel.inc.
# Memory read/write functions
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
@author: Andrey Filippov
@copyright: 2015 Elphel, Inc.
@license: GPLv3.0+
@contact: andrey@elphel.coml
@deffield updated: Updated
'''
__author__ = "Andrey Filippov"
__copyright__ = "Copyright 2015, Elphel, Inc."
__license__ = "GPL"
__version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
import mmap
#import sys
import struct
import os
class X393Mem(object):
'''
classdocs
'''
DRY_MODE= True # True
PAGE_SIZE=4096
DEBUG_MODE=1
ENDIAN="<" # little, ">" for big
MAXI0_BASE=0x40000000
MAXI1_BASE=0x80000000
MAXI_BASE = MAXI0_BASE
def __init__(self, debug_mode=1,dry_mode=False, maxi_port=0):
if maxi_port:
self.MAXI_BASE=self.MAXI1_BASE
else:
self.MAXI_BASE=self.MAXI0_BASE;
self.DEBUG_MODE=debug_mode
if not dry_mode:
if not os.path.exists("/dev/xdevcfg"):
dry_mode=True
print("Program is forced to run in SIMULATED mode as '/dev/xdevcfg' does not exist (not a camera)")
self.DRY_MODE=dry_mode
def maxi_base(self, maxi_port=None):
if not maxi_port is None:
if maxi_port:
self.MAXI_BASE=self.MAXI1_BASE
else:
self.MAXI_BASE=self.MAXI0_BASE;
else:
maxi_port = (0,1)[self.MAXI_BASE == self.MAXI1_BASE]
print ("MAXI port = %d (0x%08x)"%(maxi_port, self.MAXI_BASE))
def write_mem (self,addr, data,quiet=1):
"""
Write 32-bit word to physical memory
@param addr - physical byte address
@param data - 32-bit data to write
@param quiet - reduce output
"""
if self.DRY_MODE:
print ("simulated: write_mem(0x%x,0x%x)"%(addr,data))
return
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
packedData=struct.pack(self.ENDIAN+"L",data)
d=struct.unpack(self.ENDIAN+"L",packedData)[0]
mm[page_offs:page_offs+4]=packedData
if quiet <1:
print ("0x%08x <== 0x%08x (%d)"%(addr,d,d))
'''
if MONITOR_EMIO and VEBOSE:
gpio0=read_mem (0xe000a068)
gpio1=read_mem (0xe000a06c)
print("GPIO: %04x %04x %04x %04x"%(gpio1>>16, gpio1 & 0xffff, gpio0>>16, gpio0 & 0xffff))
if ((gpio0 & 0xc) != 0xc) or ((gpio0 & 0xff00) != 0):
print("******** AXI STUCK ************")
exit (0)
'''
def read_mem (self,addr,quiet=1):
'''
Read 32-bit word from physical memory
@param addr physical byte address
@param quiet - reduce output
'''
if self.DRY_MODE:
print ("simulated: read_mem(0x%x)"%(addr))
return addr # just some data
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
data=struct.unpack(self.ENDIAN+"L",mm[page_offs:page_offs+4])
d=data[0]
if quiet < 1:
print ("0x%08x ==> 0x%08x (%d)"%(addr,d,d))
return d
def mem_dump (self, start_addr, end_addr=1, byte_mode=4):
'''
Read and print memory range from physical memory
@param start_addr physical byte start address
@param end_addr physical byte end address (inclusive), if negative/less than start_addr - number of items
@param byte_mode number of bytes per item (1,2,4,8)
@return list of read values
'''
frmt_bytes={1:'B',2:'H',4:'L',8:'Q'}
bytes_per_line_mask={1:0x1f,2:0x1f,4:0x3f,8:0x3f}
default_byte_mode=4
if not byte_mode in frmt_bytes.keys():
print ("Invalid byte mode: '%s'. Only %s are supported. Using %d"%(str(byte_mode),str(frmt_bytes.keys()),default_byte_mode))
byte_mode=default_byte_mode
data_frmt= "%%0%dx"%(2*byte_mode)
simul_mask= (1 << (8*byte_mode)) -1
addr_mask=0xffffffff ^ (byte_mode-1)
start_addr &= addr_mask
if end_addr < start_addr:
end_addr=start_addr + abs(end_addr*byte_mode) -1
end_addr &= addr_mask
# align start address to 32-bit word even if the mode is byte/short
start_addr &= 0xfffffffc
print_mask=bytes_per_line_mask[byte_mode]
rslt=[]
if self.DRY_MODE:
rslt=[d & simul_mask for d in range(start_addr,end_addr+byte_mode,byte_mode)]
else:
with open("/dev/mem", "r+b") as f:
for addr in range (start_addr,end_addr+byte_mode,byte_mode):
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
mm = mmap.mmap(f