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Commit 50ca592a authored by Andrey Filippov's avatar Andrey Filippov
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got identify PIO data from the SSD

parent 0a15e1e3
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.project
View file @ 50ca592a
......@@ -52,87 +52,87 @@
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ahci/ahci_ctrl_stat.v
View file @ 50ca592a
......@@ -467,7 +467,8 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
else if (pfsm_started) pfsm_started_r <= 1;
if (!pfsm_started_r) pcmd_st_cleared <= 0;
else if (swr_HBA_PORT__PxCMD) pcmd_st_cleared <= |(HBA_PORT__PxCMD__ST__MASK & PxCMD_r & ~soft_write_data);
// else if (swr_HBA_PORT__PxCMD) pcmd_st_cleared <= |(HBA_PORT__PxCMD__ST__MASK & PxCMD_r & ~soft_write_data);
else pcmd_st_cleared <= swr_HBA_PORT__PxCMD && (|(HBA_PORT__PxCMD__ST__MASK & PxCMD_r & ~soft_write_data));
end
......@@ -487,7 +488,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
({32{update_HBA_PORT__PxCMD}} & PxCMD_r) |
({32{update_HBA_PORT__PxCI}} & {31'b0, pxci0});
regs_we <= update_GHC__IS || update_HBA_PORT__PxIS || update_HBA_PORT__PxSSTS || update_HBA_PORT__PxSERR | update_HBA_PORT__PxCMD;
regs_we <= update_GHC__IS || update_HBA_PORT__PxIS || update_HBA_PORT__PxSSTS || update_HBA_PORT__PxSERR | update_HBA_PORT__PxCMD || update_HBA_PORT__PxCI;
// pending updates
if (mrst) pxci_changed <= 1; //0;
......
ahci/ahci_fis_transmit.v
View file @ 50ca592a
......@@ -100,6 +100,8 @@ module ahci_fis_transmit #(
output todev_valid, // output register full
input todev_ready // send FIFO has room for data (>= 8? dwords)
,output [9:0] debug_01
// Add a possiblity to flush any data to FIFO if error was detected after data went there?
);
localparam CLB_OFFS32 = 'h200; // # In the second half of the register space (0x800..0xbff - 1KB)
......@@ -152,6 +154,7 @@ module ahci_fis_transmit #(
wire ct_re_w; // next cycle will be ct_re;
reg [READ_CT_LATENCY:0] ct_re_r;
wire ct_stb = ct_re_r[READ_CT_LATENCY];
reg fis_dw_first;
......@@ -204,7 +207,9 @@ module ahci_fis_transmit #(
// What else to wait for when
assign fis_data_valid = ct_stb || (!dma_ct_busy && dx_fis_pend_r); // no wait write to output register 'todev_data', ct_re_r[0] is throttled according to FIFO room availability
assign ct_re_w = todev_ready && ((cfis_acmd_left_r[4:1] != 0) || (cfis_acmd_left_r[0] && !ct_re_r[0])); // Later add more sources
/// assign ct_re_w = todev_ready && ((cfis_acmd_left_r[4:1] != 0) || (cfis_acmd_left_r[0] && !ct_re_r[0])); // Later add more sources
assign ct_re_w = todev_ready && acfis_xmit_busy_r && ((cfis_acmd_left_r[4:1] != 0) || (cfis_acmd_left_r[0] && !ct_re_r[0])); // Later add more sources
//
assign fis_dw_last = (cfis_acmd_left_out_r == 1);
assign fis_data_type = {fis_dw_last, (write_or_w && dx_fis_pend_r) | (fis_dw_first && ct_stb)};
......@@ -219,6 +224,11 @@ module ahci_fis_transmit #(
// When watching for FIS end, do not fill/use output register in the same cycle
reg [3:0] dbg_was_ct_re_r;
reg [4:0] dbg_was_cfis_acmd_left_r;
always @ (posedge mclk) begin
// Mutliplex between DMA and FIS output to the output routed to transmit FIFO
// Count bypassing DMA dwords to generate FIS_last condition?
......@@ -308,7 +318,8 @@ module ahci_fis_transmit #(
if (acfis_xmit_start_r) cfis_acmd_left_out_r <= cfis_acmd_left_r;
else if (ct_stb) cfis_acmd_left_out_r <= cfis_acmd_left_out_r - 1;
ct_re_r <= {ct_re_r[READ_CT_LATENCY-1:0],ct_re_w};
if (hba_rst || acfis_xmit_start_w) ct_re_r <= 0;
else ct_re_r <= {ct_re_r[READ_CT_LATENCY-1:0], ct_re_w};
if (cfis_xmit) ct_addr <= 0;
else if (atapi_xmit) ct_addr <= 'h10; // start of ATAPI area
......@@ -369,8 +380,15 @@ module ahci_fis_transmit #(
dma_cmd_abort <= done_w && (|dx_err_r);
if (cfis_xmit) dbg_was_ct_re_r <= {ct_re_r, ct_re_w};
if (cfis_xmit) dbg_was_cfis_acmd_left_r <= cfis_acmd_left_r;
end
assign debug_01 = {dx_fis_pend_r, ct_re_r, ct_re_w, cfis_acmd_left_r}; // 1,2,5
// assign debug_01 = {acfis_xmit_start_w, acfis_xmit_pend_r, dma_ct_busy, fetch_cmd_busy_r, ct_re_w, dbg_was_cfis_acmd_left_r}; // 1,2,5
// wire acfis_xmit_start_w = (cfis_xmit || atapi_xmit || acfis_xmit_pend_r) && !dma_ct_busy && !fetch_cmd_busy_r; // dma_ct_busy no gaps with fetch_cmd_busy
endmodule
ahci/ahci_fsm.v
View file @ 50ca592a
......@@ -274,6 +274,7 @@ module ahci_fsm
reg [1:0] async_pend_r; // waiting to process cominit_got
reg async_from_st; // chnge to multi-bit if there will be more sources for async transitions
wire asynq_rq = cominit_got || pcmd_st_cleared;
// OK to wait for some time fsm_act_busy is supposed to never hang up
wire async_ackn = !fsm_preload && async_pend_r[0] && ((fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]); // OK to process async jump
// reg x_rdy_collision_pend;
reg syncesc_send_pend; // waiting for 'syncesc_send' confiramtion 'syncesc_send_done'
......@@ -358,7 +359,8 @@ module ahci_fsm
else if (asynq_rq) async_from_st <= 0;
if (hba_rst) async_pend_r <= 0;
else async_pend_r <= {async_pend_r[0], asynq_rq | (async_pend_r[0] & ~async_ackn)};
/// else async_pend_r <= {async_pend_r[0], asynq_rq | (async_pend_r[0] & ~async_ackn)};
else async_pend_r <= {async_pend_r[0], (asynq_rq | async_pend_r[0]) & ~async_ackn};
// if (hba_rst || pcmd_cr_set) x_rdy_collision_pend <= 0;
......
ahci/ahci_sata_layers.v
View file @ 50ca592a
......@@ -183,7 +183,8 @@ module ahci_sata_layers #(
/// assign debug_sata = debug_phy;
// assign debug_sata = {debug_link[31:4],debug_phy[3:0]} ; //
assign debug_sata = {debug_link[31:8],debug_phy[7:0]} ; //
// assign debug_sata = {debug_link[31:8],debug_phy[7:0]} ; //
assign debug_sata = {debug_link[27:20],debug_phy[23:0]} ; //
assign ll_h2d_last = (h2d_type_out == H2D_TYPE_FIS_LAST);
assign d2h_valid = d2h_nempty;
......
ahci/ahci_top.v
View file @ 50ca592a
......@@ -187,6 +187,14 @@ module ahci_top#(
);
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
wire datascope_clk;
wire [ADDRESS_BITS-1:0] datascope_waddr;
wire datascope_we;
wire [31:0] datascope_di;
`endif
// axi_ahci_regs signals:
// 1. Notification of data written @ hba_clk
wire [ADDRESS_BITS-1:0] soft_write_addr; // register address written by software
......@@ -691,6 +699,12 @@ module ahci_top#(
.was_hba_rst (was_hba_rst), // output
.was_port_rst (was_port_rst), // output
.debug_in ({2'b0, last_jump_addr[9:0], debug_in[19:0]})
`ifdef USE_DATASCOPE
,.datascope_clk (datascope_clk), // input
.datascope_waddr (datascope_waddr), // input[9:0]
.datascope_we (datascope_we), // input
.datascope_di (datascope_di) // input[31:0]
`endif
/// .debug_in (debug_in[31:0])
);
ahci_ctrl_stat #(
......@@ -938,7 +952,8 @@ module ahci_top#(
.dma_in_ready (dma_in_ready), // input
.dma_in_valid (dma_we) // output
);
wire ahci_fis_transmit_busy;
wire [9:0] xmit_dbg_01;
ahci_fis_transmit #(
.PREFETCH_ALWAYS (PREFETCH_ALWAYS),
.READ_REG_LATENCY (READ_REG_LATENCY),
......@@ -955,7 +970,7 @@ module ahci_top#(
.atapi_xmit (fsnd_atapi_xmit), // input
.done (fsnd_done), // output reg
.busy (), /// fsnd_busy), // output reg
.busy (ahci_fis_transmit_busy), /// fsnd_busy), // output reg
.clearCmdToIssue (fsnd_clearCmdToIssue), // input
.pCmdToIssue (fsnd_pCmdToIssue), // output
.xmit_ok (xmit_ok), // input
......@@ -995,8 +1010,47 @@ module ahci_top#(
.todev_type (h2d_type), // output[1:0] reg
.todev_valid (h2d_valid), // output
.todev_ready (h2d_ready) // input
,.debug_01(xmit_dbg_01)
);
// Datascope code
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
// wire datascope_clk;
// wire [ADDRESS_BITS-1:0] datascope_waddr;
// wire datascope_we;
// wire [31:0] datascope_di;
localparam DATASCOPE_CFIS_START=0;
reg [ADDRESS_BITS-1:0] datascope_waddr_r;
reg [1:0] datascope_run;
reg [8:0] datascope_cntr;
reg datascope_was_busy;
assign datascope_clk = mclk;
// assign datascope_di = datascope_run[0]? {h2d_type, dma_dav, datascope_was_busy, xmit_dbg_01, datascope_cntr[3:0], h2d_data[15:0]} : {{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};
assign datascope_di = datascope_run[0]? {h2d_type, xmit_dbg_01, datascope_cntr[3:0], h2d_data[15:0]} : {{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};
assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || (datascope_run == 2);
assign datascope_waddr = datascope_waddr_r;
always @(posedge mclk) begin
if (mrst) datascope_run[0] <= 0;
else if (fsnd_cfis_xmit) datascope_run[0] <= 1;
else if (h2d_valid && h2d_ready && (h2d_type == 2)) datascope_run[0] <= 0;
datascope_run[1] <= datascope_run[0];
if (fsnd_cfis_xmit) datascope_waddr_r <= DATASCOPE_CFIS_START;
else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;
if (fsnd_cfis_xmit) datascope_cntr <= 0;
else datascope_cntr <= datascope_cntr + 1;
if (fsnd_cfis_xmit) datascope_was_busy <= ahci_fis_transmit_busy;
end
`endif
endmodule
ahci/axi_ahci_regs.v
View file @ 50ca592a
......@@ -116,30 +116,28 @@ module axi_ahci_regs#(
output was_hba_rst, // last reset was hba reset (not counting system reset)
output was_port_rst, // last reset was port reset
input [31:0] debug_in
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
,input datascope_clk,
input [ADDRESS_BITS-1:0] datascope_waddr,
input datascope_we,
input [31:0] datascope_di
`endif
);
`ifdef USE_DATASCOPE
localparam AXIBRAM_BITS = ADDRESS_BITS + 1; // number of axi address outputs (one more than ADDRESS_BITS when using datascope)
wire [31:0] datascope_rdata;
reg [1:0] datascope_sel; // read datascope memory instead of the registers
always @ (posedge aclk) begin
datascope_sel <= {datascope_sel[0], bram_raddr[ADDRESS_BITS]};
end
`else
localparam AXIBRAM_BITS = ADDRESS_BITS; // number of axi address outputs (one more than ADDRESS_BITS when using datascope)
`endif
`include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams
/*
localparam GHC__GHC__HR__ADDR = 'h1;
localparam GHC__GHC__HR__MASK = 'h1;
localparam GHC__GHC__HR__DFLT = 'h0;
// RO: Device Detection Initialization
localparam HBA_PORT__PxSCTL__DET__ADDR = 'h4b;
localparam HBA_PORT__PxSCTL__DET__MASK = 'hf;
localparam HBA_PORT__PxSCTL__DET__DFLT = 'h0;
// RW: SAXIHP write channel cache mode
localparam HBA_PORT__AFI_CACHE__WR_CM__ADDR = 'h5c;
localparam HBA_PORT__AFI_CACHE__WR_CM__MASK = 'hf0;
localparam HBA_PORT__AFI_CACHE__WR_CM__DFLT = 'h30;
// RW: SAXIHP read channel cache mode
localparam HBA_PORT__AFI_CACHE__RD_CM__ADDR = 'h5c;
localparam HBA_PORT__AFI_CACHE__RD_CM__MASK = 'hf;
localparam HBA_PORT__AFI_CACHE__RD_CM__DFLT = 'h3;
*/
wire [ADDRESS_BITS-1:0] bram_waddr;
wire [AXIBRAM_BITS-1:0] bram_waddr;
// wire [ADDRESS_BITS-1:0] pre_awaddr;
wire [ADDRESS_BITS-1:0] bram_raddr;
wire [AXIBRAM_BITS-1:0] bram_raddr;
wire [31:0] bram_rdata;
wire pre_bram_wen; // one cycle ahead of bram_wen, nut not masked by dev_ready
wire bram_wen;
......@@ -192,7 +190,7 @@ module axi_ahci_regs#(
reg debug_rd_r;
assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
assign bram_addr = bram_ren[0] ? bram_raddr[ADDRESS_BITS-1:0] : (bram_wen_r ? bram_waddr_r : bram_waddr[ADDRESS_BITS-1:0]);
assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset)
assign port_arst = port_rst_r; // port _reset by software
......@@ -215,7 +213,7 @@ module axi_ahci_regs#(
bram_wen_r <= bram_wen;
if (bram_wen) bram_waddr_r <= bram_waddr;
if (bram_wen) bram_waddr_r <= bram_waddr[ADDRESS_BITS-1:0];
end
......@@ -284,7 +282,7 @@ module axi_ahci_regs#(
end
always @(posedge aclk) begin
if (bram_ren[0]) debug_rd_r <= &bram_raddr[ADDRESS_BITS-1:4]; // last 16 DWORDs
if (bram_ren[0]) debug_rd_r <= &bram_raddr[ADDRESS_BITS-1:4]; // last 16 DWORDs (With AXIBRAM_BITS will be duplicated)
end
//debug_rd_r
......@@ -325,7 +323,7 @@ sata_phy_rst_out will be released after the sata clock is stable
axibram_write #(
.ADDRESS_BITS(ADDRESS_BITS)
.ADDRESS_BITS(AXIBRAM_BITS) // in debug mode - 1 bit more than ADDERSS_BITS
) axibram_write_i (
.aclk (aclk), // input
.arst (arst), // input
......@@ -359,7 +357,7 @@ sata_phy_rst_out will be released after the sata clock is stable
);
axibram_read #(
.ADDRESS_BITS(ADDRESS_BITS)
.ADDRESS_BITS(AXIBRAM_BITS) // in debug mode - 1 bit more than ADDERSS_BITS
) axibram_read_i (
.aclk (aclk), // input
.arst (arst), // input
......@@ -383,7 +381,11 @@ sata_phy_rst_out will be released after the sata clock is stable
.bram_raddr (bram_raddr), // output[9:0]
.bram_ren (bram_ren[0]), // output
.bram_regen (bram_ren[1]), // output
`ifdef USE_DATASCOPE
.bram_rdata (datascope_sel[1] ? datascope_rdata : bram_rdata_r) // input[31:0]
`else
.bram_rdata (bram_rdata_r) // input[31:0]
`endif
);
// Register memory, lower half uses read-modify-write using bit type from ahci_regs_type_i ROM, 2 aclk cycles/per write and
......@@ -442,6 +444,26 @@ sata_phy_rst_out will be released after the sata clock is stable
.data_in (64'b0) // input[63:0]
);
`ifdef USE_DATASCOPE
ram_var_w_var_r #(
.REGISTERS (0),
.LOG2WIDTH_WR (5),
.LOG2WIDTH_RD (5),
.DUMMY(0)
) datascope_mem_i (
.rclk (aclk), // input
.raddr (bram_raddr[9:0]), // input[9:0]
.ren (bram_ren[0]), // input
.regen (bram_ren[1]), // input
.data_out (datascope_rdata), // output[31:0]
.wclk (datascope_clk), // input
.waddr (datascope_waddr), // input[9:0]
.we (datascope_we), // input
.web (8'hff), // input[7:0]
.data_in (datascope_di) // input[31:0]
);
`endif
fifo_cross_clocks #(
.DATA_WIDTH(ADDRESS_BITS+32),
.DATA_DEPTH(4)
......
device/sata_device.v
View file @ 50ca592a
......@@ -758,17 +758,17 @@ task send_good_status; // @SuppressThisWarning VEditor - Used in testbench
{1'b0,dev_specific_status_bits,4'b0}, // status
1, // error
0, // device
0, // lba_low
1, // lba_low
0, // lba_high
0, // count
1, // count
status); // output: result status
transmit_data[0] = FIS_D2HR | (irq? 'h4000:0) | (dev_specific_status_bits << 20) | 'h1000000;
transmit_data[1] = 1;
transmit_data[2] = 0;
transmit_data[3] = 1;
transmit_data[4] = 0;
linkTransmitFIS(id, 5, 0, status);
// transmit_data[0] = FIS_D2HR | (irq? 'h4000:0) | (dev_specific_status_bits << 20) | 'h1000000;
// transmit_data[1] = 1;
// transmit_data[2] = 0;
// transmit_data[3] = 1;
// transmit_data[4] = 0;
// linkTransmitFIS(id, 5, 0, status);
end
endtask
......
host/gtx_wrap.v
View file @ 50ca592a
......@@ -64,6 +64,10 @@ module gtx_wrap #(
output wire rxcominitdet,
output wire rxelecidle,
output wire rxresetdone,
input wire clk_phase_align_req,
output wire clk_phase_align_ack,
input wire txreset,
input wire txusrclk,
input wire txusrclk2,
......@@ -89,7 +93,9 @@ module gtx_wrap #(
output wire dbg_rxphaligndone,
output wire dbg_rx_clocks_aligned,
output wire dbg_rxcdrlock,
output wire dbg_rxdlysresetdone
output wire dbg_rxdlysresetdone,
output wire [1:0] txbufstatus
);
wire rxresetdone_gtx;
......@@ -129,17 +135,6 @@ assign txchardispmode_gtx = {6'h0, txdata_enc_out[19], txdata_enc_out[9]};
assign txchardispval_gtx = {6'h0, txdata_enc_out[18], txdata_enc_out[8]};
// Interface part
/*
input wire cpllreset, - async
input wire wrap_rxreset_, - async
input wire wrap_txreset_, - async
input wire rxreset, - async
input wire txreset, - async
input wire txelecidle, - txusrclk2 - need to resync to gtx iface clk - txusrclk
input wire txpcsreset, - async
input wire txcominit, - txusrclk2 - need to resync to gtx iface clk - txusrclk
input wire txcomwake, - txusrclk2 - need to resync to gtx iface clk - txusrclk
*/
// @ gtx iface clk
wire txcominit_gtx;
wire txcomwake_gtx;
......@@ -178,15 +173,7 @@ if (DATA_BYTE_WIDTH == 4) begin
always @ (posedge txreset or posedge txusrclk) begin
if (txreset) txdata_resync_strobe <= 0;
else if (txdata_resync_valid) txdata_resync_strobe <= ~txdata_resync_strobe;
/*
if (txreset) begin
txdata_enc_in_r <= 0;
txcharisk_enc_in_r <= 0;
end else if (txdata_resync_valid) begin
txdata_enc_in_r <= txdata_resync_strobe? txdata_resync_out[31:16]: txdata_resync_out[15:0];
txcharisk_enc_in_r <= txdata_resync_strobe? txdata_resync_out[35:34]: txdata_resync_out[33:32];
end
*/
if (txreset) begin
txcomwake_gtx_f <= 0;
txcominit_gtx_f <= 0;
......@@ -246,37 +233,93 @@ gtx_8x10enc gtx_8x10enc(
);
// Adjust RXOUTCLK so RXUSRCLK (==xclk) matches SIPO output data
`ifdef CLK_ADJUST_VARIANT_1
wire rxcdrlock; // Marked as "reserved" - maybe not use it, only rxelecidle?
reg rxdlysreset = 0;
wire rxphaligndone;
wire rxdlysresetdone;
reg rx_clocks_aligned = 0;
reg [2:0] rxdlysreset_cntr = 7;
reg rxdlysresetdone_r;
wire rxcdrlock; // Marked as "reserved" - maybe not use it, only rxelecidle?
reg rxdlysreset = 0;
wire rxphaligndone;
wire rxdlysresetdone;
reg rx_clocks_aligned = 0;
reg [2:0] rxdlysreset_cntr = 7;
reg rxdlysresetdone_r;
assign dbg_rxphaligndone = rxphaligndone; // never gets up?
assign dbg_rx_clocks_aligned = rx_clocks_aligned;
assign dbg_rxcdrlock = rxcdrlock; //goes in/out (because of the SS ?
assign dbg_rxdlysresetdone = rxdlysresetdone_r;
always @ (posedge xclk) begin
// if (rxelecidle || !rxcdrlock) rxdlysreset_cntr <= 5;
assign dbg_rxphaligndone = rxphaligndone; // never gets up?
assign dbg_rx_clocks_aligned = rx_clocks_aligned;
assign dbg_rxcdrlock = rxcdrlock; //goes in/out (because of the SS ?
assign dbg_rxdlysresetdone = rxdlysresetdone_r;
always @ (posedge xclk) begin
// if (rxelecidle || !rxcdrlock) rxdlysreset_cntr <= 5;
if (rxelecidle) rxdlysreset_cntr <= 5;
else if (|rxdlysreset_cntr) rxdlysreset_cntr <= rxdlysreset_cntr - 1;
// if (rxelecidle || !rxcdrlock) rxdlysreset <= 0;
// if (rxelecidle || !rxcdrlock) rxdlysreset <= 0;
if (rxelecidle) rxdlysreset <= 0;
else rxdlysreset <= |rxdlysreset_cntr;
// if (rxelecidle || !rxcdrlock || rxdlysreset || |rxdlysreset_cntr) rx_clocks_aligned <= 0;
// if (rxelecidle || rxdlysreset || |rxdlysreset_cntr) rx_clocks_aligned <= 0;
// if (rxelecidle || !rxcdrlock || rxdlysreset || |rxdlysreset_cntr) rx_clocks_aligned <= 0;
// if (rxelecidle || rxdlysreset || |rxdlysreset_cntr) rx_clocks_aligned <= 0;
if (rxelecidle) rx_clocks_aligned <= 0;
// else if (rxphaligndone) rx_clocks_aligned <= 1;
// else if (rxphaligndone) rx_clocks_aligned <= 1;
else if (rxphaligndone) rx_clocks_aligned <= 1;
if (rxelecidle || rxdlysreset || |rxdlysreset_cntr) rxdlysresetdone_r <= 0;
else if (rxdlysresetdone) rxdlysresetdone_r <= 1;
end
end
`else
// time to first rxphaligndone ~450ns, time to second (that should stay - 4.9 usec, still much less than allowed ALIGNp response time)
wire rxdlysreset = clk_phase_align_req;
reg rxphaligndone1_r = 0; // first time rxphaligndone gets active
reg rxphaligndone2_r = 0; // rxphaligndone deasserted
reg rx_clocks_aligned = 0; // second time rxphaligndone gets active (and is supposed to stay)
reg rxdlysresetdone_r;
wire rxphaligndone;
wire rxdlysresetdone;
wire rxcdrlock; // Marked as "reserved" - maybe not use it, only rxelecidle? (seems alternating 0/1 forever- SS?)
assign clk_phase_align_ack = rx_clocks_aligned;
assign dbg_rxphaligndone = rxphaligndone; // never gets up?
assign dbg_rx_clocks_aligned = rx_clocks_aligned;
assign dbg_rxcdrlock = rxcdrlock; //goes in/out (because of the SS ?
assign dbg_rxdlysresetdone = rxdlysresetdone_r;
`ifdef ALIGN_CLOCKS
always @ (posedge xclk) begin
if (rxelecidle) rxphaligndone1_r <= 0;
else if (rxphaligndone) rxphaligndone1_r <= 1;
if (rxelecidle) rxphaligndone2_r <= 0;
else if (rxphaligndone1_r && !rxphaligndone) rxphaligndone2_r <= 1;
if (rxelecidle) rx_clocks_aligned <= 0;
else if (rxphaligndone2_r && rxphaligndone) rx_clocks_aligned <= 1;
if (rxelecidle || rxdlysreset) rxdlysresetdone_r <= 0;
else if (rxdlysresetdone) rxdlysresetdone_r <= 1;
end
`else // ALIGN_CLOCKS - just bypassing
always @ (posedge xclk) begin
if (rxelecidle) rxphaligndone1_r <= 0;
else if (clk_phase_align_req) rxphaligndone1_r <= 1;
if (rxelecidle) rxphaligndone2_r <= 0;
else if (rxphaligndone1_r && !clk_phase_align_req) rxphaligndone2_r <= 1;
if (rxelecidle) rx_clocks_aligned <= 0;
else if (rxphaligndone2_r) rx_clocks_aligned <= 1;
if (rxelecidle || rxdlysreset) rxdlysresetdone_r <= 0;
else if (rxphaligndone2_r) rxdlysresetdone_r <= 1;
end
`endif
`endif
/*
* RX PCS part: comma detect + align module, 10/8 decoder, elastic buffer, interface resynchronisation
......@@ -371,7 +414,8 @@ wire rxcominitdet_gtx;
.rclk (rxusrclk),
/// .isaligned_in (state_aligned),
.isaligned_in (state_aligned && rxdlysresetdone_r), // rx_clocks_aligned), //Allow to align early, but do not tell it is aligned until xclk is aligned to SIPO par. clock
// .isaligned_in (state_aligned && rxdlysresetdone_r), // input
.isaligned_in (state_aligned), // input Moved clock phase reset/align to OOB module to handle
.charisk_in (rxcharisk_dec_out),
.notintable_in (rxnotintable_dec_out),
.disperror_in (rxdisperr_dec_out),
......@@ -505,7 +549,8 @@ wire rxcominitdet_gtx;
) elastic1632_i (
.wclk (xclk), // input 150MHz, recovered
.rclk (rxusrclk2), // input 75 MHz, system
.isaligned_in (state_aligned && rxdlysresetdone_r), // input
// .isaligned_in (state_aligned && rxdlysresetdone_r), // input
.isaligned_in (state_aligned), // input Moved clock phase reset/align to OOB module to handle
.charisk_in (rxcharisk_dec_out), // input[1:0]
.notintable_in (rxnotintable_dec_out), // input[1:0]
.disperror_in (rxdisperr_dec_out), // input[1:0]
......@@ -518,14 +563,7 @@ wire rxcominitdet_gtx;
.full (rxelsfull), // output
.empty (rxelsempty) // output
);
/*
// What is left:
assign rxcomwakedet = rxdata_resync_out[49];
assign rxcominitdet = rxdata_resync_out[48];
assign rxresetdone = rxdata_resync_out[47];
assign txresetdone = rxdata_resync_out[46];
*/
reg rxresetdone_r;
reg txresetdone_r;
always @ (posedge rxusrclk2) rxresetdone_r <= rxresetdone_gtx;
......@@ -674,7 +712,11 @@ gtxe2_channel_wrapper #(
.RXPH_CFG (24'h000000),
.RXPHDLY_CFG (24'h084020),
.RXPH_MONITOR_SEL (5'b00000),
`ifdef ALIGN_CLOCKS
.RX_XCLK_SEL ("RXUSR"), // ("RXREC"), // Andrey: Now they are the same, just using p.247 "Using RX Buffer Bypass..."
`else
.RX_XCLK_SEL ("RXREC"), // Andrey: Does not align clocks if in this mode
`endif
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
/// .RXCDR_CFG (72'h03000023ff10200020),// 1.6G - 6.25G, No SS, RXOUT_DIV=2
......@@ -850,10 +892,13 @@ gtxe2_channel_wrapper(
.GTXRXN (rxn),
.RXBUFRESET (1'b0),
.RXBUFSTATUS (),
// .RXDDIEN (1'b0),
`ifdef ALIGN_CLOCKS
.RXDDIEN (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode"
// .RXDLYBYPASS (1'b1),
.RXDLYBYPASS (1'b0), // Andrey: p.243: "0: Uses the RX delay alignment circuit."
`else
.RXDDIEN (1'b0),
.RXDLYBYPASS (1'b1),
`endif
.RXDLYEN (1'b0),
.RXDLYOVRDEN (1'b0),
.RXDLYSRESET (rxdlysreset),
......@@ -975,7 +1020,7 @@ gtxe2_channel_wrapper(
.TXPHINIT (1'b0),
.TXPHINITDONE (),
.TXPHOVRDEN (1'b0),
.TXBUFSTATUS (),
.TXBUFSTATUS (txbufstatus[1:0]), // Andrey
.TXBUFDIFFCTRL (3'b100),
.TXDEEMPH (1'b0),
.TXDIFFCTRL (4'b1000),
......
host/link.v
View file @ 50ca592a
......@@ -391,29 +391,29 @@ assign clr_rcvr_badend = set_nocommerr | set_reset | set_sync_esc | got_esc
// Others transitions are straightforward
always @ (posedge clk)
begin
state_sync_esc <= (state_sync_esc | set_sync_esc & ~alignes_pair) & ~clr_sync_esc & ~rst;
state_nocommerr <= (state_nocommerr | set_nocommerr & ~alignes_pair) & ~clr_nocommerr & ~rst;
state_nocomm <= (state_nocomm | set_nocomm & ~alignes_pair) & ~clr_nocomm & ~rst;
state_sync_esc <= (state_sync_esc | set_sync_esc & ~alignes_pair) & ~(clr_sync_esc & ~alignes_pair) & ~rst;
state_nocommerr <= (state_nocommerr | set_nocommerr & ~alignes_pair) & ~(clr_nocommerr & ~alignes_pair) & ~rst;
state_nocomm <= (state_nocomm | set_nocomm & ~alignes_pair) & ~(clr_nocomm & ~alignes_pair) & ~rst;
// state_align is not used, it is handled by OOB
state_align <= (state_align | set_align & ~alignes_pair) & ~clr_align & ~rst;
state_reset <= (state_reset | set_reset ) & ~clr_reset & ~rst;
state_send_rdy <= (state_send_rdy | set_send_rdy & ~alignes_pair) & ~clr_send_rdy & ~rst;
state_send_sof <= (state_send_sof | set_send_sof & ~alignes_pair) & ~clr_send_sof & ~rst;
state_send_data <= (state_send_data | set_send_data & ~alignes_pair) & ~clr_send_data & ~rst;
state_send_rhold <= (state_send_rhold | set_send_rhold & ~alignes_pair) & ~clr_send_rhold & ~rst;
state_send_shold <= (state_send_shold | set_send_shold & ~alignes_pair) & ~clr_send_shold & ~rst;
state_send_crc <= (state_send_crc | set_send_crc & ~alignes_pair) & ~clr_send_crc & ~rst;
state_send_eof <= (state_send_eof | set_send_eof & ~alignes_pair) & ~clr_send_eof & ~rst;
state_wait <= (state_wait | set_wait & ~alignes_pair) & ~clr_wait & ~rst;
state_rcvr_wait <= (state_rcvr_wait | set_rcvr_wait & ~alignes_pair) & ~clr_rcvr_wait & ~rst;
state_rcvr_rdy <= (state_rcvr_rdy | set_rcvr_rdy & ~alignes_pair) & ~clr_rcvr_rdy & ~rst;
state_rcvr_data <= (state_rcvr_data | set_rcvr_data & ~alignes_pair) & ~clr_rcvr_data & ~rst;
state_rcvr_rhold <= (state_rcvr_rhold | set_rcvr_rhold & ~alignes_pair) & ~clr_rcvr_rhold & ~rst;
state_rcvr_shold <= (state_rcvr_shold | set_rcvr_shold & ~alignes_pair) & ~clr_rcvr_shold & ~rst;
state_rcvr_eof <= (state_rcvr_eof | set_rcvr_eof & ~alignes_pair) & ~clr_rcvr_eof & ~rst;
state_rcvr_goodcrc <= (state_rcvr_goodcrc | set_rcvr_goodcrc & ~alignes_pair) & ~clr_rcvr_goodcrc & ~rst;
state_rcvr_goodend <= (state_rcvr_goodend | set_rcvr_goodend & ~alignes_pair) & ~clr_rcvr_goodend & ~rst;
state_rcvr_badend <= (state_rcvr_badend | set_rcvr_badend & ~alignes_pair) & ~clr_rcvr_badend & ~rst;
state_align <= (state_align | set_align & ~alignes_pair) & ~(clr_align & ~alignes_pair) & ~rst;
state_reset <= (state_reset | set_reset ) & ~ clr_reset & ~rst;
state_send_rdy <= (state_send_rdy | set_send_rdy & ~alignes_pair) & ~(clr_send_rdy & ~alignes_pair) & ~rst;
state_send_sof <= (state_send_sof | set_send_sof & ~alignes_pair) & ~(clr_send_sof & ~alignes_pair) & ~rst;
state_send_data <= (state_send_data | set_send_data & ~alignes_pair) & ~(clr_send_data & ~alignes_pair) & ~rst;
state_send_rhold <= (state_send_rhold | set_send_rhold & ~alignes_pair) & ~(clr_send_rhold & ~alignes_pair) & ~rst;
state_send_shold <= (state_send_shold | set_send_shold & ~alignes_pair) & ~(clr_send_shold & ~alignes_pair) & ~rst;
state_send_crc <= (state_send_crc | set_send_crc & ~alignes_pair) & ~(clr_send_crc & ~alignes_pair) & ~rst;
state_send_eof <= (state_send_eof | set_send_eof & ~alignes_pair) & ~(clr_send_eof & ~alignes_pair) & ~rst;
state_wait <= (state_wait | set_wait & ~alignes_pair) & ~(clr_wait & ~alignes_pair) & ~rst;
state_rcvr_wait <= (state_rcvr_wait | set_rcvr_wait & ~alignes_pair) & ~(clr_rcvr_wait & ~alignes_pair) & ~rst;
state_rcvr_rdy <= (state_rcvr_rdy | set_rcvr_rdy & ~alignes_pair) & ~(clr_rcvr_rdy & ~alignes_pair) & ~rst;
state_rcvr_data <= (state_rcvr_data | set_rcvr_data & ~alignes_pair) & ~(clr_rcvr_data & ~alignes_pair) & ~rst;
state_rcvr_rhold <= (state_rcvr_rhold | set_rcvr_rhold & ~alignes_pair) & ~(clr_rcvr_rhold & ~alignes_pair) & ~rst;
state_rcvr_shold <= (state_rcvr_shold | set_rcvr_shold & ~alignes_pair) & ~(clr_rcvr_shold & ~alignes_pair) & ~rst;
state_rcvr_eof <= (state_rcvr_eof | set_rcvr_eof & ~alignes_pair) & ~(clr_rcvr_eof & ~alignes_pair) & ~rst;
state_rcvr_goodcrc <= (state_rcvr_goodcrc | set_rcvr_goodcrc & ~alignes_pair) & ~(clr_rcvr_goodcrc & ~alignes_pair) & ~rst;
state_rcvr_goodend <= (state_rcvr_goodend | set_rcvr_goodend & ~alignes_pair) & ~(clr_rcvr_goodend & ~alignes_pair) & ~rst;
state_rcvr_badend <= (state_rcvr_badend | set_rcvr_badend & ~alignes_pair) & ~(clr_rcvr_badend & ~alignes_pair) & ~rst;
end
// flag if incoming request to terminate current transaction came from TL
......
host/oob.v
View file @ 50ca592a
......@@ -43,10 +43,8 @@ module oob #(
)
(
output reg [11:0] debug,
// sata clk = usrclk2
input wire clk,
// reset oob
input wire rst,
input wire clk, // sata clk = usrclk2
input wire rst, // reset oob
// oob responses
input wire rxcominitdet_in,
input wire rxcomwakedet_in,
......@@ -55,50 +53,40 @@ module oob #(
output wire txcominit,
output wire txcomwake,
output wire txelecidle,
// partial tx reset
output wire txpcsreset_req,
output wire txpcsreset_req, // partial tx reset
input wire recal_tx_done,
// rx reset (after rxelecidle -> 0)
output wire rxreset_req,
output wire rxreset_req, // rx reset (after rxelecidle -> 0)
input wire rxreset_ack,
// input data stream (if any data during OOB setting => ignored)
input wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_in,
// Andrey: adding new signal and state - after RX is operational try re-align clock
output wire clk_phase_align_req, // Request GTX to align SIPO parallel clock and user- provided RXUSRCLK
input wire clk_phase_align_ack, // GTX aligned clock phase (DEBUG - not always clear when it works or not)
input wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_in, // input data stream (if any data during OOB setting => ignored)
input wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in,
// output data stream to gtx
output wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_out,
output wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_out, // output data stream to gtx
output wire [DATA_BYTE_WIDTH - 1:0] txcharisk_out,
// input data from gtx
input wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in,
input wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_in,
// bypassed data from gtx
output wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_out,
output wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out,
// oob sequence needs to be issued
input wire oob_start,
// connection established, all further data is valid
output wire oob_done,
// oob can't handle new start request
output wire oob_busy,
input wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in, // input data from gtx
input wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_in,
// doc p265, link is established after 3back-to-back non-ALIGNp
output wire link_up,
// link goes down - if rxelecidle
output wire link_down,
output wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_out, // bypassed data from gtx
output wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out,
// the device itself sends cominit
output wire cominit_req,
// allow to respond to cominit
input wire cominit_allow,
input wire oob_start, // oob sequence needs to be issued
output wire oob_done, // connection established, all further data is valid
output wire oob_busy, // oob can't handle new start request
output wire link_up, // doc p265, link is established after 3back-to-back non-ALIGNp
output wire link_down, // link goes down - if rxelecidle
output wire cominit_req, // the device itself sends cominit
input wire cominit_allow, // allow to respond to cominit
// status information to handle by a control block if any exists
// incompatible host-device speed grades (host cannot lock to alignp)
output wire oob_incompatible,
// timeout in an unexpected place
output wire oob_error,
// noone responds to our cominits
output wire oob_silence
output wire oob_incompatible, // incompatible host-device speed grades (host cannot lock to alignp)
output wire oob_error, // timeout in an unexpected place
output wire oob_silence // noone responds to our cominits
,output debug_detected_alignp
......@@ -136,6 +124,12 @@ assign debug_detected_alignp = detected_alignp;
localparam [19:0] CLK_TO_TIMER_CONTRIB = CLK_SPEED_GRADE == 1 ? 20'h4 :
CLK_SPEED_GRADE == 2 ? 20'h2 :
CLK_SPEED_GRADE == 4 ? 20'h1 : 20'h1;
localparam RXDLYSRESET_CYCLES = 5; // minimum - 50ns
reg [RXDLYSRESET_CYCLES-1:0] rxdlysreset_r;
assign clk_phase_align_req = rxdlysreset_r[RXDLYSRESET_CYCLES-1];
`ifdef SIMULATION
localparam [19:0] TIMER_LIMIT = 19'd20000;
`else
......@@ -172,6 +166,7 @@ reg [9:0] rxcom_timer;
localparam COMINIT_DONE_TIME = 896; // 300Mhz cycles
localparam COMWAKE_DONE_TIME = 448; // 300Mhz cycles
// wait until rxelecidle is not stable (more or less) deasserted
// let's say, if rxelecidle = 0 longer, than 2 comwake burst duration (2 * 106.7 ns), elecidle is stable and we're receiving some data
// 2 * 106.7ns = 64 clock cycles @ 300 MHz, 32 @ 150, 16 @ 75
......@@ -188,6 +183,8 @@ reg state_recal_tx;
reg state_wait_eidle;
reg state_wait_rxrst;
reg state_wait_align;
reg state_wait_clk_align;
reg state_wait_align2; // after clocks aligned
reg state_wait_synp;
reg state_wait_linkup;
reg state_error;
......@@ -198,6 +195,8 @@ wire set_recal_tx;
wire set_wait_eidle;
wire set_wait_rxrst;
wire set_wait_align;
wire set_wait_clk_align;
wire set_wait_align2;
wire set_wait_synp;
wire set_wait_linkup;
wire set_error;
......@@ -207,19 +206,40 @@ wire clr_recal_tx;
wire clr_wait_eidle;
wire clr_wait_rxrst;
wire clr_wait_align;
wire clr_wait_clk_align;
wire clr_wait_align2;
wire clr_wait_synp;
wire clr_wait_linkup;
wire clr_error;
assign state_idle = ~state_wait_cominit & ~state_wait_comwake & ~state_wait_align & ~state_wait_synp & ~state_wait_linkup & ~state_error & ~state_recal_tx & ~state_wait_rxrst & ~state_wait_eidle;
always @ (posedge clk) begin
if (rst || rxelecidle) rxdlysreset_r <= 0;
else if (set_wait_clk_align) rxdlysreset_r <= ~0;
else rxdlysreset_r <= rxdlysreset_r << 1;
end
assign state_idle = ~state_wait_cominit &
~state_wait_comwake &
~state_wait_align &
~state_wait_clk_align &
~state_wait_align2 &
~state_wait_synp &
~state_wait_linkup &
~state_error &
~state_recal_tx &
~state_wait_rxrst &
~state_wait_eidle;
always @ (posedge clk)
begin
state_wait_cominit <= (state_wait_cominit | set_wait_cominit) & ~clr_wait_cominit & ~rst;
state_wait_comwake <= (state_wait_comwake | set_wait_comwake) & ~clr_wait_comwake & ~rst;
state_wait_cominit <= (state_wait_cominit | set_wait_cominit ) & ~clr_wait_cominit & ~rst;
state_wait_comwake <= (state_wait_comwake | set_wait_comwake ) & ~clr_wait_comwake & ~rst;
state_recal_tx <= (state_recal_tx | set_recal_tx ) & ~clr_recal_tx & ~rst;
state_wait_eidle <= (state_wait_eidle | set_wait_eidle ) & ~clr_wait_eidle & ~rst;
state_wait_rxrst <= (state_wait_rxrst | set_wait_rxrst ) & ~clr_wait_rxrst & ~rst;
state_wait_align <= (state_wait_align | set_wait_align ) & ~clr_wait_align & ~rst;
state_wait_clk_align <= (state_wait_clk_align | set_wait_clk_align) & ~clr_wait_clk_align & ~rst;
state_wait_align2 <= (state_wait_align2 | set_wait_align2 ) & ~clr_wait_align2 & ~rst;
state_wait_synp <= (state_wait_synp | set_wait_synp ) & ~clr_wait_synp & ~rst;
state_wait_linkup <= (state_wait_linkup | set_wait_linkup ) & ~clr_wait_linkup & ~rst;
state_error <= (state_error | set_error ) & ~clr_error & ~rst;
......@@ -231,16 +251,32 @@ assign set_recal_tx = state_wait_comwake & rxcomwakedet_l & rxcomwake_done;
assign set_wait_eidle = state_recal_tx & recal_tx_done;
assign set_wait_rxrst = state_wait_eidle & eidle_timer_done;
assign set_wait_align = state_wait_rxrst & rxreset_ack;
assign set_wait_clk_align = state_wait_align & (detected_alignp_r);
assign set_wait_align2 = state_wait_clk_align & clk_phase_align_ack;
//assign set_wait_synp = state_wait_align & detected_alignp;
assign set_wait_synp = state_wait_align & (detected_alignp_r); // N previous were both ALIGNp
assign set_wait_synp = state_wait_align2 & (detected_alignp_r); // N previous were both ALIGNp
assign set_wait_linkup = state_wait_synp & detected_syncp;
assign set_error = timer_fin & (state_wait_cominit | state_wait_comwake | state_recal_tx | state_wait_eidle | state_wait_rxrst | state_wait_align | state_wait_synp/* | state_wait_linkup*/);
assign set_error = timer_fin & (state_wait_cominit |
state_wait_comwake |
state_recal_tx |
state_wait_eidle |
state_wait_rxrst |
state_wait_align |
state_wait_clk_align |
state_wait_align2 |
state_wait_synp/* | state_wait_linkup*/);
assign clr_wait_cominit = set_wait_comwake | set_error;
assign clr_wait_comwake = set_recal_tx | set_error;
assign clr_recal_tx = set_wait_eidle | set_error;
assign clr_wait_eidle = set_wait_rxrst | set_error;
assign clr_wait_rxrst = set_wait_align | set_error;
assign clr_wait_align = set_wait_synp | set_error;
assign clr_wait_align = set_wait_clk_align | set_error;
assign clr_wait_clk_align = set_wait_align2 | set_error;
assign clr_wait_align2 = set_wait_synp | set_error;
assign clr_wait_synp = set_wait_linkup | set_error;
assign clr_wait_linkup = state_wait_linkup; //TODO not so important, but still have to trace 3 back-to-back non alignp primitives
assign clr_error = state_error;
......
host/oob_ctrl.v
View file @ 50ca592a
......@@ -51,6 +51,10 @@ module oob_ctrl #(
input wire recal_tx_done, // input wire
output wire rxreset_req, // output wire // rx reset (after rxelecidle -> 0)
input wire rxreset_ack, // input wire
// Andrey: adding new signal and state - after RX is operational try re-align clock
output wire clk_phase_align_req, // Request GTX to align SIPO parallel clock and user- provided RXUSRCLK
input wire clk_phase_align_ack, // GTX aligned clock phase (DEBUG - not always clear when it works or not)
input wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_in, // output[31:0] wire // input data stream (if any data during OOB setting => ignored)
input wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in, // output[3:0] wire // input data stream (if any data during OOB setting => ignored)
output wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_out, // output[31:0] wire // output data stream to gtx
......@@ -137,11 +141,13 @@ oob
.rxelecidle_in (rxelecidle_in), // input wire // oob responses
.txcominit (txcominit), // output wire // oob issues
.txcomwake (txcomwake), // output wire // oob issues
.txelecidle (txelecidle_inner), // output wire // oob issues
.txelecidle (txelecidle_inner),// output wire // oob issues
.txpcsreset_req (txpcsreset_req), // output wire
.recal_tx_done (recal_tx_done), // input wire
.rxreset_req (rxreset_req), // output wire
.rxreset_ack (rxreset_ack), // input wire
.clk_phase_align_req (clk_phase_align_req), // output wire
.clk_phase_align_ack (clk_phase_align_ack), // input wire
.txdata_in (txdata_in), // input [31:0] wire // input data stream (if any data during OOB setting => ignored)
.txcharisk_in (txcharisk_in), // input [3:0] wire // input data stream (if any data during OOB setting => ignored)
.txdata_out (txdata_out), // output [31:0] wire // output data stream to gtx
......
host/sata_phy.v
View file @ 50ca592a
......@@ -97,6 +97,7 @@ wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in;
wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out;
wire [DATA_BYTE_WIDTH - 1:0] rxdisperr;
wire [DATA_BYTE_WIDTH - 1:0] rxnotintable;
wire [1:0] txbufstatus;
assign ll_err_out = rxdisperr | rxnotintable;
......@@ -119,6 +120,10 @@ wire txpcsreset_req;
wire recal_tx_done;
wire rxreset_req;
wire rxreset_ack;
wire clk_phase_align_req;
wire clk_phase_align_ack;
wire rxreset_oob;
// elastic buffer status signals TODO
//wire rxelsfull;
......@@ -159,6 +164,9 @@ oob_ctrl oob_ctrl(
.rxreset_req (rxreset_req),
.rxreset_ack (rxreset_ack),
.clk_phase_align_req (clk_phase_align_req), // output wire
.clk_phase_align_ack (clk_phase_align_ack), // input wire
// input data stream (if any data during OOB setting => ignored)
.txdata_in (txdata_in),
.txcharisk_in (txcharisk_in),
......@@ -313,19 +321,43 @@ always @ (posedge clk or posedge extrst)
// issue partial tx reset to restore functionality after oob sequence. Let it lasts 8 clock lycles
reg [3:0] txpcsreset_cnt;
wire txpcsreset_stop;
// issue partial tx reset to restore functionality after oob sequence. Let it lasts 8 clock cycles
// Not enough or too early (after txelctidle?) txbufstatus shows overflow
`ifdef OLD_TXPCSRESET
reg [3:0] txpcsreset_cnt;
wire txpcsreset_stop;
assign txpcsreset_stop = txpcsreset_cnt[3];
assign txpcsreset = txpcsreset_req & ~txpcsreset_stop & gtx_configured;
assign recal_tx_done = txpcsreset_stop & gtx_ready;
assign txpcsreset_stop = txpcsreset_cnt[3];
assign txpcsreset = txpcsreset_req & ~txpcsreset_stop & gtx_configured;
assign recal_tx_done = txpcsreset_stop & gtx_ready;
always @ (posedge clk or posedge extrst)
// txpcsreset_cnt <= extrst | rst | ~txpcsreset_req ? 4'h0 : txpcsreset_stop ? txpcsreset_cnt : txpcsreset_cnt + 1'b1;
always @ (posedge clk or posedge extrst)
// txpcsreset_cnt <= extrst | rst | ~txpcsreset_req ? 4'h0 : txpcsreset_stop ? txpcsreset_cnt : txpcsreset_cnt + 1'b1;
if (extrst) txpcsreset_cnt <= 1;
else txpcsreset_cnt <= rst | ~txpcsreset_req ? 4'h0 : txpcsreset_stop ? txpcsreset_cnt : txpcsreset_cnt + 1'b1;
`else // OLD_TXPCSRESET
localparam TXPCSRESET_CYCLES = 100;
reg txpcsreset_r;
reg [7:0] txpcsreset_cntr;
reg recal_tx_done_r;
assign recal_tx_done = recal_tx_done_r;
assign txpcsreset = txpcsreset_r;
always @ (posedge clk) begin
if (rst || (txpcsreset_cntr == 0)) txpcsreset_r <= 0;
else if (txpcsreset_req) txpcsreset_r <= 1;
if (rst) txpcsreset_cntr <= 0;
else if (txpcsreset_req) txpcsreset_cntr <= TXPCSRESET_CYCLES;
else if (txpcsreset_cntr != 0) txpcsreset_cntr <= txpcsreset_cntr - 1;
if (rst || txelecidle || txpcsreset_r) recal_tx_done_r <= 0;
else if (txresetdone) recal_tx_done_r <= 1;
end
`endif // OLD_TXPCSRESET
// issue rx reset to restore functionality after oob sequence. Let it lasts 8 clock lycles
reg [3:0] rxreset_oob_cnt;
wire rxreset_oob_stop;
......@@ -460,6 +492,10 @@ gtx_wrap
.rxelecidle (rxelecidle), // output wire
.rxresetdone (rxresetdone), // output wire
.txreset (txreset), // input wire
.clk_phase_align_req(clk_phase_align_req), // output wire
.clk_phase_align_ack(clk_phase_align_ack), // input wire
.txusrclk (txusrclk), // input wire
.txusrclk2 (txusrclk2), // input wire
.txelecidle (txelecidle), // input wire
......@@ -481,7 +517,8 @@ gtx_wrap
.dbg_rxphaligndone (dbg_rxphaligndone),
.dbg_rx_clocks_aligned(dbg_rx_clocks_aligned),
.dbg_rxcdrlock (dbg_rxcdrlock) ,
.dbg_rxdlysresetdone(dbg_rxdlysresetdone)
.dbg_rxdlysresetdone(dbg_rxdlysresetdone),
.txbufstatus (txbufstatus[1:0])
);
......@@ -542,6 +579,32 @@ always @ (posedge clk) begin
else if (debug_error_r) debug_cntr6 <= debug_cntr6 + 1;
end
reg [15:0] dbg_clk_align_cntr;
reg dbg_clk_align_wait;
//reg dbg_rxphaligndone_down;
//reg dbg_rxphaligndone_second;
always @ (posedge clk) begin
if (rxelecidle || clk_phase_align_ack) dbg_clk_align_wait <= 0;
else if (clk_phase_align_req) dbg_clk_align_wait <= 1;
if (rxelecidle) dbg_clk_align_cntr <= 0;
else if (dbg_clk_align_wait) dbg_clk_align_cntr <= dbg_clk_align_cntr +1;
/*
if (rxelecidle || dbg_rxphaligndone_second) dbg_clk_align_wait <= 0;
else if (clk_phase_align_req) dbg_clk_align_wait <= 1;
if (rxelecidle) dbg_rxphaligndone_down <= 0;
else if (dbg_rx_clocks_aligned && !dbg_rxphaligndone) dbg_rxphaligndone_down <= 1;
if (rxelecidle) dbg_rxphaligndone_second <= 0;
else if (dbg_rxphaligndone_down && dbg_rxphaligndone) dbg_rxphaligndone_second <= 1;
*/
end
/*
assign debug_sata[ 3: 0] = debug_cntr1;
assign debug_sata[ 7: 4] = debug_cntr2;
......@@ -555,9 +618,17 @@ assign debug_sata[17] = txreset;
assign debug_sata[18] = txpcsreset;
assign debug_sata[19] = txelecidle;
assign debug_sata[23:20] = debug_cntr4;
.clk_phase_align_req(clk_phase_align_req), // output wire
.clk_phase_align_ack(clk_phase_align_ack), // input wire
*/
//assign phy_ready = link_state & gtx_ready & rxbyteisaligned;
//assign debug_sata = {debug_cntr6,debug_cntr5};
assign debug_sata = {25'b0, dbg_rxdlysresetdone, rxelecidle, dbg_rxcdrlock, rxelsfull, rxelsempty, dbg_rxphaligndone, dbg_rx_clocks_aligned};
//assign debug_sata = {8'b0, dbg_clk_align_cntr, 1'b0, dbg_rxdlysresetdone, rxelecidle, dbg_rxcdrlock, rxelsfull, rxelsempty, dbg_rxphaligndone, dbg_rx_clocks_aligned};
assign debug_sata = {8'b0, dbg_clk_align_cntr, txbufstatus[1:0], rxelecidle, dbg_rxcdrlock, rxelsfull, rxelsempty, dbg_rxphaligndone, dbg_rx_clocks_aligned};
endmodule
system_defines.vh
View file @ 50ca592a
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
`define ALIGN_CLOCKS
`define USE_DATASCOPE
`define PRELOAD_BRAMS
`define AHCI_SATA 1
// Enviroment-dependent options
......
tb/tb_ahci.tf
View file @ 50ca592a
......@@ -1059,6 +1059,17 @@ initial begin //Host
/// setup_pio_read_identify_command_multi4(1,27,64,83); // prdt interrupt for entry 0
setup_pio_read_identify_command_multi4(1,64,63,64); // prdt interrupt for entry 0
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
`ifdef TEST_ABORT_COMMAND
// Abort command by clearing ST
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, 0-> ST
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
repeat (300) @(posedge CLK);
// maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, 0-> ST
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
// maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, 0-> ST
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
`endif
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup)
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear that interrupt
......@@ -1069,6 +1080,15 @@ initial begin //Host
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear PS interrupt
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts
wait (~IRQ);
// Print datascope - contents of the last CFIS sent
maxigp1_print ('h1000,"DATASCOPE 0"); //
maxigp1_print ('h1004,"DATASCOPE 1"); //
maxigp1_print ('h1008,"DATASCOPE 2"); //
maxigp1_print ('h100c,"DATASCOPE 3"); //
maxigp1_print ('h1010,"DATASCOPE 4"); //
maxigp1_print ('h1014,"DATASCOPE 5"); //
maxigp1_print ('h1018,"DATASCOPE 6"); //
maxigp1_print ('h101c,"DATASCOPE 7"); //
// sysmem_print ('h1e81,'h180); // for shifted
sysmem_print ('h1e80,'h180); // Compact dump of "system memory" in hex word format
......@@ -1087,6 +1107,17 @@ initial begin //Host
TESTBENCH_TITLE = "DMA transfer to device completed";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
repeat (50) @(posedge CLK);
// Print datascope - contents of the last CFIS sent
maxigp1_print ('h1000,"DATASCOPE 0"); //
maxigp1_print ('h1004,"DATASCOPE 1"); //
maxigp1_print ('h1008,"DATASCOPE 2"); //
maxigp1_print ('h100c,"DATASCOPE 3"); //
maxigp1_print ('h1010,"DATASCOPE 4"); //
maxigp1_print ('h1014,"DATASCOPE 5"); //
maxigp1_print ('h1018,"DATASCOPE 6"); //
maxigp1_print ('h101c,"DATASCOPE 7"); //
/*
// Reset port
maxigp1_print ('h3ff << 2,"DEBUG_REGISTER");
......
tb_ahci_01.sav
View file @ 50ca592a
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Thu Feb 4 19:47:54 2016
[*] Sat Feb 6 02:12:42 2016
[*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160204124302694.fst"
[dumpfile_mtime] "Thu Feb 4 19:44:22 2016"
[dumpfile_size] 9978698
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160205183420632.fst"
[dumpfile_mtime] "Sat Feb 6 01:35:47 2016"
[dumpfile_size] 10099447
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 0
[timestart] 22906600
[size] 1823 1180
[pos] 1959 27
*-23.683727 4778998 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] 1917 0
*-15.467498 23097166 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.linkMonitorFIS.
......@@ -57,12 +57,15 @@
[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[treeopen] tb_ahci.simul_axi_read_i.
[sst_width] 362
[signals_width] 374
[sst_width] 290
[signals_width] 278
[sst_expanded] 1
[sst_vpaned_height] 568
[sst_vpaned_height] 573
@820
tb_ahci.TESTBENCH_TITLE[639:0]
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_cntr[8:0]
@820
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
tb_ahci.DEVICE_TITLE[639:0]
tb_ahci.dev.DEV_TITLE[639:0]
......@@ -111,7 +114,14 @@ tb_ahci.simul_axi_master_rdaddr_i.arvalid_out
-axi_read
@c00200
-axi_ahci_regs
@800022
@800028
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.datascope_sel[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.datascope_sel[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.datascope_sel[1:0]
@1001200
-group_end
@c00022
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
......@@ -146,7 +156,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in[31:0]
@1001200
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_rst
......@@ -160,10 +170,23 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wen_r
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_addr[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.aclk
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.dev_ready
@800022
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
@1001200
-group_end
@800028
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_ren[1:0]
@28
......@@ -173,6 +196,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_ren[1:0]
-group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_rdata_r[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.bram_rdata[31:0]
@200
-
@28
......@@ -187,7 +211,6 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wen
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wen_r
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_waddr_r[9:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_waddr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb[3:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_addr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wdata[31:0]
......@@ -366,9 +389,6 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.araddr[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.arvalid
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.arready
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.bram_raddr[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.dev_ready
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.start_burst
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.bram_ren
......@@ -624,7 +644,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.serr[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pxci0_clear
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pxci_changed
@800022
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
......@@ -633,9 +653,9 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_changed[5:0]
@1001200
@1401200
-group_end
@800022
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
......@@ -644,7 +664,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[5:0]
@1001200
@1401200
-group_end
@200
-
......@@ -890,6 +910,11 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen3
@c00200
-axi_ahci_regs
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_din[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_we
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_reset_cntr[8:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_arst
......@@ -902,6 +927,19 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.set_port_rst
-axi_ahci_regs
@c00200
-ahci_fsm
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pcmd_st_cleared
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.asynq_rq
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
@c00028
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
@1401200
-group_end
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
@28
......@@ -969,7 +1007,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_end_w
-
@1401200
-other
@c00200
@800200
-actions
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pfsm_started
......@@ -984,7 +1022,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.sirq_PC
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.get_rfis
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_sig
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.update_err_sts
@1401200
@1000200
-actions
@c00200
-conditions
......@@ -1128,6 +1166,20 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@c00200
-ahci_fis_receive
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_data_in_type[1:0]
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_addr[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_we
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_data[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.pUpdateSig_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.wreg_we_r
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.reg_addr_r[9:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.xfer_cntr[31:2]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.xfer_cntr_zero
......@@ -2544,7 +2596,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rst
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_reset
@800022
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
......@@ -2586,8 +2638,44 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.select_prim[15:0]
@1401200
-group_end
@1001200
-group_end
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_send_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rst
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.clr_send_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair
@c00200
-states
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_idle
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_nocomm
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_nocommerr
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_badend
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_eof
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_goodcrc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_goodend
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_rdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_rhold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_shold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_wait
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_crc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_eof
[color] 2
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_rdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_rhold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_shold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_send_sof
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_sync_esc
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_wait
@1401200
-states
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.link_reset
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_align
......@@ -2610,7 +2698,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_timer[8:0]
@1401200
-group_end
@800200
@c00200
-oob
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.link_state
......@@ -2632,7 +2720,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_isk_in_r[3:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.phy_data_in_r[31:0]
@200
-
@800200
@c00200
-states
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.rst
......@@ -2646,7 +2734,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_eidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_linkup
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_rxrst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_synp
@1000200
@1401200
-states
-oob
@c00200
......@@ -2846,11 +2934,17 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy
-link
@c00200
-phy
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txdata[31:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txresetdone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_ready
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txuserrdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txpcsreset_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txpcsreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txoutclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txreset
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txpcsreset_cnt[3:0]
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.debug_sata[31:0]
@28
......@@ -3009,7 +3103,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtx_comma_align.comma_detec
-
@1401200
-comma
@c00201
@c00200
-elastic_slow
@28
tb_ahci.elastic1632_slow_i.wclk
......@@ -3113,7 +3207,7 @@ tb_ahci.elastic1632_slow_i.skip_rclk
tb_ahci.elastic1632_slow_i.waddr[4:0]
tb_ahci.elastic1632_slow_i.raddr[4:0]
tb_ahci.elastic1632_slow_i.dbg_diff[4:0]
@1401201
@1401200
-elastic_slow
@c00200
-elastic_fast
......@@ -3180,15 +3274,102 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready
-
@800200
-oob
-states
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_idle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_cominit
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_comwake
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_recal_tx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_eidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_rxrst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_clk_align
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_align2
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_synp
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.state_wait_linkup
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.dbg_clk_align_wait
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.clk_phase_align_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.clk_phase_align_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.dbg_rx_clocks_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.dbg_rxphaligndone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.phy_ready
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.dbg_clk_align_cntr[15:0]
@1000200
-states
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_sata[31:0]
@1401200
-group_end
@200
-
@1000200
-oob
@1401200
-oob_ctrl
@800200
@c00200
-gtx
@800200
-ttxdata_resynchro
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.arst
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_out[38:0]
@8028
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.waddr[2:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.raddr[2:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.rclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.re
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.rrst[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.srst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.valid
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.wclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.we
@1000200
-ttxdata_resynchro
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resync_strobe
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resync_valid
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txuserrdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txpcsreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rx_clocks_aligned
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_triggered
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.state_aligned
......@@ -3216,15 +3397,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_g
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.RXCDRLOCK
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset_cntr[2:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset_cntr[2:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset_cntr[2:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset_cntr[2:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.comma
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.wrap_rxreset_
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxbyteisaligned
......@@ -3260,7 +3432,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
-
@1401200
-gtx8x10enc
@1000200
-gtx
@c00200
-device
......@@ -3315,5 +3486,80 @@ tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXN
tb_ahci.dev.linkSendPrim.type[111:0]
@1401200
-device
@800200
-datascope
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.fis_data_valid
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_stb
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_w
@c00023
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0]
@1401203
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.fsnd_cfis_xmit
@200
-
@22
tb_ahci.dut.sata_top.ahci_top_i.h2d_data[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.h2d_ready
tb_ahci.dut.sata_top.ahci_top_i.h2d_type[1:0]
tb_ahci.dut.sata_top.ahci_top_i.h2d_valid
@22
tb_ahci.dut.sata_top.ahci_top_i.data_out_dwords[11:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_clk
@c00022
tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@1401200
-group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_run[1:0]
tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_we
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_cntr[8:0]
@1000200
-datascope
[pattern_trace] 1
[pattern_trace] 0
wrapper/GTXE2_GPL.v
View file @ 50ca592a
......@@ -3008,9 +3008,9 @@ localparam RXCDRLOCK_DELAY = 10; // Refclk periods
localparam RXDLYSRESET_MIN_DURATION = 50; // ns
localparam RXDLYSRESETDONE_DELAY = 10;
localparam RXDLYSRESETDONE_DURATION = 7; // 100ns
localparam RXPHALIGNDONE_DELAY1 = 15;
localparam RXPHALIGNDONE_DELAY1 = 15; // 0.45 usec from the end of reset (measured)
localparam RXPHALIGNDONE_DURATION1 = 7;
localparam RXPHALIGNDONE_DELAY2 = 10;
localparam RXPHALIGNDONE_DELAY2 = 311; // 4.9 usec from the end of reset (measured)
initial forever @ (posedge (reset || RXELECIDLE)) begin
rxcdrlock <= 1'b0;
......
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