Commit 50ca592a authored by Andrey Filippov's avatar Andrey Filippov
Browse files

got identify PIO data from the SSD

parent 0a15e1e3

.project

+17 −17
Original line number Diff line number Diff line
@@ -52,87 +52,87 @@ 
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ahci/ahci_ctrl_stat.v

+3 −2
Original line number Diff line number Diff line
@@ -467,7 +467,8 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; 
        else if (pfsm_started)        pfsm_started_r <= 1;                  

        

        if (!pfsm_started_r)          pcmd_st_cleared <= 0;

        else if (swr_HBA_PORT__PxCMD) pcmd_st_cleared <= |(HBA_PORT__PxCMD__ST__MASK & PxCMD_r & ~soft_write_data);

//        else if (swr_HBA_PORT__PxCMD) pcmd_st_cleared <= |(HBA_PORT__PxCMD__ST__MASK & PxCMD_r & ~soft_write_data);

        else                          pcmd_st_cleared <= swr_HBA_PORT__PxCMD && (|(HBA_PORT__PxCMD__ST__MASK & PxCMD_r & ~soft_write_data));

                          

    end
@@ -487,7 +488,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; 
                     ({32{update_HBA_PORT__PxCMD}}  & PxCMD_r) |

                     ({32{update_HBA_PORT__PxCI}}   & {31'b0, pxci0});

                     

        regs_we <=   update_GHC__IS || update_HBA_PORT__PxIS || update_HBA_PORT__PxSSTS || update_HBA_PORT__PxSERR | update_HBA_PORT__PxCMD;

        regs_we <=   update_GHC__IS || update_HBA_PORT__PxIS || update_HBA_PORT__PxSSTS || update_HBA_PORT__PxSERR | update_HBA_PORT__PxCMD || update_HBA_PORT__PxCI;

        

        // pending updates

        if      (mrst)                                         pxci_changed <= 1; //0;

ahci/ahci_fis_transmit.v

+20 −2
Original line number Diff line number Diff line
@@ -100,6 +100,8 @@ module ahci_fis_transmit #( 
    output                        todev_valid,    // output register full

    input                         todev_ready     // send FIFO has room for data (>= 8? dwords)

    

    ,output                [9:0] debug_01

    

    // Add a possiblity to flush any data to FIFO if error was detected after data went there?

);

    localparam CLB_OFFS32 = 'h200; //  # In the second half of the register space (0x800..0xbff - 1KB)
@@ -152,6 +154,7 @@ module ahci_fis_transmit #( 
    

    wire                     ct_re_w; // next cycle will be ct_re;

    reg  [READ_CT_LATENCY:0] ct_re_r;

    

    wire                     ct_stb = ct_re_r[READ_CT_LATENCY];

    

    reg                      fis_dw_first;
@@ -204,7 +207,9 @@ module ahci_fis_transmit #( 
    // What else to wait for when

    assign fis_data_valid = ct_stb || (!dma_ct_busy && dx_fis_pend_r); // no wait write to output register 'todev_data', ct_re_r[0] is throttled according to FIFO room availability

    

    assign ct_re_w = todev_ready && ((cfis_acmd_left_r[4:1] != 0) || (cfis_acmd_left_r[0] && !ct_re_r[0]));  // Later add more sources

///    assign ct_re_w = todev_ready &&  ((cfis_acmd_left_r[4:1] != 0) || (cfis_acmd_left_r[0] && !ct_re_r[0]));  // Later add more sources

    assign ct_re_w = todev_ready &&  acfis_xmit_busy_r && ((cfis_acmd_left_r[4:1] != 0) || (cfis_acmd_left_r[0] && !ct_re_r[0]));  // Later add more sources

    //

    assign fis_dw_last = (cfis_acmd_left_out_r == 1);

    assign fis_data_type = {fis_dw_last, (write_or_w && dx_fis_pend_r) | (fis_dw_first && ct_stb)};
@@ -219,6 +224,11 @@ module ahci_fis_transmit #( 
    

// When watching for FIS end, do not fill/use output register in the same cycle    



    reg [3:0] dbg_was_ct_re_r;

    reg [4:0] dbg_was_cfis_acmd_left_r;

    

    

    

    always @ (posedge mclk) begin

        // Mutliplex between DMA and FIS output to the output routed to transmit FIFO

        // Count bypassing DMA dwords to generate FIS_last condition?
@@ -308,7 +318,8 @@ module ahci_fis_transmit #( 
       if      (acfis_xmit_start_r) cfis_acmd_left_out_r <= cfis_acmd_left_r;

       else if (ct_stb)             cfis_acmd_left_out_r <= cfis_acmd_left_out_r - 1;

       

       ct_re_r <= {ct_re_r[READ_CT_LATENCY-1:0],ct_re_w};

       if (hba_rst || acfis_xmit_start_w) ct_re_r <= 0;

       else                               ct_re_r <= {ct_re_r[READ_CT_LATENCY-1:0], ct_re_w};

       

       if      (cfis_xmit)   ct_addr <= 0;

       else if (atapi_xmit)  ct_addr <= 'h10; // start of ATAPI area
@@ -369,8 +380,15 @@ module ahci_fis_transmit #( 


       dma_cmd_abort <= done_w && (|dx_err_r);



       if (cfis_xmit) dbg_was_ct_re_r <= {ct_re_r, ct_re_w};

       if (cfis_xmit) dbg_was_cfis_acmd_left_r <= cfis_acmd_left_r;



    end 

    

    assign debug_01 = {dx_fis_pend_r,  ct_re_r, ct_re_w, cfis_acmd_left_r}; // 1,2,5

//    assign debug_01 = {acfis_xmit_start_w,  acfis_xmit_pend_r, dma_ct_busy, fetch_cmd_busy_r, ct_re_w, dbg_was_cfis_acmd_left_r}; // 1,2,5

//    wire                     acfis_xmit_start_w = (cfis_xmit || atapi_xmit || acfis_xmit_pend_r) && !dma_ct_busy && !fetch_cmd_busy_r; // dma_ct_busy no gaps with fetch_cmd_busy

    



endmodule

ahci/ahci_fsm.v

+3 −1
Original line number Diff line number Diff line
@@ -274,6 +274,7 @@ module ahci_fsm 
    reg                      [1:0] async_pend_r; // waiting to process cominit_got

    reg                            async_from_st; // chnge to multi-bit if there will be more sources for async transitions

    wire                           asynq_rq = cominit_got || pcmd_st_cleared;

                                   // OK to wait for some time fsm_act_busy is supposed to never hang up

    wire                           async_ackn = !fsm_preload && async_pend_r[0] && ((fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]);   // OK to process async jump

//    reg                            x_rdy_collision_pend;

    reg                            syncesc_send_pend; // waiting for 'syncesc_send' confiramtion 'syncesc_send_done'
@@ -358,7 +359,8 @@ module ahci_fsm 
        else if   (asynq_rq) async_from_st <= 0;

        

        if (hba_rst) async_pend_r <= 0;

        else async_pend_r <= {async_pend_r[0], asynq_rq | (async_pend_r[0] & ~async_ackn)};  

///        else async_pend_r <= {async_pend_r[0], asynq_rq | (async_pend_r[0] & ~async_ackn)};  

        else async_pend_r <= {async_pend_r[0], (asynq_rq | async_pend_r[0]) & ~async_ackn};  

        

        

//        if (hba_rst || pcmd_cr_set) x_rdy_collision_pend <= 0;

ahci/ahci_sata_layers.v

+2 −1
Original line number Diff line number Diff line
@@ -183,7 +183,8 @@ module ahci_sata_layers #( 
///    assign debug_sata = debug_phy;

    

//    assign debug_sata = {debug_link[31:4],debug_phy[3:0]} ; // 

    assign debug_sata = {debug_link[31:8],debug_phy[7:0]} ; // 

//    assign debug_sata = {debug_link[31:8],debug_phy[7:0]} ; // 

    assign debug_sata = {debug_link[27:20],debug_phy[23:0]} ; // 

    

    assign ll_h2d_last =  (h2d_type_out == H2D_TYPE_FIS_LAST); 

    assign d2h_valid = d2h_nempty;