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Commit 507b1bd3 authored by Andrey Filippov's avatar Andrey Filippov
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more testing with DRP

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.project
View file @ 507b1bd3
......@@ -52,87 +52,87 @@
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160209233437529.log</location>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160209233437529.log</location>
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<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160209233437529.log</location>
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</projectDescription>
ahci/ahci_dma.v
View file @ 507b1bd3
......@@ -273,6 +273,7 @@ module ahci_dma (
reg abort_rq_mclk;
reg abort_busy_mclk;
wire [21:0] abort_debug;
reg rwaddr_rq_r; // next cycle after requesting waddr_data_rq, raddr_data_rq, raddr_ct_rq and raddr_prd_rq (*-pend is valid)
assign afi_wvalid = aborting ? afi_wvalid_abort: afi_wvalid_data;
assign afi_wid = aborting ? afi_wid_abort: afi_id;
......@@ -380,6 +381,9 @@ module ahci_dma (
always @ (posedge hclk) begin
hrst_r <= hrst;
if (hrst) rwaddr_rq_r <= 0;
else rwaddr_rq_r <= raddr_ct_rq || raddr_prd_rq || raddr_data_rq || waddr_data_rq;
addr_data_rq_r <= addr_data_rq_w;
prd_start_hclk_r <= prd_start_hclk;
......@@ -414,7 +418,9 @@ module ahci_dma (
if (hrst) {is_ct_addr, is_prd_addr, is_data_addr} <= 0;
else if (raddr_ct_rq || raddr_prd_rq || wcount_set) {is_ct_addr, is_prd_addr, is_data_addr} <= {raddr_ct_rq, raddr_prd_rq, wcount_set};
if (axi_set_raddr_w || axi_set_waddr_w) begin
/// if (axi_set_raddr_w || axi_set_waddr_w) begin
if (rwaddr_rq_r) begin // first cycle one of the *_pend is set
if (raddr_data_pend || waddr_data_pend) afi_addr <= {data_addr[31:3], 3'b0};
else afi_addr <= {ct_maddr[31:4], 4'b0};
......
ahci/ahci_fsm.v
View file @ 507b1bd3
......@@ -266,11 +266,12 @@ module ahci_fsm
// reg [7:0] conditions;
// wire pre_jump_w = (|async_pend_r) ? async_ackn : |(cond_met_w & fsm_transitions[1]);
wire pre_jump_w = (|async_pend_r) ? async_ackn : (cond_met_w & fsm_transitions[1]);
wire fsm_act_done = get_fis_done ||
wire fsm_act_done_w = get_fis_done ||
xmit_done ||
(syncesc_send_pend && syncesc_send_done) ||
dma_abort_done ||
asynq_rq; // cominit_got || pcmd_st_cleared
reg fsm_act_done; // made later by 1 cycle so the new conditions are latched
wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done
wire fsm_last_act_w = pgm_data[17];
......@@ -340,6 +341,8 @@ module ahci_fsm
was_rst <= hba_rst;
fsm_act_done <= fsm_act_done_w; // delay by 1 clock cycle
fsm_jump <= {fsm_jump[1:0], pre_jump_w | (was_rst & ~hba_rst)};
if (fsm_jump[0]) pgm_addr <= pgm_jump_addr;
......
ahci/ahci_sata_layers.v
View file @ 507b1bd3
......@@ -91,6 +91,16 @@ module ahci_sata_layers #(
output wire txn_out,
input wire rxp_in,
input wire rxn_in,
`ifdef USE_DRP
input drp_rst,
input drp_clk,
input drp_en, // @aclk strobes drp_ad
input drp_we,
input [14:0] drp_addr,
input [15:0] drp_di,
output drp_rdy,
output [15:0] drp_do ,
`endif
output [31:0] debug_phy,
output [31:0] debug_link
......@@ -339,6 +349,16 @@ module ahci_sata_layers #(
.cplllock_debug (),
.usrpll_locked_debug(),
`ifdef USE_DRP
.drp_rst (drp_rst), // input
.drp_clk (drp_clk), // input
.drp_en (drp_en), // input
.drp_we (drp_we), // input
.drp_addr (drp_addr), // input[14:0]
.drp_di (drp_di), // input[15:0]
.drp_rdy (drp_rdy), // output
.drp_do (drp_do), // output[15:0]
`endif
.debug_sata (debug_phy)
,.debug_detected_alignp(debug_detected_alignp)
);
......
ahci/ahci_top.v
View file @ 507b1bd3
......@@ -182,6 +182,14 @@ module ahci_top#(
output irq, // CPU interrupt request
`ifdef USE_DRP
output drp_en, // @aclk strobes drp_ad
output drp_we,
output [14:0] drp_addr,
output [15:0] drp_di,
input drp_rdy,
input [15:0] drp_do,
`endif
input [31:0] debug_in_phy,
input [31:0] debug_in_link
......@@ -708,6 +716,16 @@ module ahci_top#(
.debug_in1 (debug_dma1), // debug_in_link), // input[31:0]
.debug_in2 (debug_in_phy), // input[31:0] // debug from phy/link
.debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
`ifdef USE_DRP
,.drp_en (drp_en), // output reg
.drp_we (drp_we), // output reg
.drp_addr (drp_addr), // output[14:0] reg
.drp_di (drp_di), // output[15:0] reg
.drp_rdy (drp_rdy), // input
.drp_do (drp_do) // input[15:0]
`endif
`ifdef USE_DATASCOPE
,.datascope_clk (datascope_clk), // input
.datascope_waddr (datascope_waddr), // input[9:0]
......@@ -977,7 +995,7 @@ wire [9:0] xmit_dbg_01;
// .hba_rst (mrst), // input TODO: Reset when !PxCMD.ST? pcmd_st
.hba_rst (mrst || !pcmd_st), // input TODO: Reset when !PxCMD.ST? pcmd_st
.mclk (mclk), // input
.pcmd_st_cleared (pcmd_st_cleared), // input
.fetch_cmd (fsnd_fetch_cmd), // input
.cfis_xmit (fsnd_cfis_xmit), // input
.dx_xmit (fsnd_dx_xmit), // input
......
ahci/axi_ahci_regs.v
View file @ 507b1bd3
......@@ -119,6 +119,14 @@ module axi_ahci_regs#(
input [31:0] debug_in1,
input [31:0] debug_in2,
input [31:0] debug_in3
`ifdef USE_DRP
,output reg drp_en, // @aclk strobes drp_ad
output reg drp_we,
output reg [14:0] drp_addr,
output reg [15:0] drp_di,
input drp_rdy,
input [15:0] drp_do
`endif
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
,input datascope_clk,
......@@ -127,6 +135,12 @@ module axi_ahci_regs#(
input [31:0] datascope_di
`endif
);
`ifdef USE_DRP
localparam DRP_ADDR = 'h3fb;
reg [15:0] drp_read_data;
reg drp_read_r;
reg drp_ready_r;
`endif
`ifdef USE_DATASCOPE
localparam AXIBRAM_BITS = ADDRESS_BITS + 1; // number of axi address outputs (one more than ADDRESS_BITS when using datascope)
wire [31:0] datascope_rdata;
......@@ -202,7 +216,27 @@ module axi_ahci_regs#(
assign was_hba_rst = was_hba_rst_r[0];
assign was_port_rst = was_port_rst_r[0];
always @(posedge aclk) begin
`ifdef USE_DRP
if (bram_waddr == DRP_ADDR) begin
drp_di <= bram_wdata[15: 0];
drp_addr <= bram_wdata[30:16];
// drp_we <= bram_wdata[31];
end
drp_en <= (bram_waddr == DRP_ADDR);
drp_we <= (bram_waddr == DRP_ADDR) && bram_wdata[31];
if (arst || (bram_waddr == DRP_ADDR)) drp_ready_r <= 0;
else if (drp_rdy) drp_ready_r <= 1;
if (drp_rdy) drp_read_data <= drp_do;
if (bram_ren[0]) drp_read_r <= (bram_raddr == DRP_ADDR);
`endif
if (arst) write_busy_r <= 0;
else if (write_start_burst) write_busy_r <= 1;
......@@ -210,21 +244,30 @@ module axi_ahci_regs#(
if (bram_wen) bram_wdata_r <= bram_wdata;
// if (bram_ren[1]) bram_rdata_r <= debug_rd_r? debug_in : bram_rdata;
bram_wstb_r <= {4{bram_wen}} & bram_wstb;
bram_wen_r <= bram_wen;
if (bram_wen) bram_waddr_r <= bram_waddr[ADDRESS_BITS-1:0];
if (bram_ren[0]) debug_rd_r <= &bram_raddr[ADDRESS_BITS-1:4]; // last 16 DWORDs (With AXIBRAM_BITS will be duplicated)
`ifdef USE_DATASCOPE
if (bram_ren[0]) debug_rd_r <= (&bram_raddr[ADDRESS_BITS-1:4]) &&
// (bram_raddr[3:2] == 0) &&
!bram_raddr[ADDRESS_BITS]; //
`else
if (bram_ren[0]) debug_rd_r <= (&bram_raddr[ADDRESS_BITS-1:4]); // &&
// (bram_raddr[3:2] == 0); //
`endif
if (bram_ren[0]) debug_r <= bram_raddr[1]? (bram_raddr[0] ? debug_in3: debug_in2):
(bram_raddr[0] ? debug_in1: debug_in0);
if (bram_ren[1]) bram_rdata_r <= debug_rd_r? debug_r : bram_rdata;
`ifdef USE_DRP
if (bram_ren[1]) bram_rdata_r <= drp_read_r? {drp_ready_r, 15'b0,drp_read_data}:
(debug_rd_r? debug_r : bram_rdata);
`else
if (bram_ren[1]) bram_rdata_r <= debug_rd_r? debug_r : bram_rdata;
`endif
end
//debug_rd_r
......@@ -415,12 +458,9 @@ sata_phy_rst_out will be released after the sata clock is stable
) ahci_regs_i (
.clk_a (aclk), // input
.addr_a (bram_addr), // input[9:0]
/// .en_a (bram_ren[0] || write_busy_w), // input
.en_a (bram_ren[0] || bram_wen || bram_wen_r), // input
/// .en_a (bram_ren_w[0] || bram_wen || bram_wen_r), // input
.regen_a (1'b0), // input
// .we_a (write_busy_r && !nowrite), // input
.we_a (bram_wstb_r), //bram_wen_d), // input[3:0]
.we_a (bram_wstb_r), // input[3:0]
//
.data_out_a (bram_rdata), // output[31:0]
.data_in_a (ahci_regs_di), // input[31:0]
......
ahci/sata_ahci_top.v
View file @ 507b1bd3
......@@ -224,6 +224,16 @@
reg [2:0] nhrst_r;
wire hrst = !nhrst_r[2];
`ifdef USE_DRP
wire drp_en;
wire drp_we;
wire [14:0] drp_addr;
wire [15:0] drp_di;
wire drp_rdy;
wire [15:0] drp_do;
`endif
wire [31:0] debug_phy;
wire [31:0] debug_link;
......@@ -366,6 +376,14 @@
.sctl_ipm (sctl_ipm), // output[3:0]
.sctl_spd (sctl_spd), // output[3:0]
.irq (irq), // output
`ifdef USE_DRP
.drp_en (drp_en), // output reg
.drp_we (drp_we), // output reg
.drp_addr (drp_addr), // output[14:0] reg
.drp_di (drp_di), // output[15:0] reg
.drp_rdy (drp_rdy), // input
.drp_do (drp_do), // input[15:0]
`endif
.debug_in_phy (debug_phy), // input[31:0]
.debug_in_link (debug_link) // input[31:0]
);
......@@ -426,6 +444,16 @@
.txn_out (TXN), // output wire
.rxp_in (RXP), // input wire
.rxn_in (RXN), // input wire
`ifdef USE_DRP
.drp_rst (arst), // input
.drp_clk (ACLK), // input
.drp_en (drp_en), // input
.drp_we (drp_we), // input
.drp_addr (drp_addr), // input[14:0]
.drp_di (drp_di), // input[15:0]
.drp_rdy (drp_rdy), // output
.drp_do (drp_do), // output[15:0]
`endif
.debug_phy (debug_phy), // output[31:0]
.debug_link (debug_link) // output[31:0]
);
......
host/gtx_wrap.v
View file @ 507b1bd3
......@@ -36,6 +36,7 @@
//`include "gtx_comma_align.v"
//`include "gtx_elastic.v"
// All computations have been done in assumption of GTX interface being 20 bits wide!
//`include "system_defines.v"
module gtx_wrap #(
parameter DATA_BYTE_WIDTH = 4,
parameter TXPMARESET_TIME = 5'h1,
......@@ -96,6 +97,17 @@ module gtx_wrap #(
output wire dbg_rxdlysresetdone,
output wire [1:0] txbufstatus
`ifdef USE_DRP
,input drp_rst,
input drp_clk,
input drp_en, // @aclk strobes drp_ad
input drp_we,
input [14:0] drp_addr,
input [15:0] drp_di,
output drp_rdy,
output [15:0] drp_do
`endif
);
wire rxresetdone_gtx;
......@@ -140,6 +152,27 @@ wire txcominit_gtx;
wire txcomwake_gtx;
wire txelecidle_gtx;
`ifdef USE_DRP
wire [1:0] drp_en_w; // [0] - select GTX, [1] - select sipo_to_xclk_measure
wire [1:0] drp_we_w; // [0] - select GTX, [1] - select sipo_to_xclk_measure
reg [1:0] drp_sel; // [0] - select GTX, [1] - select sipo_to_xclk_measure
wire [15:0] drp_do_gtx;
wire [15:0] drp_do_meas;
wire drp_rdy_gtx;
wire drp_rdy_meas;
wire [15:0] other_control; // control bits programmed over DRP interface
assign drp_rdy = (drp_sel[0] & drp_rdy_gtx) | (drp_sel[1] & drp_rdy_meas);
assign drp_do = ({16{drp_sel[0]}} & drp_do_gtx) | ({16{drp_sel[1]}} & drp_do_meas);
assign drp_en_w = {2{drp_en & ~(|drp_addr[14:10])}} & {drp_addr[9],~drp_addr[9]};
assign drp_we_w = {2{drp_we & ~(|drp_addr[14:10])}} & {drp_addr[9],~drp_addr[9]};
always @ (posedge drp_clk) drp_sel <= {2{~(|drp_addr[14:10])}} & {drp_addr[9],~drp_addr[9]};
`endif
// insert resync if it's necessary
generate
if (DATA_BYTE_WIDTH == 4) begin
......@@ -237,7 +270,7 @@ gtx_8x10enc gtx_8x10enc(
wire rxcdrlock; // Marked as "reserved" - maybe not use it, only rxelecidle?
reg rxdlysreset = 0;
wire rxphaligndone;
wire rxdlysresetdone;
wire rxdlysresetdone; // gtx output
reg rx_clocks_aligned = 0;
reg [2:0] rxdlysreset_cntr = 7;
reg rxdlysresetdone_r;
......@@ -271,7 +304,7 @@ gtx_8x10enc gtx_8x10enc(
reg rxphaligndone1_r = 0; // first time rxphaligndone gets active
reg rxphaligndone2_r = 0; // rxphaligndone deasserted
reg rx_clocks_aligned = 0; // second time rxphaligndone gets active (and is supposed to stay)
reg rxdlysresetdone_r;
reg rxdlysresetdone_r; // debug only
wire rxphaligndone;
wire rxdlysresetdone;
wire rxcdrlock; // Marked as "reserved" - maybe not use it, only rxelecidle? (seems alternating 0/1 forever- SS?)
......@@ -281,18 +314,25 @@ gtx_8x10enc gtx_8x10enc(
assign dbg_rx_clocks_aligned = rx_clocks_aligned;
assign dbg_rxcdrlock = rxcdrlock; //goes in/out (because of the SS ?
assign dbg_rxdlysresetdone = rxdlysresetdone_r;
wire bypass_aligned;
`ifdef USE_DRP
assign bypass_aligned = other_control[0];
`else
assign bypass_aligned = 0;
`endif
`ifdef ALIGN_CLOCKS
wire first_confirm = rxphaligndone || (bypass_aligned && clk_phase_align_req);
always @ (posedge xclk) begin
if (rxelecidle) rxphaligndone1_r <= 0;
else if (rxphaligndone) rxphaligndone1_r <= 1;
else if (first_confirm) rxphaligndone1_r <= 1;
if (rxelecidle) rxphaligndone2_r <= 0;
else if (rxphaligndone1_r && !rxphaligndone) rxphaligndone2_r <= 1;
else if (rxphaligndone1_r && !first_confirm) rxphaligndone2_r <= 1;
if (rxelecidle) rx_clocks_aligned <= 0;
else if (rxphaligndone2_r && rxphaligndone) rx_clocks_aligned <= 1;
else if (rxphaligndone2_r && (rxphaligndone || bypass_aligned)) rx_clocks_aligned <= 1;
if (rxelecidle || rxdlysreset) rxdlysresetdone_r <= 0;
if (rxelecidle || rxdlysreset) rxdlysresetdone_r <= 0; // debug only
else if (rxdlysresetdone) rxdlysresetdone_r <= 1;
end
`else // ALIGN_CLOCKS - just bypassing
......@@ -328,11 +368,110 @@ gtx_8x10enc gtx_8x10enc(
wire xclk;
// assuming GTX interface width = 20 bits
// comma aligner
reg [19:0] rxdata_comma_in;
wire [19:0] rxdata_comma_out;
always @ (posedge xclk)
rxdata_comma_in <= {rxdisperr_gtx[1], rxcharisk_gtx[1], rxdata_gtx[15:8], rxdisperr_gtx[0], rxcharisk_gtx[0], rxdata_gtx[7:0]};
wire [19:0] gtx_rx_data20 = {rxdisperr_gtx[1], rxcharisk_gtx[1], rxdata_gtx[15:8], rxdisperr_gtx[0], rxcharisk_gtx[0], rxdata_gtx[7:0]};
wire [19:0] rxdata_comma_in;
// TODO: Add timing constraints on gtx_rx_data20 to reduce spread between bits?
//`ifndef USE_DRP
// `define USE_DRP
//`endif
// asynchronous signals to be controlled by external programmable bits
wire RXPHDLYRESET; // 1 (1'b0),
wire RXPHALIGN; // 2 (1'b0),
wire RXPHALIGNEN; // 3 (1'b0),
wire RXPHDLYPD; // 4 (1'b0),
wire RXPHOVRDEN; // 5 (1'b0),
wire RXDLYSRESET; // 6 (rxdlysreset),
wire RXDLYBYPASS; // 7 (1'b0), // Andrey: p.243: "0: Uses the RX delay alignment circuit."
wire RXDLYEN; // 8 (1'b0),
wire RXDLYOVRDEN; // 9 (1'b0),
wire RXDDIEN; // 10 (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode"
`ifdef USE_DRP
sipo_to_xclk_measure #(
.DATA_WIDTH (20),
.DRP_ABITS (8),
.DRP_MASK_ADDR (0),
.DRP_MASK_BITS (3),
.DRP_TIMER_ADDR (8),
.DRP_EARLY_ADDR (9),
.DRP_LATE_ADDR (10),
.DRP_OTHERCTRL_ADDR (11)
) sipo_to_xclk_measure_i (
.xclk (xclk), // input
.drp_rst (drp_rst), //
.sipo_di (gtx_rx_data20), // input[19:0]
.sipo_do (rxdata_comma_in), // output[19:0] //sipo_di registered @ (posedge xclk)
.drp_clk (drp_clk), // input
.drp_en (drp_en_w[1]), // input
.drp_we (drp_we_w[1]), // input
.drp_addr (drp_addr[7:0]), // input[7:0]
.drp_di (drp_di), // input[15:0]
.drp_rdy (drp_rdy_meas), // output reg
.drp_do (drp_do_meas), // output[15:0] reg
.other_control (other_control) // output[15:0] reg
);
assign RXPHDLYRESET = other_control[ 1]; // 1 (1'b0),
assign RXPHALIGN = other_control[ 2]; // 2 (1'b0),
assign RXPHALIGNEN = other_control[ 3]; // 3 (1'b0),
assign RXPHDLYPD = other_control[ 4]; // 4 (1'b0),
assign RXPHOVRDEN = other_control[ 5]; // 5 (1'b0),
assign RXDLYSRESET = other_control[ 6]; // 6 (rxdlysreset),
assign RXDLYBYPASS = other_control[ 7]; // 7 (1'b0), // Andrey: p.243: "0: Uses the RX delay alignment circuit."
assign RXDLYEN = other_control[ 8]; // 8 (1'b0),
assign RXDLYOVRDEN = other_control[ 9]; // 9 (1'b0),
assign RXDDIEN = other_control[10]; // 10 (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode"
`else
reg [19:0] rxdata_comma_in_r;
assign rxdata_comma_in = rxdata_comma_in_r;
always @ (posedge xclk)
rxdata_comma_in_r <= gtx_rx_data20;
// VDT bug - considered USE_DRP undefined during closure, temporary including unconnected module
sipo_to_xclk_measure #(
.DATA_WIDTH (20),
.DRP_ABITS (8),
.DRP_MASK_ADDR (0),
.DRP_MASK_BITS (3),
.DRP_TIMER_ADDR (8),
.DRP_EARLY_ADDR (9),
.DRP_LATE_ADDR (10),
.DRP_OTHERCTRL_ADDR (11)
) sipo_to_xclk_measure_i (
.xclk (), // input
.sipo_di (), // input[19:0]
.sipo_do (), // output[19:0] //sipo_di registered @ (posedge xclk)
.drp_clk (), // input
.drp_en (), // input
.drp_we (), // input
.drp_addr (), // input[7:0]
.drp_di (), // input[15:0]
.drp_rdy (), // output reg
.drp_do (), // output[15:0] reg
.other_control () // output[15:0] reg
);
assign RXPHDLYRESET = 1'b0;; // 1 (1'b0),
assign RXPHALIGN = 1'b0;; // 2 (1'b0),
assign RXPHALIGNEN = 1'b0;; // 3 (1'b0),
assign RXPHDLYPD = 1'b0;; // 4 (1'b0),
assign RXPHOVRDEN = 1'b0;; // 5 (1'b0),
assign RXDLYSRESET = 1'b0;; // 6 (rxdlysreset),
`ifdef ALIGN_CLOCKS
assign RXDLYBYPASS = 1'b0; // 7 (1'b0), // Andrey: p.243: "0: Uses the RX delay alignment circuit."
`else
assign RXDLYBYPASS = 1'b1; // 7 (1'b0), // Andrey: p.243: "0: Uses the RX delay alignment circuit."
`endif
assign RXDLYEN = 1'b0; // 8 (1'b0),
assign RXDLYOVRDEN = 1'b0; // 9 (1'b0),
`ifdef ALIGN_CLOCKS
assign RXDDIEN = 1'b1; // Andrey: p.243: "Set high in RX buffer bypass mode"
`else
assign RXDDIEN = 1'b0; // 10 (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode"
`endif
`endif
// aligner status generation
// if we detected comma & there was 1st realign after non-aligned state -> triggered, we wait until the next comma
// if no realign would be issued, assumes, that we've aligned to the stream otherwise go back to non-aligned state
......@@ -604,7 +743,7 @@ BUFG bufg_txoutclk (.O(txoutclk),.I(txoutclk_gtx));
//BUFR bufr_xclk (.O(xclk),.I(xclk_mr),.CE(1'b1),.CLR(1'b0));
//BUFMR bufmr_xclk (.O(xclk_mr),.I(xclk_gtx));
BUFG bug_xclk (.O(xclk),.I(xclk_gtx));
BUFG bug_xclk (.O(xclk),.I(~xclk_gtx));
gtxe2_channel_wrapper #(
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
......@@ -713,14 +852,14 @@ gtxe2_channel_wrapper #(
.RXPHDLY_CFG (24'h084020),
.RXPH_MONITOR_SEL (5'b00000),
`ifdef ALIGN_CLOCKS
.RX_XCLK_SEL ("RXUSR"), // ("RXREC"), // Andrey: Now they are the same, just using p.247 "Using RX Buffer Bypass..."
// .RX_XCLK_SEL ("RXUSR"), // ("RXREC"), // Andrey: Now they are the same, just using p.247 "Using RX Buffer Bypass..."
.RX_XCLK_SEL ("RXREC"), // Andrey: Does not align clocks if in this mode
`else
.RX_XCLK_SEL ("RXREC"), // Andrey: Does not align clocks if in this mode
`endif
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
/// .RXCDR_CFG (72'h03000023ff10200020),// 1.6G - 6.25G, No SS, RXOUT_DIV=2
/// .RXCDR_CFG (72'h03800023ff10200008),// Guess for SS
/// .RXCDR_CFG (72'h03_0000_23ff_1020_0020),// 1.6G - 6.25G, No SS, RXOUT_DIV=2
.RXCDR_CFG (72'h03_8800_8BFF_4020_0008),// http://www.xilinx.com/support/answers/53364.html - SATA-2, div=2
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
......@@ -838,6 +977,15 @@ gtxe2_channel_wrapper(
.GTREFCLK1 (1'b0),
.GTSOUTHREFCLK0 (1'b0),
.GTSOUTHREFCLK1 (1'b0),
`ifdef USE_DRP
.DRPADDR (drp_addr[8:0]),
.DRPCLK (drp_clk),
.DRPDI (drp_di),
.DRPDO (drp_do_gtx),
.DRPEN (drp_en_w[0]),
.DRPRDY (drp_rdy_gtx),
.DRPWE (drp_we_w[0]),
`else
.DRPADDR (9'b0),
.DRPCLK (drpclk),
.DRPDI (16'b0),
......@@ -845,6 +993,7 @@ gtxe2_channel_wrapper(
.DRPEN (1'b0),
.DRPRDY (),
.DRPWE (1'b0),
`endif
.GTREFCLKMONITOR (),
.QPLLCLK (1'b0/*gtrefclk*/),
.QPLLREFCLK (1'b0/*gtrefclk*/),
......@@ -893,23 +1042,23 @@ gtxe2_channel_wrapper(
.RXBUFRESET (1'b0),
.RXBUFSTATUS (),
`ifdef ALIGN_CLOCKS
.RXDDIEN (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode"
.RXDLYBYPASS (1'b0), // Andrey: p.243: "0: Uses the RX delay alignment circuit."
.RXDDIEN (RXDDIEN), // (1'b1), // Andrey: p.243: "Set high in RX buffer bypass mode"
.RXDLYBYPASS (RXDLYBYPASS), // (1'b0), // Andrey: p.243: "0: Uses the RX delay alignment circuit."
`else
.RXDDIEN (1'b0),
.RXDLYBYPASS (1'b1),
.RXDDIEN (RXDDIEN), // (1'b0),
.RXDLYBYPASS (RXDLYBYPASS), // (1'b1),
`endif
.RXDLYEN (1'b0),
.RXDLYOVRDEN (1'b0),
.RXDLYSRESET (rxdlysreset),
.RXDLYEN (RXDLYEN), // (1'b0),
.RXDLYOVRDEN (RXDLYOVRDEN), // (1'b0),
.RXDLYSRESET (RXDLYSRESET || rxdlysreset),
.RXDLYSRESETDONE (rxdlysresetdone),
.RXPHALIGN (1'b0),
.RXPHALIGN (RXPHALIGN), // (1'b0),
.RXPHALIGNDONE (rxphaligndone),
.RXPHALIGNEN (1'b0),
.RXPHDLYPD (1'b0),
.RXPHDLYRESET (1'b0),
.RXPHALIGNEN (RXPHALIGNEN), // (1'b0),
.RXPHDLYPD (RXPHDLYPD), // (1'b0),
.RXPHDLYRESET (RXPHDLYRESET), // (1'b0),
.RXPHMONITOR (),
.RXPHOVRDEN (1'b0),
.RXPHOVRDEN (RXPHOVRDEN), // (1'b0),
.RXPHSLIPMONITOR (),
.RXSTATUS (),
.RXBYTEISALIGNED (),
......
host/sata_phy.v
View file @ 507b1bd3
......@@ -82,6 +82,16 @@ module sata_phy #(
output cplllock_debug,
output usrpll_locked_debug,
`ifdef USE_DRP
input drp_rst,
input drp_clk,
input drp_en, // @aclk strobes drp_ad
input drp_we,
input [14:0] drp_addr,
input [15:0] drp_di,
output drp_rdy,
output [15:0] drp_do,
`endif
output [31:0] debug_sata
,output debug_detected_alignp
......@@ -519,6 +529,17 @@ gtx_wrap
.dbg_rxcdrlock (dbg_rxcdrlock) ,
.dbg_rxdlysresetdone(dbg_rxdlysresetdone),
.txbufstatus (txbufstatus[1:0])
`ifdef USE_DRP
,.drp_rst (drp_rst), // input
.drp_clk (drp_clk), // input
.drp_en (drp_en), // input
.drp_we (drp_we), // input
.drp_addr (drp_addr), // input[14:0]
.drp_di (drp_di), // input[15:0]
.drp_rdy (drp_rdy), // output
.drp_do (drp_do) // output[15:0]
`endif
);
......
host/sipo_to_xclk_measure.v 0 → 100644
View file @ 507b1bd3
/*******************************************************************************
* Module: sipo_to_xclk_measure
* Date:2016-02-09
* Author: andrey
* Description: Measuring phase of the SIPO data output relative to (global) xclk
* This module allow select all/some of the input data lines and see if the data
* sampled at negedge of the xclk differs from sampled at the previous or next
* posedge on any of the selected bits. Mismatch with previous posedge means that
* data comes while xclk == 0 (input data too late), mismatch with next posedge
* means that data changes while xclk == 1 (too early).
* Input selection for low 16 bits is written at address DRP_MASK_ADDR (0), next
* 16 bits - at DRP_MASK_ADDR + 1.
* Measurement starts by writing duration to DRP_TIMER_ADDR (8).
* Results (number of mismatches) are available as 15-bit numbers at
* DRP_EARLY_ADDR (9) and DRP_LATE_ADDR (10), MSB indicates that measurement is
* still in progress (wait it clears, small latency for 0 -> 1 should not be
* a problem).
*
* Copyright (c) 2016 Elphel, Inc .
* sipo_to_xclk_measure.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sipo_to_xclk_measure.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module sipo_to_xclk_measure#(
parameter DATA_WIDTH = 20, // Number of data bits to measure
parameter DRP_ABITS = 8,
parameter DRP_MASK_ADDR = 0,
parameter DRP_MASK_BITS = 3,
parameter DRP_TIMER_ADDR = 8, // write timer value (how long to count early/late)
parameter DRP_EARLY_ADDR = 9, // write timer value (how long to count early/late)
parameter DRP_LATE_ADDR = 10, // write timer value (how long to count early/late)
parameter DRP_OTHERCTRL_ADDR = 11
)(
input xclk,
input drp_rst, // for other_control
input [DATA_WIDTH-1:0] sipo_di,
output [DATA_WIDTH-1:0] sipo_do, // input data registered @ posedge xclk (to be used by other modules)
input drp_clk,
input drp_en, // @aclk strobes drp_ad
input drp_we,
input [DRP_ABITS-1:0] drp_addr,
input [15:0] drp_di,
output reg drp_rdy,
output reg [15:0] drp_do,
output reg [15:0] other_control // set/reset some control bits not related to this module
);
localparam MASK_WORDS = (DATA_WIDTH + 15) >> 4;
reg [DATA_WIDTH-1:0] sipo_p; // input data registered @ posedge xclk
reg [DATA_WIDTH-1:0] sipo_n; // input data registered @ negedge xclk
reg [DATA_WIDTH-1:0] sipo_pp; // input data registered twice @ posedge xclk
reg [DATA_WIDTH-1:0] sipo_np; // input data registered @ negedge xclk, then @ posedge xclk
reg [(16 * MASK_WORDS) - 1:0] dmask; // bits to consider (or)
reg input_early_r; // SIPO data is intended to be registered @ posedge xclk
reg input_late_r;
reg [15:0] timer_cntr;
reg [14:0] early_cntr;
reg [14:0] late_cntr;
wire timer_start;
reg timer_run;
reg [DRP_ABITS-1:0] drp_addr_r;
reg drp_wr_r;
reg [ 1:0] drp_rd_r;
reg [15:0] drp_di_r;
reg drp_mask_wr;
reg drp_timer_wr;
reg drp_read_early;
reg drp_read_late;
reg drp_other_ctrl;
reg drp_read_other_ctrl;
localparam DRP_MASK_MASK = (1 << DRP_MASK_BITS) -1;
assign sipo_do = sipo_p;
always @ (negedge xclk) sipo_n <= sipo_di; // only data registered @negedge
always @ (posedge xclk) begin
sipo_p <= sipo_di;
sipo_np <= sipo_n;
sipo_pp <= sipo_p;
input_early_r <= |(dmask[DATA_WIDTH-1:0] & (sipo_np ^ sipo_pp));
input_late_r <= |(dmask[DATA_WIDTH-1:0] & (sipo_np ^ sipo_p));
if (timer_start) timer_cntr <= drp_di_r;
else if (timer_run) timer_cntr <= timer_cntr - 1;
if (timer_start) timer_run <= 1;
else if (!(|timer_cntr[15:1])) timer_run <= 0;
if (timer_start) early_cntr <= 0;
else if (timer_run && input_early_r) early_cntr <= early_cntr + 1;
if (timer_start) late_cntr <= 0;
else if (timer_run && input_late_r) late_cntr <= late_cntr + 1;
end
// DRP interface
always @ (posedge drp_clk) begin
drp_addr_r <= drp_addr;
drp_wr_r <= drp_we && drp_en;
drp_rd_r <= {drp_rd_r[0],~drp_we & drp_en};
drp_di_r <= drp_di;
drp_mask_wr <= drp_wr_r && ((drp_addr_r & ~DRP_MASK_MASK) == DRP_MASK_ADDR);
drp_timer_wr <= drp_wr_r && (drp_addr_r == DRP_TIMER_ADDR);
drp_read_early <= drp_rd_r[0] && (drp_addr_r == DRP_EARLY_ADDR);
drp_read_late <= drp_rd_r[0] && (drp_addr_r == DRP_LATE_ADDR);
drp_other_ctrl <= drp_wr_r && (drp_addr_r == DRP_OTHERCTRL_ADDR);
drp_read_other_ctrl <= drp_rd_r[0] && (drp_addr_r == DRP_OTHERCTRL_ADDR);
drp_rdy <= drp_wr_r || drp_rd_r[1];
drp_do <= ({16{drp_read_early}} & {timer_run,early_cntr}) |
({16{drp_read_late}} & {timer_run,late_cntr}) |
({16{drp_read_other_ctrl}} & {other_control}) ;
if (drp_rst) other_control <= 0;
else if (drp_other_ctrl) other_control <= drp_di_r;
end
// 0..7 - data mask
genvar i1;
generate
for (i1 = 0; i1 < MASK_WORDS; i1 = i1 + 1) begin: gen_drp_mask
always @ (posedge drp_clk)
if (drp_mask_wr && ((drp_addr_r & DRP_MASK_MASK) ==i1)) dmask[16*i1 +: 16] <= drp_di_r;
end
endgenerate
pulse_cross_clock #(
.EXTRA_DLY(0)
) timer_set_i (
.rst (drp_mask_wr), // input
.src_clk (drp_clk), // input
.dst_clk (xclk), // input
.in_pulse (drp_timer_wr), // input
.out_pulse (timer_start), // output
.busy() // output
);
endmodule
py393sata/x393sata.py
View file @ 507b1bd3
......@@ -62,7 +62,7 @@ COMMAND_BUFFER_OFFSET = 0x0 # Just at the beginning of available memory
COMMAND_BUFFER_SIZE = 0x100 # 256 bytes - 128 before PRDT, 128+ - PRDTs (16 bytes each)
PRD_OFFSET = 0x80 # Start of the PRD table
FB_OFFS = 0xc00 # Needs 0x100 bytes
DRP_OFFS = 0xfec # Read/Write DRP data [31] - write/ready, [30:16] - address/0, [15:0] - data to/data from
DATAIN_BUFFER_OFFSET = 0x10000
DATAIN_BUFFER_SIZE = 0x10000
IDENTIFY_BUF = 0 # Identify receive buffer offset in DATAIN_BUFFER, in bytes
......@@ -79,6 +79,14 @@ COMMAND_ADDRESS = None # start of the command buffer (to be sent to device)
DATAIN_ADDRESS = None # start of the the
DATAOUT_ADDRESS = None # start of the the
#DRP addresses (non-GTX)
DRP_MASK_ADDR = 0x200 # ..0x207
DRP_TIMER_ADDR = 0x208 # write timer value (how long to count early/late)
DRP_EARLY_ADDR = 0x209 # write timer value (how long to count early/late)
DRP_LATE_ADDR = 0x20a # write timer value (how long to count early/late)
DRP_OTHERCTRL_ADDR = 0x20b # Now bit 0 - disable wait for phase align
#FIS types
FIS_H2DR = 0x27
FIS_D2HR = 0x34
......@@ -651,6 +659,44 @@ class x393sata(object):
#print("_=mem.mem_dump (0x%x, 0x%x, 1)"%(data_buf, count * 0x200))
#self.x393_mem.mem_dump (data_buf, count * 0x200, 1)
def drp_write (self, addr, data):
self.x393_mem.write_mem(MAXI1_ADDR + DRP_OFFS, (1 << 31) | ((addr & 0x7fff) << 16) | (data & 0xffff))
# while (self.x393_mem.read_mem(MAXI1_ADDR + DRP_OFFS)) & (1 << 31): # No need to wait from Python
# sleep(0.001)
def drp_read (self, addr):
self.x393_mem.write_mem(MAXI1_ADDR + DRP_OFFS, (0 << 31) | ((addr & 0x7fff) << 16))
d = self.x393_mem.read_mem(MAXI1_ADDR + DRP_OFFS)
while not d & (1 << 31) :
d = self.x393_mem.read_mem(MAXI1_ADDR + DRP_OFFS)
return int(d & 0xffff)
def drp (self, addr, data=None):
if data is None:
return self.drp_read(addr)
self.drp_write (addr, data)
def read_sipo_meas(self, mask, duration):
self.drp_write (DRP_MASK_ADDR, mask & 0xffff)
self.drp_write (DRP_MASK_ADDR + 1, (mask >> 16) & 0xffff)
self.drp_write (DRP_TIMER_ADDR, duration)
early_count = self.drp_read(DRP_EARLY_ADDR)
while (early_count & (1 << 15)):
early_count = self.drp_read(DRP_EARLY_ADDR)
late_count = self.drp_read(DRP_LATE_ADDR)
print ("early_count = 0x%x, late_count = 0x%x, duration = 0x%x"%(early_count, late_count, duration))
return (1.0 * early_count/duration, 1.0 * late_count/duration)
def drp_cbit (self, bit, value=None):
old_val = self.drp_read (DRP_OTHERCTRL_ADDR)
if value is None:
return (old_val >> bit ) & 1;
mask = (1 << bit)
if value:
new_val = mask
else:
new_val = 0
self.drp_write (DRP_OTHERCTRL_ADDR, ((old_val ^ new_val) & mask) ^ old_val)
"""
ATA_IDFY = 0xec # Identify command
ATA_WDMA = 0xca # Write to device in DMA mode
......@@ -663,12 +709,29 @@ ATA_RBUF_DMA = 0xe9 # Read 512 bytes from device buffer in DMA mode
_=mem.mem_dump(0xf800b000,10,4)
_=mem.mem_dump (0x80000ff0, 4,4)
sata.read_sipo_meas(0xfffff,0x7ffe)
mem.write_mem(0x80000118,0x11) # ST & FRE
Implement DRP read/write:
mem.write_mem(0x80000fec, 0x550000)
hex(mem.read_mem(0x80000fec))
'0x8000001fL'
sata.drp_write(0x20b,1) #disable wait for auto align
sata.reset_device()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status(
sata.reset_ie(), sata.reg_status()
sata.read_sipo_meas(0xfffff,0x7ffe)
drp_write ('h20b, 'h401); // bypass, clock align
sata.reg_status(),sata.reset_ie()
sata.read_sipo_meas(0xfffff,0x7ffe)
_=mem.mem_dump (0x80000ff0, 4,4)
hex(sata.drp_read(0x55))
cd /mnt/mmc/local/bin
python
......@@ -678,14 +741,18 @@ import x393sata
import x393_mem
mem = x393_mem.X393Mem(1,0,1)
sata = x393sata.x393sata()
sata.bitstream()
#sata.drp_write (0x20b,0x401) # bypass, clock align
### sata.drp (0x20b,0x81) # bypass, clock align
#sata.drp (0x20b,0x400) # bypass, clock align
### sata.drp (0x59,0x8) # Use RXREC
#sata.drp (0x59,0x48)
sata.reg_status()
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
mem.write_mem(0x80000118,0x11)
sata.reset_ie(), sata.reg_status()
sata.reg_status(),sata.reset_ie()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.setup_pio_read_identify_command()
sata.reg_status()
......@@ -737,6 +804,7 @@ sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x81, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
......@@ -744,6 +812,141 @@ sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x321, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x331, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x341, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x441, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x421, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x481, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x4c1, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x4f1, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x4ff, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x500, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x400, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x401, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x601, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x600, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x5ff, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x601, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x600, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x602, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
sata.reg_status()
sata.reset_ie()
sata.dd_read_dma(0x5f0, 1)
_=mem.mem_dump (0x80001000, 0x100,4)
sata.reg_status()
_=mem.mem_dump (0x80000ff0, 4,4)
mem.write_mem(0x80000118,0x10)
......@@ -766,7 +969,7 @@ hex(mem.read_mem(0x80000ff0))
mem.write_mem(0x80000118,0x11)
sata.setup_pio_read_identify_command()
mem.write_mem(sata.get_reg_address('HBA_PORT__PxCI'), 1)
#mem.write_mem(sata.get_reg_address('HBA_PORT__PxCI'), 1)
_=mem.mem_dump (0x80001000, 0x20,4)
mem.maxi_base()
......
system_defines.vh
View file @ 507b1bd3
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
`define USE_DRP
`define ALIGN_CLOCKS
`define USE_DATASCOPE
`define PRELOAD_BRAMS
......
tb/tb_ahci.tf
View file @ 507b1bd3
......@@ -714,6 +714,9 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
`include "includes/ahci_localparams.vh" // SuppressThisWarning VEditor - many unused defines
`include "includes/fis_types.vh" // SuppressThisWarning VEditor - some unused defines
localparam MAXIGP1 = 32'h80000000; // Start of the MAXIGP1 address range (use ahci_localparams.vh offsets)
localparam DRP_OFFSET = 'hfec;
localparam DEBUG_OFFSET = 'hff0;
task maxigp1_write_single; // address in bytes, not words
input [31:0] address;
......@@ -732,7 +735,47 @@ localparam MAXIGP1 = 32'h80000000; // Start of the MAXIGP1 address range (use ah
end
endtask
task drp_write;
input [14:0] addr;
input [15:0] data;
begin
$display ("[DRP]: %x <- %x @ %t",addr, data,$time);
maxigp1_write_single (DRP_OFFSET, {1'b1, addr, data});
maxigp1_read (DRP_OFFSET);
while (!registered_rdata[31]) maxigp1_read (DRP_OFFSET);
end
endtask
task drp_read;
input [14:0] addr;
output reg [15:0] data;
begin
maxigp1_write_single (DRP_OFFSET, {1'b0, addr, 16'b0});
maxigp1_read (DRP_OFFSET);
while (!registered_rdata[31]) maxigp1_read (DRP_OFFSET);
data = registered_rdata[15:0];
$display ("[DRP]: %x -> %x @ %t",addr, data,$time);
end
endtask
task read_sipo_meas;
input [31:0] mask;
input [15:0] duration;
output reg [14:0] early_count;
output reg [14:0] late_count;
reg running;
// wire [15:0] data;
begin
drp_write ('h200, mask[15:0]);
drp_write ('h201, mask[31:16]);
drp_write ('h208, duration);
drp_read ('h209, {running,early_count});
drp_read ('h209, {running,early_count});
while (running) drp_read ('h209,{running, early_count});
drp_read ('h20a, {running, late_count});
$display ("[DRP] read_sipo_meas(): early:%x/%x, late: %x/%x @ %t",early_count,duration,late_count,duration,$time);
end
endtask
task maxigp1_read;
input [31:0] address;
......@@ -999,7 +1042,9 @@ localparam ATA_RBUF_DMA = 'he9; // Read 512 bytes from device buffer in DMA mod
reg [15:0] drp_read_data;
reg [14:0] early_count;
reg [14:0] late_count;
initial begin //Host
NUM_WORDS_EXPECTED =0;
......@@ -1011,6 +1056,21 @@ initial begin //Host
axi_set_rd_lag(0);
axi_set_b_lag(0);
//simulate DRP write/read
// disable waiting for phase aligned:
// drp_write ('h20b, 'h400); // no-bypass, clock align
drp_write ('h20b, 'h401); // bypass, clock align
drp_write ('h10, 'h1234);
drp_write ('h11, 'h2345);
drp_write ('h12, 'h3456);
drp_read ('h10, drp_read_data);
drp_read ('h11, drp_read_data);
drp_read ('h12, drp_read_data);
drp_read ('h20b, drp_read_data);
maxigp1_writep (PXSIG_OFFS32 << 2, 'h12345678); //
maxigp1_writep (PXTFD_OFFS32 << 2, 'h87654321); //
maxigp1_writep (CLB_OFFS32 << 2, 'h12345678); //
......@@ -1045,6 +1105,17 @@ initial begin //Host
wait (IRQ);
TESTBENCH_TITLE = "Got D2H IRQ";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
maxigp1_print (DEBUG_OFFSET + 0, "DEBUG0");
maxigp1_print (DEBUG_OFFSET + 4, "DEBUG1");
maxigp1_print (DEBUG_OFFSET + 8 ,"DEBUG2");
maxigp1_print (DEBUG_OFFSET + 12, "DEBUG3");
read_sipo_meas ('hfffff, 256, early_count, late_count);
read_sipo_meas ('h00001, 256, early_count, late_count);
maxigp1_print (GHC__IS__IPS__ADDR << 2,"GHC__IS__IPS__ADDR"); // Should be 1 (port 0)
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear that interrupt
maxigp1_print (GHC__IS__IPS__ADDR << 2,"GHC__IS__IPS__ADDR"); // Now it should be 0
......
tb_ahci_01.sav
View file @ 507b1bd3
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Tue Feb 9 00:10:45 2016
[*] Wed Feb 10 06:33:11 2016
[*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160208143933526.fst"
[dumpfile_mtime] "Mon Feb 8 21:40:58 2016"
[dumpfile_size] 10386281
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160209233045645.fst"
[dumpfile_mtime] "Wed Feb 10 06:32:11 2016"
[dumpfile_size] 10480323
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 0
[size] 1823 1180
[pos] 1917 0
*-23.562601 17391070 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] 0 0
*-23.654860 890000 29549854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev.linkMonitorFIS.
......@@ -23,18 +23,20 @@
[treeopen] tb_ahci.dut.
[treeopen] tb_ahci.dut.axi_hp_clk_i.
[treeopen] tb_ahci.dut.sata_top.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.crc.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.rx.dataiface.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.tx.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.
......@@ -45,18 +47,20 @@
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.
[treeopen] tb_ahci.elastic1632_fast_i.
[treeopen] tb_ahci.elastic1632_slow_i.
[treeopen] tb_ahci.read_sipo_meas.
[treeopen] tb_ahci.simul_axi_hp_rd_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[treeopen] tb_ahci.simul_axi_read_i.
[sst_width] 290
[signals_width] 355
[sst_width] 306
[signals_width] 409
[sst_expanded] 1
[sst_vpaned_height] 573
@820
......@@ -116,10 +120,6 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.datascope_sel[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.datascope_sel[1:0]
@1001200
-group_end
@c00200
-tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_rst
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_arst
......@@ -133,7 +133,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_addr[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.aclk
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.dev_ready
@800022
@c00022
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
......@@ -147,7 +147,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_raddr[10:0]
@1001200
@1401200
-group_end
@800028
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_ren[1:0]
......@@ -322,7 +322,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtrefclk
-
@1401200
-up
@800200
@c00200
-ahci_regs_i
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.addr_a[9:0]
......@@ -342,7 +342,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.en_b
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_b[3:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_b4[3:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.data_in32_b[31:0]
@1000200
@1401200
-ahci_regs_i
@c00200
-axibram_read
......@@ -872,8 +872,14 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen3
@c00200
-axi_ahci_regs
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in0[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in1[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in2[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in3[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_din[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_r[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_rd_r
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_we
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
......@@ -885,6 +891,78 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.port_arst_any
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.wait_first_access
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.any_access
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.set_port_rst
@800200
-drp
-task
@22
tb_ahci.drp_write.addr[14:0]
@200
-
@1000200
-task
@c00022
tb_ahci.registered_rdata[31:0]
@28
(0)tb_ahci.registered_rdata[31:0]
(1)tb_ahci.registered_rdata[31:0]
(2)tb_ahci.registered_rdata[31:0]
(3)tb_ahci.registered_rdata[31:0]
(4)tb_ahci.registered_rdata[31:0]
(5)tb_ahci.registered_rdata[31:0]
(6)tb_ahci.registered_rdata[31:0]
(7)tb_ahci.registered_rdata[31:0]
(8)tb_ahci.registered_rdata[31:0]
(9)tb_ahci.registered_rdata[31:0]
(10)tb_ahci.registered_rdata[31:0]
(11)tb_ahci.registered_rdata[31:0]
(12)tb_ahci.registered_rdata[31:0]
(13)tb_ahci.registered_rdata[31:0]
(14)tb_ahci.registered_rdata[31:0]
(15)tb_ahci.registered_rdata[31:0]
(16)tb_ahci.registered_rdata[31:0]
(17)tb_ahci.registered_rdata[31:0]
(18)tb_ahci.registered_rdata[31:0]
(19)tb_ahci.registered_rdata[31:0]
(20)tb_ahci.registered_rdata[31:0]
(21)tb_ahci.registered_rdata[31:0]
(22)tb_ahci.registered_rdata[31:0]
(23)tb_ahci.registered_rdata[31:0]
(24)tb_ahci.registered_rdata[31:0]
(25)tb_ahci.registered_rdata[31:0]
(26)tb_ahci.registered_rdata[31:0]
(27)tb_ahci.registered_rdata[31:0]
(28)tb_ahci.registered_rdata[31:0]
(29)tb_ahci.registered_rdata[31:0]
(30)tb_ahci.registered_rdata[31:0]
(31)tb_ahci.registered_rdata[31:0]
@1401200
-group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_addr[14:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_di[15:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_do[15:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_en
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_rdy
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_read_data[15:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_read_r
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_ready_r
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_we
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPCLK
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPDI[15:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPEN
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPWE
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPRDY
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPADDR[8:0]
@200
-
@1000200
-drp
@1401200
-axi_ahci_regs
@c00200
......@@ -1414,15 +1492,13 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_addr[31:1]
-group_end
@1401200
-ahci_fis_transmit
@800200
@c00200
-ahci_sata_layers
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_incom_start
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_incom_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.ll_incom_invalidate
@29
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_fifo_wr
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_type_in[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.d2h_type[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.h2d_ready
......@@ -1471,10 +1547,29 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.rreg_full
-
@1401200
-fifo_h2d_control
@1000200
-ahci_sata_layers
@c00200
-simul_axi_hp_wr
@8022
tb_ahci.simul_axi_hp_wr_i.wacount[5:0]
@28
tb_ahci.simul_axi_hp_wr_i.awvalid
tb_ahci.simul_axi_hp_wr_i.wvalid
tb_ahci.simul_axi_hp_wr_i.awvalid
@22
tb_ahci.simul_axi_hp_wr_i.awid[5:0]
@28
tb_ahci.simul_axi_hp_wr_i.waddr_i.we
@22
tb_ahci.simul_axi_hp_wr_i.awid_out[5:0]
tb_ahci.simul_axi_hp_wr_i.wid[5:0]
@28
tb_ahci.simul_axi_hp_wr_i.wdata_i.we
@22
tb_ahci.simul_axi_hp_wr_i.wid_out[5:0]
tb_ahci.simul_axi_hp_wr_i.awid[5:0]
tb_ahci.simul_axi_hp_wr_i.wid[5:0]
tb_ahci.simul_axi_hp_wr_i.awid_r[5:0]
@28
tb_ahci.simul_axi_hp_wr_i.rst
tb_ahci.simul_axi_hp_wr_i.wvalid
......@@ -1502,6 +1597,7 @@ tb_ahci.simul_axi_hp_wr_i.start_write_burst_w
tb_ahci.simul_axi_hp_wr_i.write_left[3:0]
@28
tb_ahci.simul_axi_hp_wr_i.start_write_burst_w
tb_ahci.simul_axi_hp_wr_i.start_write_burst_r
@22
tb_ahci.simul_axi_hp_wr_i.awlen[3:0]
@28
......@@ -1594,8 +1690,33 @@ tb_ahci.simul_axi_hp_wr_i.wdata_i.fill[7:0]
-simul_axi_hp_wr
@c00200
-ahci_dma
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.addr_data_rq_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.addr_data_rq_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_waddr_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_waddr_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_waddr_ready
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.waddr_data_pend
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.waddr_data_rq
@8022
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wacount[5:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wcount[7:0]
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_id[5:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_raddr_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_waddr_w
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_prd_pend
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.waddr_data_pend
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.dev_wr_id[3:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.abort_rq_mclk
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.aborting
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_id[5:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awid[5:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wid[5:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awlen[3:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awvalid
......@@ -2673,7 +2794,7 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full
-
@1401200
-ahci_dma
@800200
@c00200
-link
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.debug_out[31:0]
......@@ -3052,7 +3173,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.alignes_pair
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.frame_busy
@1000200
@1401200
-link
@c00200
-phy
......@@ -3430,13 +3551,117 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.dbg_clk_align_cntr[15:0]
-oob
@1401200
-oob_ctrl
@c00200
-gtx
@800200
-ttxdata_resynchro
-sipo_meas
@22
tb_ahci.read_sipo_meas.duration[15:0]
tb_ahci.read_sipo_meas.mask[31:0]
@28
tb_ahci.read_sipo_meas.running
@22
tb_ahci.read_sipo_meas.early_count[14:0]
tb_ahci.read_sipo_meas.late_count[14:0]
tb_ahci.drp_read.addr[14:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_addr[14:0]
@c00028
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_en_w[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_en_w[1:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_en_w[1:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_en
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_rdy_gtx
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_rdy
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_sel[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.drp_en
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.drp_we
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.drp_addr[7:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.timer_start
@8022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.timer_cntr[15:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.early_cntr[14:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.late_cntr[14:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.timer_run
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.drp_addr_r[7:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.drp_wr_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.drp_mask_wr
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.drp_timer_wr
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.dmask[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.sipo_di[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.sipo_n[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.sipo_np[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.sipo_p[19:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.sipo_pp[19:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.input_early_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.input_late_r
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.sipo_to_xclk_measure_i.other_control[15:0]
@1401200
-group_end
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxreset
@1000200
-sipo_meas
@800200
-gtx
@29
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_we
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.drp_en
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_en
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.drp_we
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPCLK
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPEN
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPWE
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPDI[15:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.DRPDO[15:0]
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.clk_phase_align_ack
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.clk_phase_align_req
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rx_clocks_aligned
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxphaligndone1_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxphaligndone2_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxphaligndone
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxdlysresetdone
@800200
-ttxdata_resynchro
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.arst
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.txdata_resynchro.data_in[38:0]
......@@ -3521,6 +3746,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
-
@1401200
-gtx8x10enc
@1000200
-gtx
@c00200
-device
......@@ -3575,7 +3801,7 @@ tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXN
tb_ahci.dev.linkSendPrim.type[111:0]
@1401200
-device
@800200
@c00200
-datascope
@200
-
......@@ -3664,7 +3890,7 @@ tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_we
@1000200
@1401200
-datascope
[pattern_trace] 1
[pattern_trace] 0
wrapper/GTXE2_GPL.v
View file @ 507b1bd3
......@@ -2986,6 +2986,26 @@ assign RXCDRLOCK = rxcdrlock;
assign RXDLYSRESETDONE = rxdlysresetdone;
assign RXPHALIGNDONE = rxphaligndone;
localparam DRP_LATENCY = 5;
integer drp_latency_counter;
reg drp_rdy_r;
reg [15:0] drp_ram[0:511];
reg [ 8:0] drp_raddr;
assign DRPDO = drp_rdy_r ? drp_ram[drp_raddr] : 16'bz;
assign DRPRDY = drp_rdy_r;
always @ (posedge DRPCLK) begin
if (DRPEN) drp_latency_counter <= DRP_LATENCY;
else if (drp_latency_counter != 0) drp_latency_counter <= drp_latency_counter - 1;
if (DRPEN && DRPWE) drp_ram[DRPADDR] <= DRPDI;
drp_rdy_r <= (drp_latency_counter == 1);
if (DRPEN) drp_raddr <= DRPADDR;
end
initial
forever @ (posedge reset)
begin
......
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