Commit 507b1bd3 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

more testing with DRP

parent d7e78d92

.project

+17 −17
Original line number Diff line number Diff line
@@ -52,87 +52,87 @@ 
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</projectDescription>

ahci/ahci_dma.v

+7 −1
Original line number Diff line number Diff line
@@ -273,6 +273,7 @@ module ahci_dma ( 
    reg            abort_rq_mclk;         

    reg            abort_busy_mclk;

    wire    [21:0] abort_debug;

    reg            rwaddr_rq_r; // next cycle after requesting waddr_data_rq, raddr_data_rq, raddr_ct_rq and raddr_prd_rq (*-pend is valid)

      

    assign afi_wvalid = aborting ? afi_wvalid_abort:  afi_wvalid_data;

    assign afi_wid =    aborting ? afi_wid_abort:     afi_id;
@@ -380,6 +381,9 @@ module ahci_dma ( 
    always @ (posedge hclk) begin

        hrst_r <= hrst;

    

        if (hrst) rwaddr_rq_r <= 0;

        else      rwaddr_rq_r <= raddr_ct_rq || raddr_prd_rq || raddr_data_rq || waddr_data_rq;

        

        addr_data_rq_r <= addr_data_rq_w;

        

        prd_start_hclk_r <= prd_start_hclk;
@@ -414,7 +418,9 @@ module ahci_dma ( 
        if (hrst)                                           {is_ct_addr, is_prd_addr, is_data_addr} <= 0;

        else if (raddr_ct_rq || raddr_prd_rq || wcount_set) {is_ct_addr, is_prd_addr, is_data_addr} <= {raddr_ct_rq, raddr_prd_rq, wcount_set};

        

        if (axi_set_raddr_w || axi_set_waddr_w) begin

///        if (axi_set_raddr_w || axi_set_waddr_w) begin

        if (rwaddr_rq_r) begin // first cycle one of the *_pend is set

        

            if (raddr_data_pend || waddr_data_pend)  afi_addr <= {data_addr[31:3], 3'b0};

            else                                     afi_addr <= {ct_maddr[31:4],  4'b0};

ahci/ahci_fsm.v

+4 −1
Original line number Diff line number Diff line
@@ -266,11 +266,12 @@ module ahci_fsm 
//    reg                      [7:0] conditions;

//    wire                           pre_jump_w =   (|async_pend_r) ? async_ackn : |(cond_met_w & fsm_transitions[1]);

    wire                           pre_jump_w =   (|async_pend_r) ? async_ackn : (cond_met_w & fsm_transitions[1]);

    wire                           fsm_act_done = get_fis_done ||

    wire                           fsm_act_done_w = get_fis_done ||

                                                  xmit_done ||

                                                  (syncesc_send_pend && syncesc_send_done) ||

                                                  dma_abort_done ||

                                                  asynq_rq; // cominit_got || pcmd_st_cleared

    reg                            fsm_act_done; // made later by 1 cycle so the new conditions are latched                                                

    wire                           fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done

    wire                           fsm_last_act_w = pgm_data[17];
@@ -340,6 +341,8 @@ module ahci_fsm 
        

        was_rst <= hba_rst;

        

        fsm_act_done <= fsm_act_done_w; // delay by 1 clock cycle

               

        fsm_jump <= {fsm_jump[1:0], pre_jump_w | (was_rst & ~hba_rst)};

        

        if   (fsm_jump[0]) pgm_addr <= pgm_jump_addr;

ahci/ahci_sata_layers.v

+21 −1
Original line number Diff line number Diff line
@@ -91,6 +91,16 @@ module ahci_sata_layers #( 
    output  wire        txn_out,

    input   wire        rxp_in,

    input   wire        rxn_in,

`ifdef USE_DRP

    input               drp_rst,

    input               drp_clk,

    input               drp_en, // @aclk strobes drp_ad

    input               drp_we,

    input        [14:0] drp_addr,       

    input        [15:0] drp_di,

    output              drp_rdy,

    output       [15:0] drp_do ,

`endif    

    

    output       [31:0] debug_phy,

    output       [31:0] debug_link
@@ -339,6 +349,16 @@ module ahci_sata_layers #( 
        .cplllock_debug  (),

        .usrpll_locked_debug(),



`ifdef USE_DRP

        .drp_rst           (drp_rst),           // input

        .drp_clk           (drp_clk),           // input

        .drp_en            (drp_en),            // input

        .drp_we            (drp_we),            // input

        .drp_addr          (drp_addr),          // input[14:0] 

        .drp_di            (drp_di),            // input[15:0] 

        .drp_rdy           (drp_rdy),           // output

        .drp_do            (drp_do),            // output[15:0] 

`endif 

        .debug_sata      (debug_phy)  

        ,.debug_detected_alignp(debug_detected_alignp)

    );

ahci/ahci_top.v

+21 −3
Original line number Diff line number Diff line
@@ -182,6 +182,14 @@ module ahci_top#( 
    



    output             irq, // CPU interrupt request

`ifdef USE_DRP

    output                    drp_en, // @aclk strobes drp_ad

    output                    drp_we,

    output             [14:0] drp_addr,       

    output             [15:0] drp_di,

    input                     drp_rdy,

    input              [15:0] drp_do, 

`endif    

    

    input       [31:0] debug_in_phy,

    input       [31:0] debug_in_link
@@ -708,6 +716,16 @@ module ahci_top#( 
        .debug_in1        (debug_dma1),      // debug_in_link),   // input[31:0]

        .debug_in2        (debug_in_phy),    // input[31:0]     // debug from phy/link

        .debug_in3        ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer

`ifdef USE_DRP

       ,.drp_en           (drp_en),          // output reg 

        .drp_we           (drp_we),          // output reg 

        .drp_addr         (drp_addr),        // output[14:0] reg 

        .drp_di           (drp_di),          // output[15:0] reg 

        .drp_rdy          (drp_rdy),         // input

        .drp_do           (drp_do)           // input[15:0] 

`endif    

        

        

`ifdef USE_DATASCOPE

        ,.datascope_clk   (datascope_clk),   // input

        .datascope_waddr  (datascope_waddr), // input[9:0]
@@ -977,7 +995,7 @@ wire [9:0] xmit_dbg_01; 
//        .hba_rst           (mrst),                 // input TODO: Reset when !PxCMD.ST? pcmd_st

        .hba_rst           (mrst || !pcmd_st),     // input TODO: Reset when !PxCMD.ST? pcmd_st

        .mclk              (mclk),                 // input



        .pcmd_st_cleared   (pcmd_st_cleared),      // input

        .fetch_cmd         (fsnd_fetch_cmd),       // input

        .cfis_xmit         (fsnd_cfis_xmit),       // input

        .dx_xmit           (fsnd_dx_xmit),         // input