testing non-aligned data (64-bit dma, 16-bit aligned)

tb/tb_ahci.tf

@@ -687,23 +687,41 @@ localparam ATA_IDFY = 'hec; // Identify command
     wire [31:2] sysmem_dworda_rd = {(afi_sim_rd_address[31:3] - (SYS_MEM_START >> 3)),1'b0};
     assign #1 afi_sim_rd_data=  afi_sim_rd_ready?(MEM_SEL? {sysmem[sysmem_dworda_rd[31:2]+1], sysmem[sysmem_dworda_rd[31:2]]} :64'bx):64'bz;
     wire [31:2] sysmem_dworda_wr = {(afi_sim_wr_address[31:3] - (SYS_MEM_START >> 3)),1'b0};
-    wire [31:0] sysmem_di_low =  ({{8{afi_sim_wr_stb[3]}},{8{afi_sim_wr_stb[2]}},{8{afi_sim_wr_stb[1]}},{8{afi_sim_wr_stb[0]}}} &
-                                (sysmem[sysmem_dworda_wr[31:2]] ^ afi_sim_wr_data[31:0])) ^ sysmem[sysmem_dworda_wr[31:2]];
+    wire [31:0] sysmem_di_low =  ({{8{~afi_sim_wr_stb[3]}},{8{~afi_sim_wr_stb[2]}},{8{~afi_sim_wr_stb[1]}},{8{~afi_sim_wr_stb[0]}}} &
+                                (sysmem[sysmem_dworda_wr[31:2]] ^ afi_sim_wr_data[31:0])) ^ afi_sim_wr_data[31:0];
     
-    wire [31:0] sysmem_di_high = ({{8{afi_sim_wr_stb[7]}},{8{afi_sim_wr_stb[6]}},{8{afi_sim_wr_stb[5]}},{8{afi_sim_wr_stb[4]}}} &
-                                (sysmem[sysmem_dworda_wr[31:2]+1] ^ afi_sim_wr_data[63:32])) ^ sysmem[sysmem_dworda_wr[31:2]+1];
+    wire [31:0] sysmem_di_high = ({{8{~afi_sim_wr_stb[7]}},{8{~afi_sim_wr_stb[6]}},{8{~afi_sim_wr_stb[5]}},{8{~afi_sim_wr_stb[4]}}} &
+                                (sysmem[sysmem_dworda_wr[31:2]+1] ^ afi_sim_wr_data[63:32])) ^ afi_sim_wr_data[63:32];
     always @ (posedge HCLK) begin
         if (|afi_sim_wr_stb[3:0]) sysmem[sysmem_dworda_wr[31:2]    ] <= sysmem_di_low;
         if (|afi_sim_wr_stb[7:4]) sysmem[sysmem_dworda_wr[31:2] + 1] <= sysmem_di_high;
     end
     
+    task sysmem_print;
+        input integer start_w;  // start word
+        input integer len_w;    // number of words
+        integer i,j;
+        reg [15:0] data[0:7];
+        reg [31:0] d;
+        begin
+            for (i = 0; i < len_w; i = i + 8) begin
+                for (j = 0; j < 8; j = j+1) begin
+                    d = sysmem[(start_w + i + j) >> 1];
+//                    $display ("%h: %h", (start_w + i ) >> 1, d);
+                    data[j] = ((start_w + i + j) & 1) ? d[31:16] : d [15:0]; 
+                end
+                $display("%h: %h %h %h %h %h %h %h %h ",start_w + i, data[0],  data[1], data[2], data[3], data[4], data[5], data[6], data[7]);
+            end 
+        end
+    endtask
+    
     
     task setup_pio_read_identify_command;
         input integer prd_int; // [0] - first prd interrupt, ... [31] - 31-st
         integer i;
         begin
             // clear system memory for command
-            for (i = 0; i < 63; i = i+1)  sysmem[(COMMAND_TABLE >> 2) + i] = 0;
+            for (i = 0; i < 64; i = i+1)  sysmem[(COMMAND_TABLE >> 2) + i] = 0;
             // fill ATA command 
             sysmem[(COMMAND_TABLE >> 2) + 0] = FIS_H2DR |         // FIS type - H2D register (0x27)
                                                ('h80 << 8) |      // set C = 1
@@ -711,7 +729,7 @@ localparam ATA_IDFY = 'hec; // Identify command
                                               ( 0 << 24);        // features = 0 ?
             // All other 4 DWORDs are 0 for this command
             // Set PRDT (single item) TODO: later check multiple small ones
-            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 0] = SYS_MEM_START + IDENTIFY_BUF;
+            sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 0] = SYS_MEM_START + IDENTIFY_BUF + 2; // shift by 2 bytes
             sysmem[((COMMAND_TABLE + PRD_OFFSET) >> 2) + 3] = (prd_int[0] << 31) | 511; // 512 bytes in this PRDT
             // Setup command header
             maxigp1_writep       ((CLB_OFFS32 + 0) << 2,     (5 <<  0) | // 'CFL' - number of DWORDs in thes CFIS
@@ -796,7 +814,18 @@ initial begin //Host
     
     setup_pio_read_identify_command(1); // prdt interrupt for entry 0
     maxigp1_print        (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
-//    $finish;
+    
+    maxigp1_writep       (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup)
+    maxigp1_writep       (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear that interrupt
+    wait (IRQ);
+    TESTBENCH_TITLE = "Got Identify";
+    $display("[Testbench]:       %s @%t", TESTBENCH_TITLE, $time);
+
+    maxigp1_print        (HBA_PORT__PxIS__PSS__ADDR << 2,"HBA_PORT__PxIS__PSS__ADDR");
+    
+    sysmem_print ('h1e81,'h180);
+    
+    $finish;
 //HBA_PORT__PxIE__DHRE__MASK = 'h1;
 end
 

tb_ahci_01.sav

 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Wed Jan 27 03:45:46 2016
+[*] Wed Jan 27 06:51:42 2016
 [*]
-[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160126201651026.fst"
-[dumpfile_mtime] "Wed Jan 27 03:17:46 2016"
-[dumpfile_size] 6562795
+[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160126234218474.fst"
+[dumpfile_mtime] "Wed Jan 27 06:43:12 2016"
+[dumpfile_size] 6563895
 [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
-[timestart] 19020700
-[size] 1823 1180
+[timestart] 0
+[size] 1823 1173
 [pos] 1994 0
-*-15.938510 19216667 19123334 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-22.938511 25590250 19123334 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] tb_ahci.
 [treeopen] tb_ahci.dev.phy.
 [treeopen] tb_ahci.dut.
@@ -435,7 +435,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tfd_err[7:0]
 -ahci_fis_receive
 @1401200
 -ahci_top
-@c00200
+@800200
 -ahci_ctrl_stat
 @22
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_addr[9:0]
@@ -620,7 +620,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
 (31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIE_r[31:0]
 @1401200
 -group_end
-@c00022
+@800022
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
 @28
 (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
@@ -653,9 +653,11 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
 (27)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
 (28)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
 (29)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
+@29
 (30)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
+@28
 (31)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.PxIS_r[31:0]
-@1401200
+@1001200
 -group_end
 @28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.pxci0_clear
@@ -738,6 +740,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen2
 tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen3
 @1401200
 -ssts
+@1000200
 -ahci_ctrl_stat
 @c00200
 -axi_ahci_regs
@@ -975,7 +978,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
 @1000200
 -ahci_fsm
-@800200
+@c00200
 -ahci_fis_receive
 @200
 -
@@ -1025,7 +1028,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_skipping_extra
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_first_flushing_r
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_in_valid
 tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.dma_in
-@1000200
+@1401200
 -ahci_fis_receive
 @c00200
 -ahci_fis_transmit
@@ -1148,7 +1151,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.rreg_full
 @1401200
 -fifo_h2d_control
 -ahci_sata_layers
-@800200
+@c00200
 -simul_axi_hp_wr
 @28
 tb_ahci.simul_axi_hp_wr_i.rst
@@ -1265,8 +1268,9 @@ tb_ahci.simul_axi_hp_wr_i.wdata_i.fifo_fill[7:0]
 tb_ahci.simul_axi_hp_wr_i.wdata_i.fill[7:0]
 @1000200
 -fifo_wdata
+@1401200
 -simul_axi_hp_wr
-@800200
+@c00200
 -ahci_dma
 @28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.hrst
@@ -1279,6 +1283,21 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_rd_busy
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_abort
 @22
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wdata[63:0]
+@c00022
+tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wstrb[7:0]
+@28
+(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wstrb[7:0]
+(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wstrb[7:0]
+(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wstrb[7:0]
+(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wstrb[7:0]
+(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wstrb[7:0]
+(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wstrb[7:0]
+(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wstrb[7:0]
+(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wstrb[7:0]
+@1401200
+-group_end
+@22
+tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wstb4[3:0]
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wid[5:0]
 @28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wready
@@ -1358,7 +1377,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]
 (21)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]
 @1401200
 -group_end
-@29
+@28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_next_burst
 @22
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_alen[3:0]
@@ -1421,7 +1440,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_prd_addr
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wcount_many
 @22
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wcount[7:0]
-@800200
+@c00200
 -dma_d2h_fifo
 @28
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.init
@@ -1526,7 +1545,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_rd
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.fifo_rd_r
 @22
 tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_wr_fifo_i.raddr[3:0]
-@1000200
+@1401200
 -dma_d2h_fifo
 @200
 -----
@@ -1740,7 +1759,7 @@ tb_ahci.simul_axi_hp_rd_i.rdata_i.out_full
 -top
 @200
 -
-@1000200
+@1401200
 -ahci_dma
 @c00200
 -link
@@ -1873,7 +1892,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
 @1401200
 -gtx8x10enc
 -gtx
-@800200
+@c00200
 -device
 @22
 tb_ahci.dev.receive_id
@@ -1896,6 +1915,7 @@ tb_ahci.dev.phy.ll_charisk_in[3:0]
 -
 @1000200
 -dev_phy
+@1401200
 -device
 [pattern_trace] 1
 [pattern_trace] 0