Commit 03215fa1 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

more debugging

parent 84a54d4f

ahci/ahci_dma.v

+31 −10
Original line number Original line Diff line number Diff line
@@ -177,7 +177,7 @@ module ahci_dma ( 
    reg            data_irq; // interrupt at the end of this PRD

    reg            data_irq; // interrupt at the end of this PRD

    reg     [21:1] wcount;  // Word count

    reg     [21:1] wcount;  // Word count

    reg            wcount_set; 

    reg            wcount_set; 

    reg     [21:1] qwcount; // only [21:3] are used

    reg     [22:1] qwcount; // only [21:3] are used ([22] - carry from subtraction )

    

    

    reg     [21:3] qw_datawr_left;

    reg     [21:3] qw_datawr_left;

    reg     [ 3:0] qw_datawr_burst;

    reg     [ 3:0] qw_datawr_burst;
@@ -216,12 +216,20 @@ module ahci_dma ( 
    wire           raddr_ct_rq = cmd_start_hclk;

    wire           raddr_ct_rq = cmd_start_hclk;

    reg            raddr_ct_pend;

    reg            raddr_ct_pend;





/*

    wire           addr_data_rq = (wcount_set || data_next_burst);

    wire           addr_data_rq = (wcount_set || data_next_burst);

     

     

    wire           waddr_data_rq =  !dev_wr_hclk && addr_data_rq;

    wire           waddr_data_rq =  !dev_wr_hclk && addr_data_rq;

    reg            waddr_data_pend;

    

    wire           raddr_data_rq =   dev_wr_hclk && addr_data_rq;

    wire           raddr_data_rq =   dev_wr_hclk && addr_data_rq;



*/     

    wire           addr_data_rq_w = (wcount_set || data_next_burst);

    reg            addr_data_rq_r;

     

    wire           waddr_data_rq =  !dev_wr_hclk && addr_data_rq_r;

    wire           raddr_data_rq =   dev_wr_hclk && addr_data_rq_r;



    reg            waddr_data_pend;

    reg            raddr_data_pend;

    reg            raddr_data_pend;

    // count different types of AXI ID separately - just for debugging

    // count different types of AXI ID separately - just for debugging

    reg      [3:0] ct_id;

    reg      [3:0] ct_id;
@@ -240,7 +248,8 @@ module ahci_dma ( 
    assign ct_done = (ct_busy_r == 2'b10);

    assign ct_done = (ct_busy_r == 2'b10);

    assign first_prd_fetch = ct_over_prd_enabled == 2'b01;

    assign first_prd_fetch = ct_over_prd_enabled == 2'b01;

    assign axi_set_raddr_w = axi_set_raddr_ready && (raddr_ct_pend || raddr_prd_pend || raddr_data_pend);    

    assign axi_set_raddr_w = axi_set_raddr_ready && (raddr_ct_pend || raddr_prd_pend || raddr_data_pend);    

    assign axi_set_waddr_w = axi_set_raddr_ready && raddr_data_pend;    

/// assign axi_set_waddr_w = axi_set_raddr_ready && raddr_data_pend;    

    assign axi_set_waddr_w = axi_set_waddr_ready && waddr_data_pend;    

    assign axi_set_addr_data_w = (axi_set_raddr_ready && raddr_data_pend) || (axi_set_waddr_ready && waddr_data_pend);

    assign axi_set_addr_data_w = (axi_set_raddr_ready && raddr_data_pend) || (axi_set_waddr_ready && waddr_data_pend);
@@ -314,7 +323,12 @@ module ahci_dma ( 
    wire debug_01 = ct_busy_r[0] || prd_rd_busy ;      

    wire debug_01 = ct_busy_r[0] || prd_rd_busy ;      

    wire debug_02 =|afi_rcount[7:SAFE_RD_BITS];

    wire debug_02 =|afi_rcount[7:SAFE_RD_BITS];

    wire debug_03 = (afi_rvalid && !(|afi_rd_ctl));

    wire debug_03 = (afi_rvalid && !(|afi_rd_ctl));

    

    wire [21:1] wcount_plus_data_addr = wcount[21:1] + data_addr[2:1];

    

    always @ (posedge hclk) begin

    always @ (posedge hclk) begin

        addr_data_rq_r <= addr_data_rq_w;

        

        prd_start_hclk_r <= prd_start_hclk;

        prd_start_hclk_r <= prd_start_hclk;

        

        

        if      (hrst || cmd_abort_hclk) prd_enabled <= 0;

        if      (hrst || cmd_abort_hclk) prd_enabled <= 0;
@@ -366,13 +380,20 @@ module ahci_dma ( 
        if (hrst) axi_set_waddr_r <= 0;

        if (hrst) axi_set_waddr_r <= 0;

        else      axi_set_waddr_r <= axi_set_waddr_w;

        else      axi_set_waddr_r <= axi_set_waddr_w;

        

        

        if (addr_data_rq) data_len <= ((|qwcount[21:7]) || (&qwcount[6:3]))? 4'hf: qwcount[6:3];       // early calculate

///     if (addr_data_rq)   data_len <= ((|qwcount[21:7]) || (&qwcount[6:3]))? 4'hf: qwcount[6:3];       // early calculate

        if (addr_data_rq_r) data_len <= ((|qwcount[21:7]) || (&qwcount[6:3]))? 4'hf: qwcount[6:3];       // early calculate



///     if      (wcount_set)          qwcount[21:1] <= wcount[21:1] + data_addr[2:1]; //minus 1

///     else if (axi_set_addr_data_w) qwcount[21:7] <= qwcount[21:7] - 1; // may get negative





        if      (wcount_set)          qwcount[22:1] <= {1'b0,wcount_plus_data_addr[21:1]}; // wcount[21:1] + data_addr[2:1]; //minus 1

        else if (axi_set_addr_data_w) qwcount[22:7] <= qwcount[22:7] - 1; // may get negative

        

        

        if      (wcount_set)          qwcount[21:1] <= wcount[21:1] + data_addr[2:1]; //minus 1

//wcount_plus_data_addr        

        else if (axi_set_addr_data_w) qwcount[21:7] <= qwcount[21:7] - 1; // may get negative

        

        

        data_next_burst <= axi_set_addr_data_w && ((|qwcount[21:7]) || (&qwcount[6:3])); // same time as afi_awvalid || afi_arvalid

///     data_next_burst <= axi_set_addr_data_w && ((|qwcount[21:7]) || (&qwcount[6:3])); // same time as afi_awvalid || afi_arvalid

///        data_next_burst <= !qwcount[22] && axi_set_addr_data_w && ((|qwcount[21:7]) || (&qwcount[6:3])); // same time as afi_awvalid || afi_arvalid

        data_next_burst <= !qwcount[22] && axi_set_addr_data_w && (|qwcount[21:7]); // same time as afi_awvalid || afi_arvalid





// Get PRD data

// Get PRD data

        // store data address from PRD, increment when needed

        // store data address from PRD, increment when needed

tb/tb_ahci.tf

+1 −1
Original line number Original line Diff line number Diff line
@@ -680,7 +680,7 @@ localparam ATA_IDFY = 'hec; // Identify command 
// afi loopback

// afi loopback

    assign #1 afi_sim_rd_valid = afi_sim_rd_ready;

    assign #1 afi_sim_rd_valid = afi_sim_rd_ready;

    assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;

    assign #1 afi_sim_rd_resp = afi_sim_rd_ready?2'b0:2'bx;

    assign #1 afi_sim_wr_ready = afi_sim_wr_valid;

    assign #1 afi_sim_wr_ready = 1; // afi_sim_wr_valid;

    assign #1 afi_sim_bresp_latency=4'h5; 

    assign #1 afi_sim_bresp_latency=4'h5; 

//  assign #1 afi_sim_rd_data=  afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1,  2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;

//  assign #1 afi_sim_rd_data=  afi_sim_rd_ready?{2'h0,afi_sim_rd_address[31:3],1'h1,  2'h0,afi_sim_rd_address[31:3],1'h0}:64'bx;

    wire MEM_SEL = (afi_sim_rd_address[31:3] >= (SYS_MEM_START >> 3)) && (afi_sim_rd_address[31:3] < ((SYS_MEM_START + SYS_MEM_SIZE) >> 3));

    wire MEM_SEL = (afi_sim_rd_address[31:3] >= (SYS_MEM_START >> 3)) && (afi_sim_rd_address[31:3] < ((SYS_MEM_START + SYS_MEM_SIZE) >> 3));

tb_ahci_01.sav

+229 −9
Original line number Original line Diff line number Diff line 
[*]

[*]

[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI

[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI

[*] Wed Jan 27 00:58:43 2016

[*] Wed Jan 27 03:45:46 2016

[*]

[*]

[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160126175635551.fst"

[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160126201651026.fst"

[dumpfile_mtime] "Wed Jan 27 00:57:30 2016"

[dumpfile_mtime] "Wed Jan 27 03:17:46 2016"

[dumpfile_size] 6579639

[dumpfile_size] 6562795

[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"

[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"

[timestart] 0

[timestart] 19020700

[size] 1823 1180

[size] 1823 1180

[pos] 1994 0

[pos] 1994 0

*-23.000113 25083634 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

*-15.938510 19216667 19123334 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1

[treeopen] tb_ahci.

[treeopen] tb_ahci.

[treeopen] tb_ahci.dev.

[treeopen] tb_ahci.dev.phy.

[treeopen] tb_ahci.dev.phy.

[treeopen] tb_ahci.dut.

[treeopen] tb_ahci.dut.

[treeopen] tb_ahci.dut.axi_hp_clk_i.

[treeopen] tb_ahci.dut.axi_hp_clk_i.
@@ -32,8 +31,11 @@ 
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.

[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.

[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.

[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.

[treeopen] tb_ahci.simul_axi_hp_rd_i.

[treeopen] tb_ahci.simul_axi_hp_rd_i.

[sst_width] 253

[treeopen] tb_ahci.simul_axi_hp_wr_i.

[signals_width] 330

[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.

[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.

[sst_width] 275

[signals_width] 256

[sst_expanded] 1

[sst_expanded] 1

[sst_vpaned_height] 618

[sst_vpaned_height] 618

@820

@820
@@ -1147,6 +1149,124 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_h2d_control_i.rreg_full 
-fifo_h2d_control

-fifo_h2d_control

-ahci_sata_layers

-ahci_sata_layers

@800200

@800200

-simul_axi_hp_wr

@28

tb_ahci.simul_axi_hp_wr_i.rst

tb_ahci.simul_axi_hp_wr_i.wvalid

@22

tb_ahci.simul_axi_hp_wr_i.wcount[7:0]

@28

tb_ahci.simul_axi_hp_wr_i.wready

tb_ahci.dut.afi3_wready

tb_ahci.simul_axi_hp_wr_i.fifo_wd_rd

tb_ahci.simul_axi_hp_wr_i.write_in_progress_w

tb_ahci.simul_axi_hp_wr_i.last_confirmed_write

tb_ahci.simul_axi_hp_wr_i.wlast_out

tb_ahci.simul_axi_hp_wr_i.fifo_wd_rd

@22

tb_ahci.simul_axi_hp_wr_i.write_left[3:0]

@28

tb_ahci.simul_axi_hp_wr_i.write_in_progress

tb_ahci.simul_axi_hp_wr_i.w_nempty

tb_ahci.simul_axi_hp_wr_i.sim_wr_ready

tb_ahci.simul_axi_hp_wr_i.sim_wr_valid

tb_ahci.simul_axi_hp_wr_i.enough_data

tb_ahci.simul_axi_hp_wr_i.aw_nempty

tb_ahci.simul_axi_hp_wr_i.start_write_burst_w

@22

tb_ahci.simul_axi_hp_wr_i.write_left[3:0]

@28

tb_ahci.simul_axi_hp_wr_i.start_write_burst_w

@22

tb_ahci.simul_axi_hp_wr_i.awlen[3:0]

@28

tb_ahci.simul_axi_hp_wr_i.awready

tb_ahci.simul_axi_hp_wr_i.awvalid

@22

tb_ahci.simul_axi_hp_wr_i.awlen_out[3:0]

@28

tb_ahci.simul_axi_hp_wr_i.fifo_wd_rd

@800200

-fifo_waddr

@28

tb_ahci.simul_axi_hp_wr_i.waddr_i.we

@c00022

tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

@28

(0)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(1)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(2)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(3)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(4)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(5)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(6)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(7)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(8)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(9)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(10)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(11)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(12)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(13)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(14)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(15)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(16)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(17)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(18)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(19)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(20)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(21)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(22)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(23)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(24)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(25)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(26)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(27)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(28)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(29)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(30)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(31)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(32)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(33)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(34)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(35)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(36)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(37)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(38)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(39)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(40)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(41)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(42)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(43)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(44)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(45)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(46)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(47)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(48)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

(49)tb_ahci.simul_axi_hp_wr_i.waddr_i.data_in[49:0]

@1401200

-group_end

@28

tb_ahci.simul_axi_hp_wr_i.waddr_i.re

@22

tb_ahci.simul_axi_hp_wr_i.waddr_i.fifo_fill[5:0]

tb_ahci.simul_axi_hp_wr_i.waddr_i.fill[5:0]

@1000200

-fifo_waddr

@800200

-fifo_wdata

@28

tb_ahci.simul_axi_hp_wr_i.wdata_i.we

@22

tb_ahci.simul_axi_hp_wr_i.wdata_i.data_in[78:0]

@28

tb_ahci.simul_axi_hp_wr_i.wdata_i.re

@22

tb_ahci.simul_axi_hp_wr_i.wdata_i.fifo_fill[7:0]

tb_ahci.simul_axi_hp_wr_i.wdata_i.fill[7:0]

@1000200

-fifo_wdata

-simul_axi_hp_wr

@800200

-ahci_dma

-ahci_dma

@28

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.hrst

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.hrst
@@ -1157,9 +1277,109 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_start 
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_busy

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_busy

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_rd_busy

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_rd_busy

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_abort

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.cmd_abort

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wdata[63:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wid[5:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wready

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wvalid

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wlast

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wcount[7:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awready

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awvalid

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_awaddr[31:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_addr[31:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_raddr_w

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_waddr_w

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.raddr_data_pend

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.waddr_data_pend

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.waddr_data_rq

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_waddr_ready

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_next_burst

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_waddr_w

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.addr_data_rq_w

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.addr_data_rq_r

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_addr_data_w

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.wcount_set

@800028

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]

@28

(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]

(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_rd_ctl[1:0]

@1001200

-group_end

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.is_prd_addr

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.int_data_addr[3:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_len[3:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qw_datawr_left[21:3]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qw_datawr_last

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qw_datawr_burst[3:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_wacount[5:0]

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_waddr_ready

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_waddr_w

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.axi_set_waddr_ready

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.waddr_data_pend

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.waddr_data_rq

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.addr_data_rq_r

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.addr_data_rq_w

@c00022

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

@28

(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(3)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(7)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(8)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(9)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(10)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(11)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(12)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(13)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(14)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(15)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(16)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(17)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(18)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(19)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(20)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

(21)tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.qwcount[22:1]

@1401200

-group_end

@29

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_next_burst

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.afi_alen[3:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_len[3:0]

@800200

-sim_d2h

@200

@200

-

-

@22

@22

tb_ahci.sysmem_dworda_wr[31:2]

tb_ahci.sysmem_di_low[31:0]

tb_ahci.sysmem_di_high[31:0]

tb_ahci.afi_sim_wr_address[31:0]

tb_ahci.afi_sim_wr_stb[7:0]

tb_ahci.afi_sim_wr_data[63:0]

@28

tb_ahci.afi_sim_wr_ready

tb_ahci.afi_sim_wr_valid

@1000200

-sim_d2h

@22

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.sys_in[31:0]

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.sys_in[31:0]

@28

@28

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.sys_nfull

tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.sys_nfull

ahci/ahci_top.v

+1 −1

File changed.

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