Commit 3efc55dc authored by Andrey Filippov's avatar Andrey Filippov

fixed error handling, added other error

parent 2d189c2d
......@@ -493,7 +493,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
else if (swr_HBA_PORT__PxCI) pxci0_r <= soft_write_data[0];
end
// HBA_PORT__PxCMD register - different behaviors of differtnt fields
// HBA_PORT__PxCMD register - different behaviors of different fields
// use PxCMD_MASK to prevent generation of unneeded register bits
always @(posedge mclk) begin
......
......@@ -318,6 +318,7 @@ module ahci_fsm
wire clear_pisn32; // additional clear when in P:NotRunning state
assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending
assign update_all = fsm_jump[0];
assign ssts_ipm_dnp = phy_ready_chng_r && (phy_ready_prev == 0); // device not present or communication not established
......@@ -389,7 +390,9 @@ module ahci_fsm
if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w;
if (hba_rst || pre_jump_w) fsm_transitions <= 0;
//// if (hba_rst || pre_jump_w) fsm_transitions <= 0;
/// 2016.12.07 jumps were not disabled after async transitions, they came from the previously executed code
if (hba_rst || pre_jump_w || dis_actions) fsm_transitions <= 0;
else if (fsm_transitions_w) fsm_transitions <= 1;
// else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) ||
// (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1;
......
/*******************************************************************************
* Module: action_decoder
* Date:2016-03-12
* Author: auto-generated file, see ahci_fsm_sequence_old.py
* Date:2016-12-07
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Decode sequencer code to 1-hot actions
*******************************************************************************/
......
/*******************************************************************************
* Module: condition_mux
* Date:2016-03-12
* Author: auto-generated file, see ahci_fsm_sequence_old.py
* Date:2016-12-07
* Author: auto-generated file, see ahci_fsm_sequence.py
* Description: Select condition
*******************************************************************************/
......
......@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE)
, .INIT_0C (256'h000000000000000000000000000000000000000001010004001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
......@@ -97,7 +97,7 @@
// RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'h2;
localparam PCI_Header__RID__RID__DFLT = 'h4;
// RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
......
......@@ -27,8 +27,8 @@ __status__ = "Development"
#import sys
# All unspecified ranges/fields default to fT:RO, fC:0 (readonly, reset value = 0)
RID = 0x02 # Revision ID (use for bitstream version)
#RID = 0x03 # Revision ID (use for bitstream version)
#RID = 0x02 # Revision ID (use for bitstream version)
RID = 0x04 # Revision ID
VID = 0xfffe # What to use for non-PCI "vendorID"?
DID = 0x0001
SSVID = 0xfffe
......
......@@ -1502,7 +1502,14 @@ modprobe ahci_elphel &
sleep 2
echo 1 > /sys/devices/soc0/amba@0/80000000.elphel-ahci/load_module
#to remove:
umount /dev/sda
rmmod ahci_elphel
142615472
wget -O - "http://localhost/x393_vsc330x.php?c:zynq=esata"
wget -O - "http://localhost/x393_vsc330x.php?c:zynq=ssd"
cd /usr/local/bin; python
......@@ -1513,7 +1520,18 @@ import x393_mem
mem = x393_mem.X393Mem(1,0,1)
sata = x393sata.x393sata()
hex(mem.read_mem(sata.get_reg_address('PCI_Header__RID')))
sata.dd_read_dma_ext(142615470, 512, 512)
sata.dd_read_dma_ext(142615472, 512, 512)
Read write pointer to datascope:
hex(((mem.read_mem(0x80000ffc) >> 10) & 0xffc) + 0x80001000)
Datascope has a ring buffer of 4K: 0x80001000..0x80001fff
mem.read_mem(0x80000118)
mem.write_mem(0x80000118,0x10)
def get_MAC():
......
......@@ -38,7 +38,7 @@
`define PRELOAD_BRAMS
`define CHECKERS_ENABLED
`define use200Mhz 1
`define SEND_READ_ERROR
/*
* using x393_testbench01.tf style, contains a lot of copy-pasted code from there
*/
......@@ -1409,12 +1409,29 @@ initial begin //Host
// maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup)
// maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear that interrupt
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow DHR only interrupts (PIO setup)
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // clear that interrupt
//// maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow DHR only interrupts (PIO setup)
//// maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // clear that interrupt
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK | HBA_PORT__PxIE__TFEE__MASK); // allow DHR and TFEE interrupts (PIO setup)
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK | HBA_PORT__PxIE__TFEE__MASK); // clear those interrupts
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 3); // Record current time in datascope with a 3-bit tag
wait (IRQ);
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 4); // Record current time in datascope with a 3-bit tag
maxigp1_print (HBA_PORT__PxIS__PSS__ADDR << 2,"HBA_PORT__PxIS__PSS__ADDR after got d2h");
if (registered_rdata & HBA_PORT__PxIE__TFEE__MASK) begin
repeat (20) @(posedge CLK);
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
// clear command issued
// maxigp1_writep (HBA_PORT__PxCI__CI__ADDR << 2, 0); // 'PxCI' - Clear 'Command issued' for slot 0 (the only one)
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // ST: 1 -> 0
repeat (20) @(posedge CLK);
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__TFEE__MASK); // clear this interrupt
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts
repeat (100) @(posedge CLK);
$finish;
end
// TESTBENCH_TITLE = "Got Identify";
TESTBENCH_TITLE = "Got D2HRFIS";
......@@ -1592,7 +1609,19 @@ initial begin //Device
dev.send_dma_activate (69, // input integer id;
status); // output integer status;
end else if (func_is_dev_read_dma_ext(dev.receive_data[0])) begin
`ifdef SEND_READ_ERROR
dev.send_D2HR(70, // same data as received from bad block read (HDD)
1, // irq,
8'h25, // status
8'h40, // error
8'h08, // device
24'h8023b1, // lba_low
24'h000008, // lba_high
16'h0001, // count
status); // output: result status
DEVICE_TITLE = "Device sent ERROR (bad block)";
$display("[Dev-TB]: %s, status = 0x%x @%t", DEVICE_TITLE, status, $time);
`else
// dev.send_incrementing_data(70, // input integer id;
dev.send_incrementing_data_pause(70, // input integer id;
128, // number of dwords to send, later decode count field
......@@ -1612,7 +1641,7 @@ initial begin //Device
status); // output: result status
DEVICE_TITLE = "Device sent D2H FIS (DMA D2H over)";
$display("[Dev-TB]: %s, status = 0x%x @%t", DEVICE_TITLE, status, $time);
`endif
end else if (func_is_h2d_data(dev.receive_data[0])) begin
DEVICE_TITLE = "Got H2D data";
$display("[Dev-TB]: %s @%t", DEVICE_TITLE, $time);
......
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