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x393_sata
Commit 2d189c2d authored by Andrey Filippov's avatar Andrey Filippov
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Synchronized to last known working version

parent 8a819cb8
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ahci/ahci_ctrl_stat.v
View file @ 2d189c2d
/*******************************************************************************
* Module: ahci_ctrl_stat
* Date:2016-01-12
* Author: andrey
* Author: Andrey Filippov
* Description: Copy of significant register fields, updating them in
* axi_ahci_regs registers (software accessible)
*
......
ahci/ahci_dma_rd_stuff.v
View file @ 2d189c2d
/*******************************************************************************
* Module: ahci_dma_rd_stuff
* Date:2016-01-01
* Author: andrey
* Author: Andrey Filippov
* Description: Stuff DWORD data with missing words into continuous 32-bit data
*
* Copyright (c) 2016 Elphel, Inc .
......
ahci/ahci_fis_transmit.v
View file @ 2d189c2d
/*******************************************************************************
* Module: ahci_fis_transmit
* Date:2016-01-07
* Author: andrey
* Author: Andrey Filippov
* Description: Fetches commands, command tables, creates/sends FIS
*
* Copyright (c) 2016 Elphel, Inc .
......
ahci/ahci_fsm.v
View file @ 2d189c2d
/*******************************************************************************
* Module: ahci_fsm
* Date:2016-01-10
* Author: andrey
* Author: Andrey Filippov
* Description: AHCI host+port0 state machine
*
* Copyright (c) 2016 Elphel, Inc .
......
ahci/ahci_sata_layers.v
View file @ 2d189c2d
/*******************************************************************************
* Module: ahci_sata_layers
* Date:2016-01-19
* Author: andrey
* Author: Andrey Filippov
* Description: Link and PHY SATA layers
*
* Copyright (c) 2016 Elphel, Inc .
......
ahci/axi_ahci_regs.v
View file @ 2d189c2d
......@@ -327,8 +327,8 @@ module axi_ahci_regs#(
end
/// always @ (hba_clk) begin
always @(posedge hba_clk) begin
//// always @ (hba_clk) begin
always @ (posedge aclk) begin
was_hba_rst_r <= {was_hba_rst_aclk, was_hba_rst_r[2:1]};
was_port_rst_r <= {was_port_rst_aclk, was_port_rst_r[2:1]};
end
......
ahci/axi_hp_abort.v
View file @ 2d189c2d
/*******************************************************************************
* Module: axi_hp_abort
* Date:2016-02-07
* Author: andrey
* Author: Andrey Filippov
* Description: Trying to gracefully reset AXI HP after aborted transmission
* For read channel - just keep afi_rready on until RD FIFO is empty (afi_rcount ==0)
* For write - keep track aof all what was sent so far, assuming aw is always ahead of w
......
ahci/freq_meter.v
View file @ 2d189c2d
/*******************************************************************************
* Module: freq_meter
* Date:2016-02-13
* Author: andrey
* Author: Andrey Filippov
* Description: Measure device clock frequency to set the local clock
*
* Copyright (c) 2016 Elphel, Inc .
......
includes/ahci_defaults.vh
View file @ 2d189c2d
......@@ -2,6 +2,6 @@
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h000000000000000000000000000000000000000001010003001000000001FFFE)
, .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
includes/ahci_localparams.vh
View file @ 2d189c2d
......@@ -97,7 +97,7 @@
// RO: HBA Revision ID
localparam PCI_Header__RID__RID__ADDR = 'h62;
localparam PCI_Header__RID__RID__MASK = 'hff;
localparam PCI_Header__RID__RID__DFLT = 'h3;
localparam PCI_Header__RID__RID__DFLT = 'h2;
// RO: Base Class Code: 1 - Mass Storage Device
localparam PCI_Header__CC__BCC__ADDR = 'h62;
localparam PCI_Header__CC__BCC__MASK = 'hff000000;
......
includes/tasks_tests_memory.vh
View file @ 2d189c2d
/*******************************************************************************
* Module: tasks_tests_memory
* Date:2015-08-01
* Author: andrey
* Author: Andrey Filippov
* Description: Top-level tasks for testing memory subsystem functionality
*
* Copyright (c) 2015 Elphel, Inc .
......@@ -43,9 +43,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
......@@ -54,9 +54,9 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITELEV_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 1, 32, 1 ); // chn=0, page=1, number of 32-bit words=32, wait_done
// task wait_read_queue_empty; - alternative way to check fo empty read queue
......@@ -74,9 +74,9 @@ task test_read_pattern; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_PATTERN_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 2, 32, 1 ); // chn=0, page=2, number of 32-bit words=32, wait_done
end
......@@ -88,9 +88,9 @@ task test_write_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
WRITE_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
0, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
1, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
// tempoary - for debugging:
// wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
end
......@@ -101,21 +101,21 @@ task test_read_block; // SuppressThisWarning VEditor - may be unused
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
3, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
2, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
READ_BLOCK_OFFSET, // input [9:0] seq_addr; // sequence start address
1, // input [1:0] page; // buffer page number
0, // input urgent; // high priority request (only for competion with other channels, wiil not pass in this FIFO)
0, // input urgent; // high priority request (only for competition with other channels, will not pass in this FIFO)
0, // input chn; // channel buffer to use: 0 - memory read, 1 - memory write
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
`PS_PIO_WAIT_COMPLETE );// wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
wait_ps_pio_done(DEFAULT_STATUS_MODE,1); // wait previous memory transaction finished before changing delays (effective immediately)
read_block_buf_chn (0, 3, 256, 1 ); // chn=0, page=3, number of 32-bit words=256, wait_done
end
......
includes/x393_parameters.vh
View file @ 2d189c2d
......@@ -332,7 +332,7 @@
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locations) relative to SENSOR_GROUP_ADDR
parameter SENSI2C_STATUS_REG_BASE = 'h20, // 4 locations" x20, x22, x24, x26
......
includes/x393_tasks_ps_pio.vh
View file @ 2d189c2d
......@@ -37,7 +37,7 @@ task schedule_ps_pio; // schedule software-control memory operation (may need to
input [1:0] page; // buffer page number
input urgent; // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
input chn; // channel buffer to use: 0 - memory read, 1 - memory write
input wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
input wait_complete; // Do not request a new transaction from the scheduler until previous memory transaction is finished
begin
// wait_ps_pio_ready(DEFAULT_STATUS_MODE); // wait FIFO not half full
write_contol_register(MCNTRL_PS_ADDR + MCNTRL_PS_CMD, {17'b0,wait_complete,chn,urgent,page,seq_addr});
......
py393sata/.project
View file @ 2d189c2d
......@@ -14,4 +14,11 @@
<natures>
<nature>org.python.pydev.pythonNature</nature>
</natures>
<linkedResources>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/eyesis/git/elphel393/fpga-elphel/x393_sata/py393sata/vivado_logs/VivadoSynthesis-20161206185119051.log</location>
</link>
</linkedResources>
</projectDescription>
py393sata/create_ahci_registers.py
View file @ 2d189c2d
......@@ -27,8 +27,8 @@ __status__ = "Development"
#import sys
# All unspecified ranges/fields default to fT:RO, fC:0 (readonly, reset value = 0)
#RID = 0x02 # Revision ID (use for bitstream version)
RID = 0x03 # Revision ID (use for bitstream version)
RID = 0x02 # Revision ID (use for bitstream version)
#RID = 0x03 # Revision ID (use for bitstream version)
VID = 0xfffe # What to use for non-PCI "vendorID"?
DID = 0x0001
SSVID = 0xfffe
......
py393sata/x393sata.py
View file @ 2d189c2d
......@@ -281,14 +281,14 @@ class x393sata(object):
else:
for d in data:
self.x393_mem.write_mem(FPGA_RST_CTRL,d)
def get_mem_buf_args(self, saddr=None, len=None):
def get_mem_buf_args(self, saddr=None, length=None):
#Is it really needed? Or use cache line size (32B), not PAGE_SIZE?
args=""
if (saddr is None) or (len is None):
if (saddr is None) or (length is None):
return ""
else:
eaddr = PAGE_SIZE * ((saddr+len) // PAGE_SIZE)
if ((saddr+len) % PAGE_SIZE):
eaddr = PAGE_SIZE * ((saddr+length) // PAGE_SIZE)
if ((saddr+length) % PAGE_SIZE):
eaddr += PAGE_SIZE
saddr = PAGE_SIZE * (saddr // PAGE_SIZE)
return "%d %d"%(saddr, eaddr-saddr )
......@@ -299,14 +299,14 @@ class x393sata(object):
return "_d2h"
elif direction.upper()[0] in "B":
return "_bidir"
def sync_for_cpu(self, direction, saddr=None, len=None):
def sync_for_cpu(self, direction, saddr=None, length=None):
with open (MEM_PATH + BUFFER_FOR_CPU + self._get_dma_dir_suffix(direction),"w") as f:
print (self.get_mem_buf_args(saddr, len),file=f)
print (self.get_mem_buf_args(saddr, length),file=f)
def sync_for_device(self, direction, saddr=None, len=None):
def sync_for_device(self, direction, saddr=None, length=None):
with open (MEM_PATH + BUFFER_FOR_DEVICE + self._get_dma_dir_suffix(direction),"w") as f:
print (self.get_mem_buf_args(saddr, len),file=f)
print (self.get_mem_buf_args(saddr, length),file=f)
'''
def flush_mem(self, saddr=None, len=None):
......@@ -368,13 +368,13 @@ class x393sata(object):
if not bitfile:
bitfile=DEFAULT_BITFILE
if quiet < 2:
print ("FPGA clock OFF")
print ("FPGA clock OFF")
self.x393_mem.write_mem(FPGA0_THR_CTRL,1)
if quiet < 2:
print ("Reset ON")
print ("Reset ON")
self.reset(0)
if quiet < 2:
print ("cat %s >%s"%(bitfile,FPGA_LOAD_BITSTREAM))
print ("cat %s >%s"%(bitfile,FPGA_LOAD_BITSTREAM))
if not self.DRY_MODE:
l=0
with open(bitfile, 'rb') as src, open(FPGA_LOAD_BITSTREAM, 'wb') as dst:
......@@ -414,22 +414,22 @@ class x393sata(object):
def set_zynq_esata(self):
self.vsc3304.connect_zynq_esata()
if self.DEBUG_MODE:
self.vsc3304.connection_status()
self.vsc3304.connection_status()
def set_zynq_ssata(self):
self.vsc3304.connect_zynq_ssata()
if self.DEBUG_MODE:
self.vsc3304.connection_status()
self.vsc3304.connection_status()
def set_esata_ssd(self):
self.vsc3304.connect_esata_ssd()
if self.DEBUG_MODE:
self.vsc3304.connection_status()
self.vsc3304.connection_status()
def set_debug_oscilloscope(self):
self.vsc3304.connect_debug()
if self.DEBUG_MODE:
self.vsc3304.connection_status()
self.vsc3304.connection_status()
def reinit_mux(self):
"""
......@@ -644,8 +644,8 @@ class x393sata(object):
(0x80 << 8) | # set C = 1
(ATA_IDFY << 16) | # Command = 0xEC (IDFY)
( 0 << 24)) # features = 0 ?
# All other 4 DWORDs are 0 for this command
# Set PRDT (single item) TODO: later check multiple small ones
# All other 4 DWORDs are 0 for this command
# Set PRDT (single item) TODO: later check multiple small ones
self.x393_mem.write_mem(COMMAND_ADDRESS + PRD_OFFSET + (0 << 2), DATAIN_ADDRESS + IDENTIFY_BUF)
prdt_int = 0
if prd_irqs:
......@@ -700,7 +700,7 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
#Wait interrupt
for r in range(10):
for _ in range(10):
istat = self.x393_mem.read_mem(self.get_reg_address('HBA_PORT__PxIS'))
if istat:
self.parse_register(group_range = ['HBA_PORT__PxIS'],
......@@ -819,7 +819,7 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
#Wait interrupt
for r in range(10):
for _ in range(10):
istat = self.x393_mem.read_mem(self.get_reg_address('HBA_PORT__PxIS'))
if istat:
self.parse_register(group_range = ['HBA_PORT__PxIS'],
......@@ -944,7 +944,7 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
#Wait interrupt
for r in range(10):
for _ in range(10):
istat = self.x393_mem.read_mem(self.get_reg_address('HBA_PORT__PxIS'))
if istat:
self.parse_register(group_range = ['HBA_PORT__PxIS'],
......@@ -1059,7 +1059,7 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
#Wait interrupt
for r in range(10):
for _ in range(10):
istat = self.x393_mem.read_mem(self.get_reg_address('HBA_PORT__PxIS'))
if istat:
self.parse_register(group_range = ['HBA_PORT__PxIS'],
......@@ -1174,7 +1174,7 @@ class x393sata(object):
print("_=mem.mem_dump (0x%x, 0x10,4)"%(COMMAND_ADDRESS))
self.x393_mem.mem_dump (COMMAND_ADDRESS, 0x20,4)
#Wait interrupt
for r in range(10):
for _ in range(10):
istat = self.x393_mem.read_mem(self.get_reg_address('HBA_PORT__PxIS'))
if istat:
self.parse_register(group_range = ['HBA_PORT__PxIS'],
......@@ -1449,7 +1449,7 @@ class x393sata(object):
if not write_mode is None:
mode = ((mode ^ ((write_mode & 0xf) << 4)) & (0xf << 4)) ^ mode
if not read_mode is None:
mode = ((mode ^ ((reade_mode & 0xf) << 0)) & (0xf << 0)) ^ mode
mode = ((mode ^ ((read_mode & 0xf) << 0)) & (0xf << 0)) ^ mode
self.x393_mem.write_mem(self.get_reg_address('HBA_PORT__AFI_CACHE'), mode)
return {'write':(mode >> 4) & 0xf, 'read':(mode >> 0) & 0xf}
......@@ -1474,6 +1474,7 @@ def init_sata():
sata.reinit_mux()
sata.configure(bitfile=None,
quiet=4) # 4 will be really quiet
print ("PCI_Header__RID = 0x%x"%(sata.x393_mem.read_mem(sata.get_reg_address('PCI_Header__RID'))))
sata.drp (0x20b,0x221) # bypass, clock align
#hex(sata.drp (0x20b))
......@@ -1496,6 +1497,25 @@ if __name__ == "__main__":
"""
x393sata.py
modprobe ahci_elphel &
sleep 2
echo 1 > /sys/devices/soc0/amba@0/80000000.elphel-ahci/load_module
cd /usr/local/bin; python
from __future__ import print_function
from __future__ import division
import x393sata
import x393_mem
mem = x393_mem.X393Mem(1,0,1)
sata = x393sata.x393sata()
hex(mem.read_mem(sata.get_reg_address('PCI_Header__RID')))
def get_MAC():
with open("/sys/class/net/eth0/address") as sysfile:
return sysfile.read()
......
x393_sata.bit
View file @ 2d189c2d
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