status update

# x393_sata

# x393_sata

SATA controller for x393 camera

SATA controller for x393 camera

Board: Zynq 7z30

FPGA: Kintex-7

# Current step:

# Current step:

Creating simple testbench structure, placing some register @ axi iface (+axi slave onto maxigp1), simulate them.

Connecting Ashwin's core (slow interface to the system is almost done, have to completely rewrite phy-level). Feels like making the phy works is going to require a lot of effort

To syntesize, try to access these registers (read+write)

# Going to do afterwards:

# Going to do afterwards:

Connect Ashwin's core and make it work at least somehow (write system level tests and application level rtl). Write host controller with ~same functionallity, check if it works with previously verified higher-level code.

Complete and test the 'current step'. Write host controller with ~same functionallity, check if it works with previously verified higher-level code.

And then to spin out the full-compatible functionallity (ideally somewhere to the level of ahci)

And then to spin out the full-compatible functionallity (ideally somewhere to the level of ahci)