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Commit 29d789db authored by Andrey Filippov's avatar Andrey Filippov
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Added compact input primitives logging and FPGA-based profiling of the host/device communication

parent 260e7464
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.project
View file @ 29d789db
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160307105520276.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160308235632422.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160307105520276.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160308235632422.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160307105520276.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160308235632422.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160307105701067.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160308235749196.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160307105701067.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160308235749196.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160307105701067.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160308235749196.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160307105701067.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160308235749196.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-route.dcp</name> <name>vivado_state/x393_sata-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160307105701067.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160308235749196.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160307105520276.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160308235632422.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ahci/ahci_fsm.v
View file @ 29d789db
...@@ -271,6 +271,7 @@ module ahci_fsm ...@@ -271,6 +271,7 @@ module ahci_fsm
wire fsm_next; wire fsm_next;
// reg fsm_next_r; // reg fsm_next_r;
reg fsm_actions; // processing actions reg fsm_actions; // processing actions
reg dis_actions; // disable actions during async jump
reg fsm_act_busy; reg fsm_act_busy;
reg [1:0] fsm_transitions; // processing transitions reg [1:0] fsm_transitions; // processing transitions
reg fsm_preload; // read first sequence data (2 cycles for regen) reg fsm_preload; // read first sequence data (2 cycles for regen)
...@@ -288,7 +289,7 @@ module ahci_fsm ...@@ -288,7 +289,7 @@ module ahci_fsm
wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done
wire fsm_last_act_w = pgm_data[17]; wire fsm_last_act_w = pgm_data[17];
wire fsm_pre_act_w = fsm_actions && fsm_next; // use it as CS for generated actions (registered) wire fsm_pre_act_w = !dis_actions && fsm_actions && fsm_next; // use it as CS for generated actions (registered)
reg [1:0] async_pend_r; // waiting to process cominit_got reg [1:0] async_pend_r; // waiting to process cominit_got
reg async_from_st; // change to multi-bit if there will be more sources for async transitions reg async_from_st; // change to multi-bit if there will be more sources for async transitions
...@@ -381,6 +382,11 @@ module ahci_fsm ...@@ -381,6 +382,11 @@ module ahci_fsm
else if (fsm_jump[2]) fsm_actions <= 1; else if (fsm_jump[2]) fsm_actions <= 1;
else if (fsm_last_act_w && fsm_next) fsm_actions <= 0; else if (fsm_last_act_w && fsm_next) fsm_actions <= 0;
if (hba_rst) dis_actions <= 0;
else if (|async_pend_r) dis_actions <= 1;
else if (fsm_jump[2]) dis_actions <= 0;
if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w; if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w;
if (hba_rst || pre_jump_w) fsm_transitions <= 0; if (hba_rst || pre_jump_w) fsm_transitions <= 0;
......
ahci/ahci_sata_layers.v
View file @ 29d789db
...@@ -308,8 +308,32 @@ assign debug_phy = debug_phy0; ...@@ -308,8 +308,32 @@ assign debug_phy = debug_phy0;
// .cominit_got (cominit_got), // output wire // .cominit_got (cominit_got), // output wire
// .comwake_got (serr_DW), // output wire // .comwake_got (serr_DW), // output wire
`ifdef DATASCOPE_INCOMING_RAW
assign datascope_di = {5'b0,debug_link[5],datascope0_di[25:0]};// aligns_pair tx assign datascope_di = {5'b0,debug_link[5],datascope0_di[25:0]};// aligns_pair tx
`else
// Mix transmitted alignes pair, but only to the closest group of 6 primitives
reg dbg_was_link5; // alignes pair sent
wire dbg_was_link5_xclk; // alignes pair sent
always @ (posedge datascope_clk) begin
if (dbg_was_link5_xclk) dbg_was_link5 <= 1;
else if (datascope_we) dbg_was_link5 <= 0;
end
pulse_cross_clock #(
.EXTRA_DLY(0)
) dbg_was_link5_i (
.rst (rst), // input
.src_clk (clk), // input
.dst_clk (datascope_clk), // input
.in_pulse (debug_link[5]), // input// is actually a two-cycle
.out_pulse (dbg_was_link5_xclk), // output
.busy() // output
);
assign datascope_di = {dbg_was_link5,datascope0_di[30:0]};// aligns_pair tx
`endif
link #( link #(
.DATA_BYTE_WIDTH(4) .DATA_BYTE_WIDTH(4)
) link ( ) link (
......
ahci/ahci_top.v
View file @ 29d789db
This diff is collapsed.
device/sata_device.v
View file @ 29d789db
...@@ -983,7 +983,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench ...@@ -983,7 +983,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Transmission is paused"; DEV_TITLE = "Transmission is paused";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time); $display("[Device] LINK: %s @%t", DEV_TITLE, $time);
linkSendPrim("HOLD"); linkSendPrim("HOLD");
xpause = xpause - 1; // xpause = xpause - 1;
end else begin end else begin
scrambler_value = scrambleFunc({16'b0,scrambler_value[31:16]}); scrambler_value = scrambleFunc({16'b0,scrambler_value[31:16]});
linkSendData(transmit_data[cnt] ^ scrambler_value); linkSendData(transmit_data[cnt] ^ scrambler_value);
......
host/gtx_wrap.v
View file @ 29d789db
This diff is collapsed.
host/link.v
View file @ 29d789db
...@@ -37,7 +37,8 @@ module link #( ...@@ -37,7 +37,8 @@ module link #(
// 4 = dword. 4-bytes aligned data transfers TODO 2 = word - easy, 8 = qword - difficult // 4 = dword. 4-bytes aligned data transfers TODO 2 = word - easy, 8 = qword - difficult
parameter DATA_BYTE_WIDTH = 4, parameter DATA_BYTE_WIDTH = 4,
`ifdef SIMULATION `ifdef SIMULATION
parameter ALIGNES_PERIOD = 10 // period of sending ALIGNp pairs // parameter ALIGNES_PERIOD = 10 // period of sending ALIGNp pairs
parameter ALIGNES_PERIOD = 100 // period of sending ALIGNp pairs
`else `else
parameter ALIGNES_PERIOD = 252 // period of sending ALIGNp pairs parameter ALIGNES_PERIOD = 252 // period of sending ALIGNp pairs
`endif `endif
......
includes/ahci_defaults.vh
View file @ 29d789db
, .INIT_00 (256'h0000000000000000000000000001030100000001000000008000000000240020) , .INIT_00 (256'h0000000000000000000000000001030100000001000000008000000000240020)
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800) , .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000) , .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000030000003300000000000000000000000000000000) , .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE) , .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000) , .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001) , .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
includes/ahci_localparams.vh
View file @ 29d789db
...@@ -793,5 +793,9 @@ ...@@ -793,5 +793,9 @@
// RW: Program address/data for programming AHCI state machine // RW: Program address/data for programming AHCI state machine
localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__ADDR = 'h5d; localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__ADDR = 'h5d;
localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__MASK = 'h3ffff; localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__MASK = 'h3ffff;
localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__DFLT = 'h3; localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__DFLT = 'h0;
// RW: 3-bit tag to add to the recorded timestamp
localparam HBA_PORT__PunchTime__TAG__ADDR = 'h5e;
localparam HBA_PORT__PunchTime__TAG__MASK = 'h7;
localparam HBA_PORT__PunchTime__TAG__DFLT = 'h0;
includes/ahci_types.vh
View file @ 29d789db
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
, .INIT_12 (256'h0000000000555555000000000000000000000000000000000000000000000000) , .INIT_12 (256'h0000000000555555000000000000000000000000000000000000000000000000)
, .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000A) , .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000A)
, .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D) , .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D)
, .INIT_17 (256'h5555555555555555555555555555555500010005555555550000000000005555) , .INIT_17 (256'h5555555555555555000000000000001500010005555555550000000000005555)
, .INIT_18 (256'h00000000000055550000000000000000AA820000001000140000000000000000) , .INIT_18 (256'h00000000000055550000000000000000AA820000001000140000000000000000)
, .INIT_1B (256'h0000000000005555000000000000000000000000000000000000000000000000) , .INIT_1B (256'h0000000000005555000000000000000000000000000000000000000000000000)
, .INIT_1C (256'h0000000000000000000000000000000000000000800100050000000000000000) , .INIT_1C (256'h0000000000000000000000000000000000000000800100050000000000000000)
py393sata/create_ahci_registers.py
View file @ 29d789db
...@@ -436,9 +436,13 @@ src=[{gN:"PCI_Header", gS: PCIHEAD, gE:PCIHEAD+0x3f, gD:" PCI header emulation w ...@@ -436,9 +436,13 @@ src=[{gN:"PCI_Header", gS: PCIHEAD, gE:PCIHEAD+0x3f, gD:" PCI header emulation w
[{ fS:25, fE:31, fT:RO, fC:0, fD:"Reserved"}, [{ fS:25, fE:31, fT:RO, fC:0, fD:"Reserved"},
{fN:"AnD", fS:24, fT:RW, fC:0, fD:"Address/not data for programming AHCI state machine"}, {fN:"AnD", fS:24, fT:RW, fC:0, fD:"Address/not data for programming AHCI state machine"},
{ fS:18, fE:23, fT:RO, fC:0, fD:"Reserved"}, { fS:18, fE:23, fT:RO, fC:0, fD:"Reserved"},
{fN:"PGM_AD",fS: 0, fE:17, fT:RW, fC:3, fD:"Program address/data for programming AHCI state machine"}, {fN:"PGM_AD",fS: 0, fE:17, fT:RW, fC:0, fD:"Program address/data for programming AHCI state machine"},
]}, ]},
{rN:"PxVS", rS:0x78, rE:0x7f, rD:"Other Port x Vendor Specific", rC: {rN:"PunchTime", rS:0x78, rE:0x7b, rD:"Record current time to the datascope", rC:
[{ fS:3, fE:31, fT:RO, fC:0, fD:"Reserved"},
{fN:"TAG", fS:0, fE:2, fT:RW, fC:0, fD:"3-bit tag to add to the recorded timestamp"},
]},
{rN:"PxVS", rS:0x7c, rE:0x7f, rD:"Other Port x Vendor Specific", rC:
[{ fT:RW, fC:0, fD:"Vendor-specific data - 96 bits"} [{ fT:RW, fC:0, fD:"Vendor-specific data - 96 bits"}
]}, ]},
......
system_defines.vh
View file @ 29d789db
...@@ -5,6 +5,7 @@ ...@@ -5,6 +5,7 @@
`define ALIGN_CLOCKS `define ALIGN_CLOCKS
`define STRAIGHT_XCLK `define STRAIGHT_XCLK
`define USE_DATASCOPE `define USE_DATASCOPE
// `define DATASCOPE_INCOMING_RAW
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
`define AHCI_SATA 1 `define AHCI_SATA 1
`define DEBUG_ELASTIC `define DEBUG_ELASTIC
......
tb/tb_ahci.tf
View file @ 29d789db
...@@ -1347,6 +1347,7 @@ initial begin //Host ...@@ -1347,6 +1347,7 @@ initial begin //Host
maxigp1_print (HBA_PORT__PxSERR__DIAG__X__ADDR << 2,"re-read: HBA_PORT__PxSERR"); // maxigp1_print (HBA_PORT__PxSERR__DIAG__X__ADDR << 2,"re-read: HBA_PORT__PxSERR"); //
//HBA_PORT__PxIS__DHRS__ADDR //HBA_PORT__PxIS__DHRS__ADDR
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 1); // Record current time in datascope with a 3-bit tag==1
maxigp1_print (PXSIG_OFFS32 << 2,"PXSIG_OFFS32"); maxigp1_print (PXSIG_OFFS32 << 2,"PXSIG_OFFS32");
maxigp1_print (PXTFD_OFFS32 << 2,"PXTFD_OFFS32"); maxigp1_print (PXTFD_OFFS32 << 2,"PXTFD_OFFS32");
...@@ -1366,18 +1367,32 @@ initial begin //Host ...@@ -1366,18 +1367,32 @@ initial begin //Host
maxigp1_print (HBA_PORT__PxSSTS__DET__ADDR << 2,"HBA_PORT__PxSSTS__DET__ADDR"); maxigp1_print (HBA_PORT__PxSSTS__DET__ADDR << 2,"HBA_PORT__PxSSTS__DET__ADDR");
drp_write ('h20b, 'hc401); // bypass, clock align, invert xclk, arm datascope1
// drp_write ('h20b, 'h8401); // bypass, clock align and invert xclk that will stop datascope1
/*
`ifdef USE_DATASCOPE
parameter DATASCOPE_START_BIT = 14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
parameter DATASCOPE_POST_MEAS = 256, // 16, // number of measurements to perform after event
`endif
*/
// setup_pio_read_identify_command_simple(512,1); // prdt interrupt for entry 0 // setup_pio_read_identify_command_simple(512,1); // prdt interrupt for entry 0
//// setup_pio_read_identify_command_simple(2560,1); // intentionally too long //// setup_pio_read_identify_command_simple(2560,1); // intentionally too long
/// setup_pio_read_identify_command_shifted(1); // prdt interrupt for entry 0 /// setup_pio_read_identify_command_shifted(1); // prdt interrupt for entry 0
/// setup_pio_read_identify_command_multi4(0,27,71,83); // No prdt interrupts /// setup_pio_read_identify_command_multi4(0,27,71,83); // No prdt interrupts
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 2); // Record current time in datascope with a 3-bit tag
setup_dma_read_ext_command_multi4(0,64,64,64); // No prdt interrupts, 4 64-word chunks setup_dma_read_ext_command_multi4(0,64,64,64); // No prdt interrupts, 4 64-word chunks
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 3); // Record current time in datascope with a 3-bit tag
/// setup_pio_read_identify_command_multi4(1,27,64,83); // prdt interrupt for entry 0 /// setup_pio_read_identify_command_multi4(1,27,64,83); // prdt interrupt for entry 0
/// setup_pio_read_identify_command_multi4(1,64,63,64); // prdt interrupt for entry 0 // last used /// setup_pio_read_identify_command_multi4(1,64,63,64); // prdt interrupt for entry 0 // last used
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
`ifdef TEST_ABORT_COMMAND `ifdef TEST_ABORT_COMMAND
TESTBENCH_TITLE = "ABORT start";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
// Abort command by clearing ST // Abort command by clearing ST
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, 0-> ST maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, 0-> ST
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
...@@ -1386,6 +1401,8 @@ initial begin //Host ...@@ -1386,6 +1401,8 @@ initial begin //Host
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
// maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, 0-> ST // maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, 0-> ST
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
TESTBENCH_TITLE = "ABORT end";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
`endif `endif
// TODO change to ifdef - this is for identify command // TODO change to ifdef - this is for identify command
...@@ -1395,8 +1412,10 @@ initial begin //Host ...@@ -1395,8 +1412,10 @@ initial begin //Host
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow DHR only interrupts (PIO setup) maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow DHR only interrupts (PIO setup)
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // clear that interrupt maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // clear that interrupt
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 3); // Record current time in datascope with a 3-bit tag
wait (IRQ); wait (IRQ);
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 4); // Record current time in datascope with a 3-bit tag
// TESTBENCH_TITLE = "Got Identify"; // TESTBENCH_TITLE = "Got Identify";
TESTBENCH_TITLE = "Got D2HRFIS"; TESTBENCH_TITLE = "Got D2HRFIS";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time); $display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
...@@ -1406,10 +1425,11 @@ initial begin //Host ...@@ -1406,10 +1425,11 @@ initial begin //Host
wait (~IRQ); wait (~IRQ);
// Reset command with abort_dma // Reset command with abort_dma
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 5); // Record current time in datascope with a 3-bit tag
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // ST: 1 -> 0 maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // ST: 1 -> 0
repeat (50) @(posedge CLK); repeat (50) @(posedge CLK);
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK |HBA_PORT__PxCMD__ST__MASK); // ST: 0 -> 1 maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK |HBA_PORT__PxCMD__ST__MASK); // ST: 0 -> 1
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 6); // Record current time in datascope with a 3-bit tag
...@@ -1433,7 +1453,8 @@ initial begin //Host ...@@ -1433,7 +1453,8 @@ initial begin //Host
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow only D2H Register interrupts maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow only D2H Register interrupts
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts for port 0 (the only one) maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts for port 0 (the only one)
wait (~IRQ); wait (~IRQ);
TESTBENCH_TITLE = "Setting up Identify";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
setup_pio_read_identify_command_simple(512,1); // prdt interrupt for entry 0 setup_pio_read_identify_command_simple(512,1); // prdt interrupt for entry 0
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup) maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup)
...@@ -1445,6 +1466,7 @@ initial begin //Host ...@@ -1445,6 +1466,7 @@ initial begin //Host
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear PS interrupt maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear PS interrupt
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts
wait (~IRQ); wait (~IRQ);
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 7); // Record current time in datascope with a 3-bit tag
// end of the second identify insertion // end of the second identify insertion
......
tb_ahci_01.sav
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x393_sata.bit
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