Commit 260e7464 authored by Oleg Dzhimiev's avatar Oleg Dzhimiev


parent 9cd542ba
......@@ -9,7 +9,7 @@ if [ -z "$1" ]
install -d -v $1/usr/local/verilog/
install -d -v $1/usr/local/bin/
install -v -m 0755 py393sata/*.py $1/usr/local/bin/
install -v -m 0644 x393_sata.bit $1/usr/local/verilog/
install -v -m 0755 $SCRIPTPATH/py393sata/*.py $1/usr/local/bin/
install -v -m 0644 $SCRIPTPATH/x393_sata.bit $1/usr/local/verilog/
exit 0
\ No newline at end of file
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